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8c1aacad263798e11179fb8790ccb276f731ed15
[openocd.git] / src / flash / nor / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "imp.h"
29 #include "cfi.h"
30 #include "non_cfi.h"
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34
35
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
38
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
41
42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
43 {
44 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
45 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
46 };
47
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
51 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
52
53 /* fixup after reading cmdset 0002 primary query table */
54 static const struct cfi_fixup cfi_0002_fixups[] = {
55 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
61 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
63 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
64 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
65 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
66 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
67 {0, 0, NULL, NULL}
68 };
69
70 /* fixup after reading cmdset 0001 primary query table */
71 static const struct cfi_fixup cfi_0001_fixups[] = {
72 {0, 0, NULL, NULL}
73 };
74
75 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
76 {
77 struct cfi_flash_bank *cfi_info = bank->driver_priv;
78 const struct cfi_fixup *f;
79
80 for (f = fixups; f->fixup; f++)
81 {
82 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
83 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
84 {
85 f->fixup(bank, f->param);
86 }
87 }
88 }
89
90 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
91 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
92 {
93 struct cfi_flash_bank *cfi_info = bank->driver_priv;
94
95 if (cfi_info->x16_as_x8) offset *= 2;
96
97 /* while the sector list isn't built, only accesses to sector 0 work */
98 if (sector == 0)
99 return bank->base + offset * bank->bus_width;
100 else
101 {
102 if (!bank->sectors)
103 {
104 LOG_ERROR("BUG: sector list not yet built");
105 exit(-1);
106 }
107 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
108 }
109 }
110
111 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
112 {
113 int i;
114
115 /* clear whole buffer, to ensure bits that exceed the bus_width
116 * are set to zero
117 */
118 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
119 cmd_buf[i] = 0;
120
121 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
122 {
123 for (i = bank->bus_width; i > 0; i--)
124 {
125 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
126 }
127 }
128 else
129 {
130 for (i = 1; i <= bank->bus_width; i++)
131 {
132 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
133 }
134 }
135 }
136
137 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
138 {
139 uint8_t command[CFI_MAX_BUS_WIDTH];
140
141 cfi_command(bank, cmd, command);
142 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
143 }
144
145 /* read unsigned 8-bit value from the bank
146 * flash banks are expected to be made of similar chips
147 * the query result should be the same for all
148 */
149 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
150 {
151 struct target *target = bank->target;
152 uint8_t data[CFI_MAX_BUS_WIDTH];
153
154 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
155
156 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
157 return data[0];
158 else
159 return data[bank->bus_width - 1];
160 }
161
162 /* read unsigned 8-bit value from the bank
163 * in case of a bank made of multiple chips,
164 * the individual values are ORed
165 */
166 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
167 {
168 struct target *target = bank->target;
169 uint8_t data[CFI_MAX_BUS_WIDTH];
170 int i;
171
172 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
173
174 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
175 {
176 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
177 data[0] |= data[i];
178
179 return data[0];
180 }
181 else
182 {
183 uint8_t value = 0;
184 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
185 value |= data[bank->bus_width - 1 - i];
186
187 return value;
188 }
189 }
190
191 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
192 {
193 struct target *target = bank->target;
194 struct cfi_flash_bank *cfi_info = bank->driver_priv;
195 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
196
197 if (cfi_info->x16_as_x8)
198 {
199 uint8_t i;
200 for (i = 0;i < 2;i++)
201 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
202 &data[i*bank->bus_width]);
203 }
204 else
205 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
206
207 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
208 return data[0] | data[bank->bus_width] << 8;
209 else
210 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
211 }
212
213 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
214 {
215 struct target *target = bank->target;
216 struct cfi_flash_bank *cfi_info = bank->driver_priv;
217 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
218
219 if (cfi_info->x16_as_x8)
220 {
221 uint8_t i;
222 for (i = 0;i < 4;i++)
223 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
224 &data[i*bank->bus_width]);
225 }
226 else
227 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
228
229 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
230 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
231 else
232 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
233 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
234 }
235
236 static int cfi_reset(struct flash_bank *bank)
237 {
238 struct cfi_flash_bank *cfi_info = bank->driver_priv;
239 int retval = ERROR_OK;
240
241 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
242 {
243 return retval;
244 }
245
246 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
247 {
248 return retval;
249 }
250
251 if (cfi_info->manufacturer == 0x20 &&
252 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
253 {
254 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
255 * so we send an extra 0xF0 reset to fix the bug */
256 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
257 {
258 return retval;
259 }
260 }
261
262 return retval;
263 }
264
265 static void cfi_intel_clear_status_register(struct flash_bank *bank)
266 {
267 struct target *target = bank->target;
268
269 if (target->state != TARGET_HALTED)
270 {
271 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
272 exit(-1);
273 }
274
275 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
276 }
277
278 static uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
279 {
280 uint8_t status;
281
282 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
283 {
284 LOG_DEBUG("status: 0x%x", status);
285 alive_sleep(1);
286 }
287
288 /* mask out bit 0 (reserved) */
289 status = status & 0xfe;
290
291 LOG_DEBUG("status: 0x%x", status);
292
293 if ((status & 0x80) != 0x80)
294 {
295 LOG_ERROR("timeout while waiting for WSM to become ready");
296 }
297 else if (status != 0x80)
298 {
299 LOG_ERROR("status register: 0x%x", status);
300 if (status & 0x2)
301 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
302 if (status & 0x4)
303 LOG_ERROR("Program suspended");
304 if (status & 0x8)
305 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
306 if (status & 0x10)
307 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
308 if (status & 0x20)
309 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
310 if (status & 0x40)
311 LOG_ERROR("Block Erase Suspended");
312
313 cfi_intel_clear_status_register(bank);
314 }
315
316 return status;
317 }
318
319 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
320 {
321 uint8_t status, oldstatus;
322 struct cfi_flash_bank *cfi_info = bank->driver_priv;
323
324 oldstatus = cfi_get_u8(bank, 0, 0x0);
325
326 do {
327 status = cfi_get_u8(bank, 0, 0x0);
328 if ((status ^ oldstatus) & 0x40) {
329 if (status & cfi_info->status_poll_mask & 0x20) {
330 oldstatus = cfi_get_u8(bank, 0, 0x0);
331 status = cfi_get_u8(bank, 0, 0x0);
332 if ((status ^ oldstatus) & 0x40) {
333 LOG_ERROR("dq5 timeout, status: 0x%x", status);
334 return(ERROR_FLASH_OPERATION_FAILED);
335 } else {
336 LOG_DEBUG("status: 0x%x", status);
337 return(ERROR_OK);
338 }
339 }
340 } else { /* no toggle: finished, OK */
341 LOG_DEBUG("status: 0x%x", status);
342 return(ERROR_OK);
343 }
344
345 oldstatus = status;
346 alive_sleep(1);
347 } while (timeout-- > 0);
348
349 LOG_ERROR("timeout, status: 0x%x", status);
350
351 return(ERROR_FLASH_BUSY);
352 }
353
354 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
355 {
356 int retval;
357 struct cfi_flash_bank *cfi_info = bank->driver_priv;
358 struct cfi_intel_pri_ext *pri_ext;
359
360 if (cfi_info->pri_ext)
361 free(cfi_info->pri_ext);
362
363 pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
364 if (pri_ext == NULL)
365 {
366 LOG_ERROR("Out of memory");
367 return ERROR_FAIL;
368 }
369 cfi_info->pri_ext = pri_ext;
370
371 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
372 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
373 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
374
375 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
376 {
377 if ((retval = cfi_reset(bank)) != ERROR_OK)
378 {
379 return retval;
380 }
381 LOG_ERROR("Could not read bank flash bank information");
382 return ERROR_FLASH_BANK_INVALID;
383 }
384
385 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
386 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
387
388 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
389
390 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
391 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
392 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
393
394 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
395 pri_ext->feature_support,
396 pri_ext->suspend_cmd_support,
397 pri_ext->blk_status_reg_mask);
398
399 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
400 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
401
402 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
403 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
404 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
405
406 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
407 if (pri_ext->num_protection_fields != 1)
408 {
409 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
410 }
411
412 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
413 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
414 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
415
416 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
417
418 return ERROR_OK;
419 }
420
421 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
422 {
423 int retval;
424 struct cfi_flash_bank *cfi_info = bank->driver_priv;
425 struct cfi_spansion_pri_ext *pri_ext;
426
427 if (cfi_info->pri_ext)
428 free(cfi_info->pri_ext);
429
430 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
431 if (pri_ext == NULL)
432 {
433 LOG_ERROR("Out of memory");
434 return ERROR_FAIL;
435 }
436 cfi_info->pri_ext = pri_ext;
437
438 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
439 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
440 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
441
442 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
443 {
444 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
445 {
446 return retval;
447 }
448 LOG_ERROR("Could not read spansion bank information");
449 return ERROR_FLASH_BANK_INVALID;
450 }
451
452 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
453 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
454
455 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
456
457 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
458 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
459 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
460 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
461 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
462 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
463 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
464 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
465 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
466 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
467 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
468
469 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
470 pri_ext->EraseSuspend, pri_ext->BlkProt);
471
472 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
473 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
474
475 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
476
477
478 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
479 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
480 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
481
482 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
483
484 /* default values for implementation specific workarounds */
485 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
486 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
487 pri_ext->_reversed_geometry = 0;
488
489 return ERROR_OK;
490 }
491
492 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
493 {
494 int retval;
495 struct cfi_atmel_pri_ext atmel_pri_ext;
496 struct cfi_flash_bank *cfi_info = bank->driver_priv;
497 struct cfi_spansion_pri_ext *pri_ext;
498
499 if (cfi_info->pri_ext)
500 free(cfi_info->pri_ext);
501
502 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
503 if (pri_ext == NULL)
504 {
505 LOG_ERROR("Out of memory");
506 return ERROR_FAIL;
507 }
508
509 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
510 * but a different primary extended query table.
511 * We read the atmel table, and prepare a valid AMD/Spansion query table.
512 */
513
514 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
515
516 cfi_info->pri_ext = pri_ext;
517
518 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
519 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
520 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
521
522 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
523 {
524 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
525 {
526 return retval;
527 }
528 LOG_ERROR("Could not read atmel bank information");
529 return ERROR_FLASH_BANK_INVALID;
530 }
531
532 pri_ext->pri[0] = atmel_pri_ext.pri[0];
533 pri_ext->pri[1] = atmel_pri_ext.pri[1];
534 pri_ext->pri[2] = atmel_pri_ext.pri[2];
535
536 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
537 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
538
539 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
540
541 pri_ext->major_version = atmel_pri_ext.major_version;
542 pri_ext->minor_version = atmel_pri_ext.minor_version;
543
544 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
545 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
546 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
547 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
548
549 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
550 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
551
552 if (atmel_pri_ext.features & 0x02)
553 pri_ext->EraseSuspend = 2;
554
555 if (atmel_pri_ext.bottom_boot)
556 pri_ext->TopBottom = 2;
557 else
558 pri_ext->TopBottom = 3;
559
560 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
561 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
562
563 return ERROR_OK;
564 }
565
566 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
567 {
568 struct cfi_flash_bank *cfi_info = bank->driver_priv;
569
570 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
571 {
572 return cfi_read_atmel_pri_ext(bank);
573 }
574 else
575 {
576 return cfi_read_spansion_pri_ext(bank);
577 }
578 }
579
580 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
581 {
582 int printed;
583 struct cfi_flash_bank *cfi_info = bank->driver_priv;
584 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
585
586 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
587 buf += printed;
588 buf_size -= printed;
589
590 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
591 pri_ext->pri[1], pri_ext->pri[2],
592 pri_ext->major_version, pri_ext->minor_version);
593 buf += printed;
594 buf_size -= printed;
595
596 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
597 (pri_ext->SiliconRevision) >> 2,
598 (pri_ext->SiliconRevision) & 0x03);
599 buf += printed;
600 buf_size -= printed;
601
602 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
603 pri_ext->EraseSuspend,
604 pri_ext->BlkProt);
605 buf += printed;
606 buf_size -= printed;
607
608 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
609 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
610 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
611
612 return ERROR_OK;
613 }
614
615 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
616 {
617 int printed;
618 struct cfi_flash_bank *cfi_info = bank->driver_priv;
619 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
620
621 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
622 buf += printed;
623 buf_size -= printed;
624
625 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
626 buf += printed;
627 buf_size -= printed;
628
629 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
630 buf += printed;
631 buf_size -= printed;
632
633 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
634 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
635 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
636 buf += printed;
637 buf_size -= printed;
638
639 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
640
641 return ERROR_OK;
642 }
643
644 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
645 */
646 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
647 {
648 struct cfi_flash_bank *cfi_info;
649
650 if (CMD_ARGC < 6)
651 {
652 LOG_WARNING("incomplete flash_bank cfi configuration");
653 return ERROR_FLASH_BANK_INVALID;
654 }
655
656 /* both widths must:
657 * - not exceed max value;
658 * - not be null;
659 * - be equal to a power of 2.
660 * bus must be wide enought to hold one chip */
661 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
662 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
663 || (bank->chip_width == 0)
664 || (bank->bus_width == 0)
665 || (bank->chip_width & (bank->chip_width - 1))
666 || (bank->bus_width & (bank->bus_width - 1))
667 || (bank->chip_width > bank->bus_width))
668 {
669 LOG_ERROR("chip and bus width have to specified in bytes");
670 return ERROR_FLASH_BANK_INVALID;
671 }
672
673 cfi_info = malloc(sizeof(struct cfi_flash_bank));
674 cfi_info->probed = 0;
675 cfi_info->erase_region_info = 0;
676 cfi_info->pri_ext = NULL;
677 bank->driver_priv = cfi_info;
678
679 cfi_info->write_algorithm = NULL;
680
681 cfi_info->x16_as_x8 = 0;
682 cfi_info->jedec_probe = 0;
683 cfi_info->not_cfi = 0;
684
685 for (unsigned i = 6; i < CMD_ARGC; i++)
686 {
687 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
688 {
689 cfi_info->x16_as_x8 = 1;
690 }
691 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
692 {
693 cfi_info->jedec_probe = 1;
694 }
695 }
696
697 cfi_info->write_algorithm = NULL;
698
699 /* bank wasn't probed yet */
700 cfi_info->qry[0] = -1;
701
702 return ERROR_OK;
703 }
704
705 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
706 {
707 int retval;
708 struct cfi_flash_bank *cfi_info = bank->driver_priv;
709 int i;
710
711 cfi_intel_clear_status_register(bank);
712
713 for (i = first; i <= last; i++)
714 {
715 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
716 {
717 return retval;
718 }
719
720 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
721 {
722 return retval;
723 }
724
725 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
726 bank->sectors[i].is_erased = 1;
727 else
728 {
729 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
730 {
731 return retval;
732 }
733
734 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
735 return ERROR_FLASH_OPERATION_FAILED;
736 }
737 }
738
739 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
740 }
741
742 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
743 {
744 int retval;
745 struct cfi_flash_bank *cfi_info = bank->driver_priv;
746 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
747 int i;
748
749 for (i = first; i <= last; i++)
750 {
751 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
752 {
753 return retval;
754 }
755
756 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
757 {
758 return retval;
759 }
760
761 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
762 {
763 return retval;
764 }
765
766 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
767 {
768 return retval;
769 }
770
771 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
772 {
773 return retval;
774 }
775
776 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
777 {
778 return retval;
779 }
780
781 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
782 bank->sectors[i].is_erased = 1;
783 else
784 {
785 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
786 {
787 return retval;
788 }
789
790 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
791 return ERROR_FLASH_OPERATION_FAILED;
792 }
793 }
794
795 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
796 }
797
798 static int cfi_erase(struct flash_bank *bank, int first, int last)
799 {
800 struct cfi_flash_bank *cfi_info = bank->driver_priv;
801
802 if (bank->target->state != TARGET_HALTED)
803 {
804 LOG_ERROR("Target not halted");
805 return ERROR_TARGET_NOT_HALTED;
806 }
807
808 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
809 {
810 return ERROR_FLASH_SECTOR_INVALID;
811 }
812
813 if (cfi_info->qry[0] != 'Q')
814 return ERROR_FLASH_BANK_NOT_PROBED;
815
816 switch (cfi_info->pri_id)
817 {
818 case 1:
819 case 3:
820 return cfi_intel_erase(bank, first, last);
821 break;
822 case 2:
823 return cfi_spansion_erase(bank, first, last);
824 break;
825 default:
826 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
827 break;
828 }
829
830 return ERROR_OK;
831 }
832
833 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
834 {
835 int retval;
836 struct cfi_flash_bank *cfi_info = bank->driver_priv;
837 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
838 int retry = 0;
839 int i;
840
841 /* if the device supports neither legacy lock/unlock (bit 3) nor
842 * instant individual block locking (bit 5).
843 */
844 if (!(pri_ext->feature_support & 0x28))
845 return ERROR_FLASH_OPERATION_FAILED;
846
847 cfi_intel_clear_status_register(bank);
848
849 for (i = first; i <= last; i++)
850 {
851 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
852 {
853 return retval;
854 }
855 if (set)
856 {
857 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
858 {
859 return retval;
860 }
861 bank->sectors[i].is_protected = 1;
862 }
863 else
864 {
865 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
866 {
867 return retval;
868 }
869 bank->sectors[i].is_protected = 0;
870 }
871
872 /* instant individual block locking doesn't require reading of the status register */
873 if (!(pri_ext->feature_support & 0x20))
874 {
875 /* Clear lock bits operation may take up to 1.4s */
876 cfi_intel_wait_status_busy(bank, 1400);
877 }
878 else
879 {
880 uint8_t block_status;
881 /* read block lock bit, to verify status */
882 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
883 {
884 return retval;
885 }
886 block_status = cfi_get_u8(bank, i, 0x2);
887
888 if ((block_status & 0x1) != set)
889 {
890 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
891 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
892 {
893 return retval;
894 }
895 cfi_intel_wait_status_busy(bank, 10);
896
897 if (retry > 10)
898 return ERROR_FLASH_OPERATION_FAILED;
899 else
900 {
901 i--;
902 retry++;
903 }
904 }
905 }
906 }
907
908 /* if the device doesn't support individual block lock bits set/clear,
909 * all blocks have been unlocked in parallel, so we set those that should be protected
910 */
911 if ((!set) && (!(pri_ext->feature_support & 0x20)))
912 {
913 /* FIX!!! this code path is broken!!!
914 *
915 * The correct approach is:
916 *
917 * 1. read out current protection status
918 *
919 * 2. override read out protection status w/unprotected.
920 *
921 * 3. re-protect what should be protected.
922 *
923 */
924 for (i = 0; i < bank->num_sectors; i++)
925 {
926 if (bank->sectors[i].is_protected == 1)
927 {
928 cfi_intel_clear_status_register(bank);
929
930 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
931 {
932 return retval;
933 }
934
935 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
936 {
937 return retval;
938 }
939
940 cfi_intel_wait_status_busy(bank, 100);
941 }
942 }
943 }
944
945 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
946 }
947
948 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
949 {
950 struct cfi_flash_bank *cfi_info = bank->driver_priv;
951
952 if (bank->target->state != TARGET_HALTED)
953 {
954 LOG_ERROR("Target not halted");
955 return ERROR_TARGET_NOT_HALTED;
956 }
957
958 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
959 {
960 LOG_ERROR("Invalid sector range");
961 return ERROR_FLASH_SECTOR_INVALID;
962 }
963
964 if (cfi_info->qry[0] != 'Q')
965 return ERROR_FLASH_BANK_NOT_PROBED;
966
967 switch (cfi_info->pri_id)
968 {
969 case 1:
970 case 3:
971 return cfi_intel_protect(bank, set, first, last);
972 break;
973 default:
974 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
975 return ERROR_FAIL;
976 }
977 }
978
979 /* Convert code image to target endian */
980 /* FIXME create general block conversion fcts in target.c?) */
981 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
982 {
983 uint32_t i;
984 for (i = 0; i< count; i++)
985 {
986 target_buffer_set_u32(target, dest, *src);
987 dest += 4;
988 src++;
989 }
990 }
991
992 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
993 {
994 struct target *target = bank->target;
995
996 uint8_t buf[CFI_MAX_BUS_WIDTH];
997 cfi_command(bank, cmd, buf);
998 switch (bank->bus_width)
999 {
1000 case 1 :
1001 return buf[0];
1002 break;
1003 case 2 :
1004 return target_buffer_get_u16(target, buf);
1005 break;
1006 case 4 :
1007 return target_buffer_get_u32(target, buf);
1008 break;
1009 default :
1010 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1011 return 0;
1012 }
1013 }
1014
1015 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1016 {
1017 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1018 struct target *target = bank->target;
1019 struct reg_param reg_params[7];
1020 struct arm_algorithm armv4_5_info;
1021 struct working_area *source;
1022 uint32_t buffer_size = 32768;
1023 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1024
1025 /* algorithm register usage:
1026 * r0: source address (in RAM)
1027 * r1: target address (in Flash)
1028 * r2: count
1029 * r3: flash write command
1030 * r4: status byte (returned to host)
1031 * r5: busy test pattern
1032 * r6: error test pattern
1033 */
1034
1035 static const uint32_t word_32_code[] = {
1036 0xe4904004, /* loop: ldr r4, [r0], #4 */
1037 0xe5813000, /* str r3, [r1] */
1038 0xe5814000, /* str r4, [r1] */
1039 0xe5914000, /* busy: ldr r4, [r1] */
1040 0xe0047005, /* and r7, r4, r5 */
1041 0xe1570005, /* cmp r7, r5 */
1042 0x1afffffb, /* bne busy */
1043 0xe1140006, /* tst r4, r6 */
1044 0x1a000003, /* bne done */
1045 0xe2522001, /* subs r2, r2, #1 */
1046 0x0a000001, /* beq done */
1047 0xe2811004, /* add r1, r1 #4 */
1048 0xeafffff2, /* b loop */
1049 0xeafffffe /* done: b -2 */
1050 };
1051
1052 static const uint32_t word_16_code[] = {
1053 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1054 0xe1c130b0, /* strh r3, [r1] */
1055 0xe1c140b0, /* strh r4, [r1] */
1056 0xe1d140b0, /* busy ldrh r4, [r1] */
1057 0xe0047005, /* and r7, r4, r5 */
1058 0xe1570005, /* cmp r7, r5 */
1059 0x1afffffb, /* bne busy */
1060 0xe1140006, /* tst r4, r6 */
1061 0x1a000003, /* bne done */
1062 0xe2522001, /* subs r2, r2, #1 */
1063 0x0a000001, /* beq done */
1064 0xe2811002, /* add r1, r1 #2 */
1065 0xeafffff2, /* b loop */
1066 0xeafffffe /* done: b -2 */
1067 };
1068
1069 static const uint32_t word_8_code[] = {
1070 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1071 0xe5c13000, /* strb r3, [r1] */
1072 0xe5c14000, /* strb r4, [r1] */
1073 0xe5d14000, /* busy ldrb r4, [r1] */
1074 0xe0047005, /* and r7, r4, r5 */
1075 0xe1570005, /* cmp r7, r5 */
1076 0x1afffffb, /* bne busy */
1077 0xe1140006, /* tst r4, r6 */
1078 0x1a000003, /* bne done */
1079 0xe2522001, /* subs r2, r2, #1 */
1080 0x0a000001, /* beq done */
1081 0xe2811001, /* add r1, r1 #1 */
1082 0xeafffff2, /* b loop */
1083 0xeafffffe /* done: b -2 */
1084 };
1085 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1086 const uint32_t *target_code_src;
1087 uint32_t target_code_size;
1088 int retval = ERROR_OK;
1089
1090
1091 cfi_intel_clear_status_register(bank);
1092
1093 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1094 armv4_5_info.core_mode = ARM_MODE_SVC;
1095 armv4_5_info.core_state = ARM_STATE_ARM;
1096
1097 /* If we are setting up the write_algorith, we need target_code_src */
1098 /* if not we only need target_code_size. */
1099
1100 /* However, we don't want to create multiple code paths, so we */
1101 /* do the unecessary evaluation of target_code_src, which the */
1102 /* compiler will probably nicely optimize away if not needed */
1103
1104 /* prepare algorithm code for target endian */
1105 switch (bank->bus_width)
1106 {
1107 case 1 :
1108 target_code_src = word_8_code;
1109 target_code_size = sizeof(word_8_code);
1110 break;
1111 case 2 :
1112 target_code_src = word_16_code;
1113 target_code_size = sizeof(word_16_code);
1114 break;
1115 case 4 :
1116 target_code_src = word_32_code;
1117 target_code_size = sizeof(word_32_code);
1118 break;
1119 default:
1120 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1121 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1122 }
1123
1124 /* flash write code */
1125 if (!cfi_info->write_algorithm)
1126 {
1127 if (target_code_size > sizeof(target_code))
1128 {
1129 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1130 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1131 }
1132 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1133
1134 /* Get memory for block write handler */
1135 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1136 if (retval != ERROR_OK)
1137 {
1138 LOG_WARNING("No working area available, can't do block memory writes");
1139 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1140 };
1141
1142 /* write algorithm code to working area */
1143 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1144 if (retval != ERROR_OK)
1145 {
1146 LOG_ERROR("Unable to write block write code to target");
1147 goto cleanup;
1148 }
1149 }
1150
1151 /* Get a workspace buffer for the data to flash starting with 32k size.
1152 Half size until buffer would be smaller 256 Bytem then fail back */
1153 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1154 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1155 {
1156 buffer_size /= 2;
1157 if (buffer_size <= 256)
1158 {
1159 LOG_WARNING("no large enough working area available, can't do block memory writes");
1160 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1161 goto cleanup;
1162 }
1163 };
1164
1165 /* setup algo registers */
1166 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1167 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1168 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1169 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1170 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1171 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1172 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1173
1174 /* prepare command and status register patterns */
1175 write_command_val = cfi_command_val(bank, 0x40);
1176 busy_pattern_val = cfi_command_val(bank, 0x80);
1177 error_pattern_val = cfi_command_val(bank, 0x7e);
1178
1179 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1180
1181 /* Programming main loop */
1182 while (count > 0)
1183 {
1184 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1185 uint32_t wsm_error;
1186
1187 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1188 {
1189 goto cleanup;
1190 }
1191
1192 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1193 buf_set_u32(reg_params[1].value, 0, 32, address);
1194 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1195
1196 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1197 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1198 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1199
1200 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1201
1202 /* Execute algorithm, assume breakpoint for last instruction */
1203 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1204 cfi_info->write_algorithm->address,
1205 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1206 10000, /* 10s should be enough for max. 32k of data */
1207 &armv4_5_info);
1208
1209 /* On failure try a fall back to direct word writes */
1210 if (retval != ERROR_OK)
1211 {
1212 cfi_intel_clear_status_register(bank);
1213 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1214 retval = ERROR_FLASH_OPERATION_FAILED;
1215 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1216 /* FIXME To allow fall back or recovery, we must save the actual status
1217 somewhere, so that a higher level code can start recovery. */
1218 goto cleanup;
1219 }
1220
1221 /* Check return value from algo code */
1222 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1223 if (wsm_error)
1224 {
1225 /* read status register (outputs debug inforation) */
1226 cfi_intel_wait_status_busy(bank, 100);
1227 cfi_intel_clear_status_register(bank);
1228 retval = ERROR_FLASH_OPERATION_FAILED;
1229 goto cleanup;
1230 }
1231
1232 buffer += thisrun_count;
1233 address += thisrun_count;
1234 count -= thisrun_count;
1235 }
1236
1237 /* free up resources */
1238 cleanup:
1239 if (source)
1240 target_free_working_area(target, source);
1241
1242 if (cfi_info->write_algorithm)
1243 {
1244 target_free_working_area(target, cfi_info->write_algorithm);
1245 cfi_info->write_algorithm = NULL;
1246 }
1247
1248 destroy_reg_param(&reg_params[0]);
1249 destroy_reg_param(&reg_params[1]);
1250 destroy_reg_param(&reg_params[2]);
1251 destroy_reg_param(&reg_params[3]);
1252 destroy_reg_param(&reg_params[4]);
1253 destroy_reg_param(&reg_params[5]);
1254 destroy_reg_param(&reg_params[6]);
1255
1256 return retval;
1257 }
1258
1259 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1260 {
1261 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1262 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1263 struct target *target = bank->target;
1264 struct reg_param reg_params[10];
1265 struct arm_algorithm armv4_5_info;
1266 struct working_area *source;
1267 uint32_t buffer_size = 32768;
1268 uint32_t status;
1269 int retval, retvaltemp;
1270 int exit_code = ERROR_OK;
1271
1272 /* input parameters - */
1273 /* R0 = source address */
1274 /* R1 = destination address */
1275 /* R2 = number of writes */
1276 /* R3 = flash write command */
1277 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1278 /* output parameters - */
1279 /* R5 = 0x80 ok 0x00 bad */
1280 /* temp registers - */
1281 /* R6 = value read from flash to test status */
1282 /* R7 = holding register */
1283 /* unlock registers - */
1284 /* R8 = unlock1_addr */
1285 /* R9 = unlock1_cmd */
1286 /* R10 = unlock2_addr */
1287 /* R11 = unlock2_cmd */
1288
1289 static const uint32_t word_32_code[] = {
1290 /* 00008100 <sp_32_code>: */
1291 0xe4905004, /* ldr r5, [r0], #4 */
1292 0xe5889000, /* str r9, [r8] */
1293 0xe58ab000, /* str r11, [r10] */
1294 0xe5883000, /* str r3, [r8] */
1295 0xe5815000, /* str r5, [r1] */
1296 0xe1a00000, /* nop */
1297 /* */
1298 /* 00008110 <sp_32_busy>: */
1299 0xe5916000, /* ldr r6, [r1] */
1300 0xe0257006, /* eor r7, r5, r6 */
1301 0xe0147007, /* ands r7, r4, r7 */
1302 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1303 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1304 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1305 0xe5916000, /* ldr r6, [r1] */
1306 0xe0257006, /* eor r7, r5, r6 */
1307 0xe0147007, /* ands r7, r4, r7 */
1308 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1309 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1310 0x1a000004, /* bne 8154 <sp_32_done> */
1311 /* */
1312 /* 00008140 <sp_32_cont>: */
1313 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1314 0x03a05080, /* moveq r5, #128 ; 0x80 */
1315 0x0a000001, /* beq 8154 <sp_32_done> */
1316 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1317 0xeaffffe8, /* b 8100 <sp_32_code> */
1318 /* */
1319 /* 00008154 <sp_32_done>: */
1320 0xeafffffe /* b 8154 <sp_32_done> */
1321 };
1322
1323 static const uint32_t word_16_code[] = {
1324 /* 00008158 <sp_16_code>: */
1325 0xe0d050b2, /* ldrh r5, [r0], #2 */
1326 0xe1c890b0, /* strh r9, [r8] */
1327 0xe1cab0b0, /* strh r11, [r10] */
1328 0xe1c830b0, /* strh r3, [r8] */
1329 0xe1c150b0, /* strh r5, [r1] */
1330 0xe1a00000, /* nop (mov r0,r0) */
1331 /* */
1332 /* 00008168 <sp_16_busy>: */
1333 0xe1d160b0, /* ldrh r6, [r1] */
1334 0xe0257006, /* eor r7, r5, r6 */
1335 0xe0147007, /* ands r7, r4, r7 */
1336 0x0a000007, /* beq 8198 <sp_16_cont> */
1337 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1338 0x0afffff9, /* beq 8168 <sp_16_busy> */
1339 0xe1d160b0, /* ldrh r6, [r1] */
1340 0xe0257006, /* eor r7, r5, r6 */
1341 0xe0147007, /* ands r7, r4, r7 */
1342 0x0a000001, /* beq 8198 <sp_16_cont> */
1343 0xe3a05000, /* mov r5, #0 ; 0x0 */
1344 0x1a000004, /* bne 81ac <sp_16_done> */
1345 /* */
1346 /* 00008198 <sp_16_cont>: */
1347 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1348 0x03a05080, /* moveq r5, #128 ; 0x80 */
1349 0x0a000001, /* beq 81ac <sp_16_done> */
1350 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1351 0xeaffffe8, /* b 8158 <sp_16_code> */
1352 /* */
1353 /* 000081ac <sp_16_done>: */
1354 0xeafffffe /* b 81ac <sp_16_done> */
1355 };
1356
1357 static const uint32_t word_16_code_dq7only[] = {
1358 /* <sp_16_code>: */
1359 0xe0d050b2, /* ldrh r5, [r0], #2 */
1360 0xe1c890b0, /* strh r9, [r8] */
1361 0xe1cab0b0, /* strh r11, [r10] */
1362 0xe1c830b0, /* strh r3, [r8] */
1363 0xe1c150b0, /* strh r5, [r1] */
1364 0xe1a00000, /* nop (mov r0,r0) */
1365 /* */
1366 /* <sp_16_busy>: */
1367 0xe1d160b0, /* ldrh r6, [r1] */
1368 0xe0257006, /* eor r7, r5, r6 */
1369 0xe2177080, /* ands r7, #0x80 */
1370 0x1afffffb, /* bne 8168 <sp_16_busy> */
1371 /* */
1372 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1373 0x03a05080, /* moveq r5, #128 ; 0x80 */
1374 0x0a000001, /* beq 81ac <sp_16_done> */
1375 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1376 0xeafffff0, /* b 8158 <sp_16_code> */
1377 /* */
1378 /* 000081ac <sp_16_done>: */
1379 0xeafffffe /* b 81ac <sp_16_done> */
1380 };
1381
1382 static const uint32_t word_8_code[] = {
1383 /* 000081b0 <sp_16_code_end>: */
1384 0xe4d05001, /* ldrb r5, [r0], #1 */
1385 0xe5c89000, /* strb r9, [r8] */
1386 0xe5cab000, /* strb r11, [r10] */
1387 0xe5c83000, /* strb r3, [r8] */
1388 0xe5c15000, /* strb r5, [r1] */
1389 0xe1a00000, /* nop (mov r0,r0) */
1390 /* */
1391 /* 000081c0 <sp_8_busy>: */
1392 0xe5d16000, /* ldrb r6, [r1] */
1393 0xe0257006, /* eor r7, r5, r6 */
1394 0xe0147007, /* ands r7, r4, r7 */
1395 0x0a000007, /* beq 81f0 <sp_8_cont> */
1396 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1397 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1398 0xe5d16000, /* ldrb r6, [r1] */
1399 0xe0257006, /* eor r7, r5, r6 */
1400 0xe0147007, /* ands r7, r4, r7 */
1401 0x0a000001, /* beq 81f0 <sp_8_cont> */
1402 0xe3a05000, /* mov r5, #0 ; 0x0 */
1403 0x1a000004, /* bne 8204 <sp_8_done> */
1404 /* */
1405 /* 000081f0 <sp_8_cont>: */
1406 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1407 0x03a05080, /* moveq r5, #128 ; 0x80 */
1408 0x0a000001, /* beq 8204 <sp_8_done> */
1409 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1410 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1411 /* */
1412 /* 00008204 <sp_8_done>: */
1413 0xeafffffe /* b 8204 <sp_8_done> */
1414 };
1415
1416 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1417 armv4_5_info.core_mode = ARM_MODE_SVC;
1418 armv4_5_info.core_state = ARM_STATE_ARM;
1419
1420 int target_code_size;
1421 const uint32_t *target_code_src;
1422
1423 switch (bank->bus_width)
1424 {
1425 case 1 :
1426 target_code_src = word_8_code;
1427 target_code_size = sizeof(word_8_code);
1428 break;
1429 case 2 :
1430 /* Check for DQ5 support */
1431 if( cfi_info->status_poll_mask & (1 << 5) )
1432 {
1433 target_code_src = word_16_code;
1434 target_code_size = sizeof(word_16_code);
1435 }
1436 else
1437 {
1438 /* No DQ5 support. Use DQ7 DATA# polling only. */
1439 target_code_src = word_16_code_dq7only;
1440 target_code_size = sizeof(word_16_code_dq7only);
1441 }
1442 break;
1443 case 4 :
1444 target_code_src = word_32_code;
1445 target_code_size = sizeof(word_32_code);
1446 break;
1447 default:
1448 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1450 }
1451
1452 /* flash write code */
1453 if (!cfi_info->write_algorithm)
1454 {
1455 uint8_t *target_code;
1456
1457 /* convert bus-width dependent algorithm code to correct endiannes */
1458 target_code = malloc(target_code_size);
1459 if (target_code == NULL)
1460 {
1461 LOG_ERROR("Out of memory");
1462 return ERROR_FAIL;
1463 }
1464 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1465
1466 /* allocate working area */
1467 retval = target_alloc_working_area(target, target_code_size,
1468 &cfi_info->write_algorithm);
1469 if (retval != ERROR_OK)
1470 {
1471 free(target_code);
1472 return retval;
1473 }
1474
1475 /* write algorithm code to working area */
1476 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1477 target_code_size, target_code)) != ERROR_OK)
1478 {
1479 free(target_code);
1480 return retval;
1481 }
1482
1483 free(target_code);
1484 }
1485 /* the following code still assumes target code is fixed 24*4 bytes */
1486
1487 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1488 {
1489 buffer_size /= 2;
1490 if (buffer_size <= 256)
1491 {
1492 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1493 if (cfi_info->write_algorithm)
1494 target_free_working_area(target, cfi_info->write_algorithm);
1495
1496 LOG_WARNING("not enough working area available, can't do block memory writes");
1497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1498 }
1499 };
1500
1501 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1502 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1503 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1504 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1505 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1506 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1507 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1508 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1509 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1510 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1511
1512 while (count > 0)
1513 {
1514 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1515
1516 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1517
1518 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1519 buf_set_u32(reg_params[1].value, 0, 32, address);
1520 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1521 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1522 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1523 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1524 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1525 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1526 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1527
1528 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1529 cfi_info->write_algorithm->address,
1530 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1531 10000, &armv4_5_info);
1532
1533 status = buf_get_u32(reg_params[5].value, 0, 32);
1534
1535 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1536 {
1537 LOG_DEBUG("status: 0x%" PRIx32 , status);
1538 exit_code = ERROR_FLASH_OPERATION_FAILED;
1539 break;
1540 }
1541
1542 buffer += thisrun_count;
1543 address += thisrun_count;
1544 count -= thisrun_count;
1545 }
1546
1547 target_free_all_working_areas(target);
1548
1549 destroy_reg_param(&reg_params[0]);
1550 destroy_reg_param(&reg_params[1]);
1551 destroy_reg_param(&reg_params[2]);
1552 destroy_reg_param(&reg_params[3]);
1553 destroy_reg_param(&reg_params[4]);
1554 destroy_reg_param(&reg_params[5]);
1555 destroy_reg_param(&reg_params[6]);
1556 destroy_reg_param(&reg_params[7]);
1557 destroy_reg_param(&reg_params[8]);
1558 destroy_reg_param(&reg_params[9]);
1559
1560 return exit_code;
1561 }
1562
1563 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1564 {
1565 int retval;
1566 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1567 struct target *target = bank->target;
1568
1569 cfi_intel_clear_status_register(bank);
1570 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1571 {
1572 return retval;
1573 }
1574
1575 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1576 {
1577 return retval;
1578 }
1579
1580 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1581 {
1582 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1583 {
1584 return retval;
1585 }
1586
1587 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1588 return ERROR_FLASH_OPERATION_FAILED;
1589 }
1590
1591 return ERROR_OK;
1592 }
1593
1594 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1595 {
1596 int retval;
1597 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1598 struct target *target = bank->target;
1599
1600 /* Calculate buffer size and boundary mask */
1601 /* buffersize is (buffer size per chip) * (number of chips) */
1602 /* bufferwsize is buffersize in words */
1603 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1604 uint32_t buffermask = buffersize-1;
1605 uint32_t bufferwsize = buffersize / bank->bus_width;
1606
1607 /* Check for valid range */
1608 if (address & buffermask)
1609 {
1610 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1611 bank->base, address, cfi_info->max_buf_write_size);
1612 return ERROR_FLASH_OPERATION_FAILED;
1613 }
1614
1615 /* Check for valid size */
1616 if (wordcount > bufferwsize)
1617 {
1618 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1619 return ERROR_FLASH_OPERATION_FAILED;
1620 }
1621
1622 /* Write to flash buffer */
1623 cfi_intel_clear_status_register(bank);
1624
1625 /* Initiate buffer operation _*/
1626 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1627 {
1628 return retval;
1629 }
1630 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1631 {
1632 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1633 {
1634 return retval;
1635 }
1636
1637 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1638 return ERROR_FLASH_OPERATION_FAILED;
1639 }
1640
1641 /* Write buffer wordcount-1 and data words */
1642 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1643 {
1644 return retval;
1645 }
1646
1647 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1648 {
1649 return retval;
1650 }
1651
1652 /* Commit write operation */
1653 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1654 {
1655 return retval;
1656 }
1657 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1658 {
1659 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1660 {
1661 return retval;
1662 }
1663
1664 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1665 return ERROR_FLASH_OPERATION_FAILED;
1666 }
1667
1668 return ERROR_OK;
1669 }
1670
1671 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1672 {
1673 int retval;
1674 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1675 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1676 struct target *target = bank->target;
1677
1678 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1679 {
1680 return retval;
1681 }
1682
1683 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1684 {
1685 return retval;
1686 }
1687
1688 if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1689 {
1690 return retval;
1691 }
1692
1693 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1694 {
1695 return retval;
1696 }
1697
1698 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1699 {
1700 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1701 {
1702 return retval;
1703 }
1704
1705 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1706 return ERROR_FLASH_OPERATION_FAILED;
1707 }
1708
1709 return ERROR_OK;
1710 }
1711
1712 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1713 {
1714 int retval;
1715 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1716 struct target *target = bank->target;
1717 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1718
1719 /* Calculate buffer size and boundary mask */
1720 /* buffersize is (buffer size per chip) * (number of chips) */
1721 /* bufferwsize is buffersize in words */
1722 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1723 uint32_t buffermask = buffersize-1;
1724 uint32_t bufferwsize = buffersize / bank->bus_width;
1725
1726 /* Check for valid range */
1727 if (address & buffermask)
1728 {
1729 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1730 return ERROR_FLASH_OPERATION_FAILED;
1731 }
1732
1733 /* Check for valid size */
1734 if (wordcount > bufferwsize)
1735 {
1736 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1737 return ERROR_FLASH_OPERATION_FAILED;
1738 }
1739
1740 // Unlock
1741 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1742 {
1743 return retval;
1744 }
1745
1746 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1747 {
1748 return retval;
1749 }
1750
1751 // Buffer load command
1752 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1753 {
1754 return retval;
1755 }
1756
1757 /* Write buffer wordcount-1 and data words */
1758 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1759 {
1760 return retval;
1761 }
1762
1763 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1764 {
1765 return retval;
1766 }
1767
1768 /* Commit write operation */
1769 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1770 {
1771 return retval;
1772 }
1773
1774 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1775 {
1776 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1777 {
1778 return retval;
1779 }
1780
1781 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1782 return ERROR_FLASH_OPERATION_FAILED;
1783 }
1784
1785 return ERROR_OK;
1786 }
1787
1788 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1789 {
1790 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1791
1792 switch (cfi_info->pri_id)
1793 {
1794 case 1:
1795 case 3:
1796 return cfi_intel_write_word(bank, word, address);
1797 break;
1798 case 2:
1799 return cfi_spansion_write_word(bank, word, address);
1800 break;
1801 default:
1802 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1803 break;
1804 }
1805
1806 return ERROR_FLASH_OPERATION_FAILED;
1807 }
1808
1809 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1810 {
1811 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1812
1813 switch (cfi_info->pri_id)
1814 {
1815 case 1:
1816 case 3:
1817 return cfi_intel_write_words(bank, word, wordcount, address);
1818 break;
1819 case 2:
1820 return cfi_spansion_write_words(bank, word, wordcount, address);
1821 break;
1822 default:
1823 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1824 break;
1825 }
1826
1827 return ERROR_FLASH_OPERATION_FAILED;
1828 }
1829
1830 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1831 {
1832 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1833 struct target *target = bank->target;
1834 uint32_t address = bank->base + offset;
1835 uint32_t read_p;
1836 int align; /* number of unaligned bytes */
1837 uint8_t current_word[CFI_MAX_BUS_WIDTH];
1838 int i;
1839 int retval;
1840
1841 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
1842 (int)count, (unsigned)offset);
1843
1844 if (bank->target->state != TARGET_HALTED)
1845 {
1846 LOG_ERROR("Target not halted");
1847 return ERROR_TARGET_NOT_HALTED;
1848 }
1849
1850 if (offset + count > bank->size)
1851 return ERROR_FLASH_DST_OUT_OF_BANK;
1852
1853 if (cfi_info->qry[0] != 'Q')
1854 return ERROR_FLASH_BANK_NOT_PROBED;
1855
1856 /* start at the first byte of the first word (bus_width size) */
1857 read_p = address & ~(bank->bus_width - 1);
1858 if ((align = address - read_p) != 0)
1859 {
1860 LOG_INFO("Fixup %d unaligned read head bytes", align);
1861
1862 /* read a complete word from flash */
1863 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1864 return retval;
1865
1866 /* take only bytes we need */
1867 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
1868 *buffer++ = current_word[i];
1869
1870 read_p += bank->bus_width;
1871 }
1872
1873 align = count / bank->bus_width;
1874 if (align)
1875 {
1876 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
1877 return retval;
1878
1879 read_p += align * bank->bus_width;
1880 buffer += align * bank->bus_width;
1881 count -= align * bank->bus_width;
1882 }
1883
1884 if (count)
1885 {
1886 LOG_INFO("Fixup %d unaligned read tail bytes", count);
1887
1888 /* read a complete word from flash */
1889 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1890 return retval;
1891
1892 /* take only bytes we need */
1893 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
1894 *buffer++ = current_word[i];
1895 }
1896
1897 return ERROR_OK;
1898 }
1899
1900 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1901 {
1902 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1903 struct target *target = bank->target;
1904 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1905 uint32_t write_p;
1906 int align; /* number of unaligned bytes */
1907 int blk_count; /* number of bus_width bytes for block copy */
1908 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1909 int i;
1910 int retval;
1911
1912 if (bank->target->state != TARGET_HALTED)
1913 {
1914 LOG_ERROR("Target not halted");
1915 return ERROR_TARGET_NOT_HALTED;
1916 }
1917
1918 if (offset + count > bank->size)
1919 return ERROR_FLASH_DST_OUT_OF_BANK;
1920
1921 if (cfi_info->qry[0] != 'Q')
1922 return ERROR_FLASH_BANK_NOT_PROBED;
1923
1924 /* start at the first byte of the first word (bus_width size) */
1925 write_p = address & ~(bank->bus_width - 1);
1926 if ((align = address - write_p) != 0)
1927 {
1928 LOG_INFO("Fixup %d unaligned head bytes", align);
1929
1930 /* read a complete word from flash */
1931 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
1932 return retval;
1933
1934 /* replace only bytes that must be written */
1935 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
1936 current_word[i] = *buffer++;
1937
1938 retval = cfi_write_word(bank, current_word, write_p);
1939 if (retval != ERROR_OK)
1940 return retval;
1941 write_p += bank->bus_width;
1942 }
1943
1944 /* handle blocks of bus_size aligned bytes */
1945 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1946 switch (cfi_info->pri_id)
1947 {
1948 /* try block writes (fails without working area) */
1949 case 1:
1950 case 3:
1951 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1952 break;
1953 case 2:
1954 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1955 break;
1956 default:
1957 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1958 retval = ERROR_FLASH_OPERATION_FAILED;
1959 break;
1960 }
1961 if (retval == ERROR_OK)
1962 {
1963 /* Increment pointers and decrease count on succesful block write */
1964 buffer += blk_count;
1965 write_p += blk_count;
1966 count -= blk_count;
1967 }
1968 else
1969 {
1970 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1971 {
1972 /* Calculate buffer size and boundary mask */
1973 /* buffersize is (buffer size per chip) * (number of chips) */
1974 /* bufferwsize is buffersize in words */
1975 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1976 uint32_t buffermask = buffersize-1;
1977 uint32_t bufferwsize = buffersize / bank->bus_width;
1978
1979 /* fall back to memory writes */
1980 while (count >= (uint32_t)bank->bus_width)
1981 {
1982 int fallback;
1983 if ((write_p & 0xff) == 0)
1984 {
1985 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1986 }
1987 fallback = 1;
1988 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1989 {
1990 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1991 if (retval == ERROR_OK)
1992 {
1993 buffer += buffersize;
1994 write_p += buffersize;
1995 count -= buffersize;
1996 fallback = 0;
1997 }
1998 }
1999 /* try the slow way? */
2000 if (fallback)
2001 {
2002 for (i = 0; i < bank->bus_width; i++)
2003 current_word[i] = *buffer++;
2004
2005 retval = cfi_write_word(bank, current_word, write_p);
2006 if (retval != ERROR_OK)
2007 return retval;
2008
2009 write_p += bank->bus_width;
2010 count -= bank->bus_width;
2011 }
2012 }
2013 }
2014 else
2015 return retval;
2016 }
2017
2018 /* return to read array mode, so we can read from flash again for padding */
2019 if ((retval = cfi_reset(bank)) != ERROR_OK)
2020 {
2021 return retval;
2022 }
2023
2024 /* handle unaligned tail bytes */
2025 if (count > 0)
2026 {
2027 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2028
2029 /* read a complete word from flash */
2030 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2031 return retval;
2032
2033 /* replace only bytes that must be written */
2034 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2035 current_word[i] = *buffer++;
2036
2037 retval = cfi_write_word(bank, current_word, write_p);
2038 if (retval != ERROR_OK)
2039 return retval;
2040 }
2041
2042 /* return to read array mode */
2043 return cfi_reset(bank);
2044 }
2045
2046 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2047 {
2048 (void) param;
2049 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2050 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2051
2052 pri_ext->_reversed_geometry = 1;
2053 }
2054
2055 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2056 {
2057 int i;
2058 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2059 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2060 (void) param;
2061
2062 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2063 {
2064 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2065
2066 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2067 {
2068 int j = (cfi_info->num_erase_regions - 1) - i;
2069 uint32_t swap;
2070
2071 swap = cfi_info->erase_region_info[i];
2072 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2073 cfi_info->erase_region_info[j] = swap;
2074 }
2075 }
2076 }
2077
2078 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2079 {
2080 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2081 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2082 struct cfi_unlock_addresses *unlock_addresses = param;
2083
2084 pri_ext->_unlock1 = unlock_addresses->unlock1;
2085 pri_ext->_unlock2 = unlock_addresses->unlock2;
2086 }
2087
2088
2089 static int cfi_query_string(struct flash_bank *bank, int address)
2090 {
2091 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2092 int retval;
2093
2094 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2095 {
2096 return retval;
2097 }
2098
2099 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2100 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2101 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2102
2103 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2104
2105 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2106 {
2107 if ((retval = cfi_reset(bank)) != ERROR_OK)
2108 {
2109 return retval;
2110 }
2111 LOG_ERROR("Could not probe bank: no QRY");
2112 return ERROR_FLASH_BANK_INVALID;
2113 }
2114
2115 return ERROR_OK;
2116 }
2117
2118 static int cfi_probe(struct flash_bank *bank)
2119 {
2120 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2121 struct target *target = bank->target;
2122 int num_sectors = 0;
2123 int i;
2124 int sector = 0;
2125 uint32_t unlock1 = 0x555;
2126 uint32_t unlock2 = 0x2aa;
2127 int retval;
2128 uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2129
2130 if (bank->target->state != TARGET_HALTED)
2131 {
2132 LOG_ERROR("Target not halted");
2133 return ERROR_TARGET_NOT_HALTED;
2134 }
2135
2136 cfi_info->probed = 0;
2137 if (bank->sectors)
2138 {
2139 free(bank->sectors);
2140 bank->sectors = NULL;
2141 }
2142 if(cfi_info->erase_region_info)
2143 {
2144 free(cfi_info->erase_region_info);
2145 cfi_info->erase_region_info = NULL;
2146 }
2147
2148 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2149 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2150 */
2151 if (cfi_info->jedec_probe)
2152 {
2153 unlock1 = 0x5555;
2154 unlock2 = 0x2aaa;
2155 }
2156
2157 /* switch to read identifier codes mode ("AUTOSELECT") */
2158 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2159 {
2160 return retval;
2161 }
2162 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2163 {
2164 return retval;
2165 }
2166 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2167 {
2168 return retval;
2169 }
2170
2171 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2172 {
2173 return retval;
2174 }
2175 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2176 {
2177 return retval;
2178 }
2179 switch (bank->chip_width) {
2180 case 1:
2181 cfi_info->manufacturer = *value_buf0;
2182 cfi_info->device_id = *value_buf1;
2183 break;
2184 case 2:
2185 cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2186 cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2187 break;
2188 case 4:
2189 cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2190 cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2191 break;
2192 default:
2193 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2194 return ERROR_FLASH_OPERATION_FAILED;
2195 }
2196
2197 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2198 /* switch back to read array mode */
2199 if ((retval = cfi_reset(bank)) != ERROR_OK)
2200 {
2201 return retval;
2202 }
2203
2204 /* check device/manufacturer ID for known non-CFI flashes. */
2205 cfi_fixup_non_cfi(bank);
2206
2207 /* query only if this is a CFI compatible flash,
2208 * otherwise the relevant info has already been filled in
2209 */
2210 if (cfi_info->not_cfi == 0)
2211 {
2212 int retval;
2213
2214 /* enter CFI query mode
2215 * according to JEDEC Standard No. 68.01,
2216 * a single bus sequence with address = 0x55, data = 0x98 should put
2217 * the device into CFI query mode.
2218 *
2219 * SST flashes clearly violate this, and we will consider them incompatbile for now
2220 */
2221
2222 retval = cfi_query_string(bank, 0x55);
2223 if (retval != ERROR_OK)
2224 {
2225 /*
2226 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2227 * be harmless enough:
2228 *
2229 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2230 */
2231 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2232 retval = cfi_query_string(bank, 0x555);
2233 }
2234 if (retval != ERROR_OK)
2235 return retval;
2236
2237 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2238 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2239 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2240 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2241
2242 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2243
2244 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2245 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2246 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2247 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2248 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2249 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2250 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2251 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2252 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2253 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2254 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2255 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2256
2257 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2258 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2259 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2260 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2261 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2262 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2263 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2264 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2265 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2266 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2267 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2268
2269 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2270 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2271 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2272 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2273
2274 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2275
2276 if (cfi_info->num_erase_regions)
2277 {
2278 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2279 for (i = 0; i < cfi_info->num_erase_regions; i++)
2280 {
2281 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2282 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2283 i,
2284 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2285 (cfi_info->erase_region_info[i] >> 16) * 256);
2286 }
2287 }
2288 else
2289 {
2290 cfi_info->erase_region_info = NULL;
2291 }
2292
2293 /* We need to read the primary algorithm extended query table before calculating
2294 * the sector layout to be able to apply fixups
2295 */
2296 switch (cfi_info->pri_id)
2297 {
2298 /* Intel command set (standard and extended) */
2299 case 0x0001:
2300 case 0x0003:
2301 cfi_read_intel_pri_ext(bank);
2302 break;
2303 /* AMD/Spansion, Atmel, ... command set */
2304 case 0x0002:
2305 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2306 cfi_read_0002_pri_ext(bank);
2307 break;
2308 default:
2309 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2310 break;
2311 }
2312
2313 /* return to read array mode
2314 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2315 */
2316 if ((retval = cfi_reset(bank)) != ERROR_OK)
2317 {
2318 return retval;
2319 }
2320 } /* end CFI case */
2321
2322 /* apply fixups depending on the primary command set */
2323 switch (cfi_info->pri_id)
2324 {
2325 /* Intel command set (standard and extended) */
2326 case 0x0001:
2327 case 0x0003:
2328 cfi_fixup(bank, cfi_0001_fixups);
2329 break;
2330 /* AMD/Spansion, Atmel, ... command set */
2331 case 0x0002:
2332 cfi_fixup(bank, cfi_0002_fixups);
2333 break;
2334 default:
2335 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2336 break;
2337 }
2338
2339 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2340 {
2341 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2342 }
2343
2344 if (cfi_info->num_erase_regions == 0)
2345 {
2346 /* a device might have only one erase block, spanning the whole device */
2347 bank->num_sectors = 1;
2348 bank->sectors = malloc(sizeof(struct flash_sector));
2349
2350 bank->sectors[sector].offset = 0x0;
2351 bank->sectors[sector].size = bank->size;
2352 bank->sectors[sector].is_erased = -1;
2353 bank->sectors[sector].is_protected = -1;
2354 }
2355 else
2356 {
2357 uint32_t offset = 0;
2358
2359 for (i = 0; i < cfi_info->num_erase_regions; i++)
2360 {
2361 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2362 }
2363
2364 bank->num_sectors = num_sectors;
2365 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2366
2367 for (i = 0; i < cfi_info->num_erase_regions; i++)
2368 {
2369 uint32_t j;
2370 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2371 {
2372 bank->sectors[sector].offset = offset;
2373 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2374 offset += bank->sectors[sector].size;
2375 bank->sectors[sector].is_erased = -1;
2376 bank->sectors[sector].is_protected = -1;
2377 sector++;
2378 }
2379 }
2380 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2381 {
2382 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2383 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2384 }
2385 }
2386
2387 cfi_info->probed = 1;
2388
2389 return ERROR_OK;
2390 }
2391
2392 static int cfi_auto_probe(struct flash_bank *bank)
2393 {
2394 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2395 if (cfi_info->probed)
2396 return ERROR_OK;
2397 return cfi_probe(bank);
2398 }
2399
2400 static int cfi_intel_protect_check(struct flash_bank *bank)
2401 {
2402 int retval;
2403 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2404 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2405 int i;
2406
2407 /* check if block lock bits are supported on this device */
2408 if (!(pri_ext->blk_status_reg_mask & 0x1))
2409 return ERROR_FLASH_OPERATION_FAILED;
2410
2411 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2412 {
2413 return retval;
2414 }
2415
2416 for (i = 0; i < bank->num_sectors; i++)
2417 {
2418 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2419
2420 if (block_status & 1)
2421 bank->sectors[i].is_protected = 1;
2422 else
2423 bank->sectors[i].is_protected = 0;
2424 }
2425
2426 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2427 }
2428
2429 static int cfi_spansion_protect_check(struct flash_bank *bank)
2430 {
2431 int retval;
2432 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2433 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2434 int i;
2435
2436 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2437 {
2438 return retval;
2439 }
2440
2441 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2442 {
2443 return retval;
2444 }
2445
2446 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2447 {
2448 return retval;
2449 }
2450
2451 for (i = 0; i < bank->num_sectors; i++)
2452 {
2453 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2454
2455 if (block_status & 1)
2456 bank->sectors[i].is_protected = 1;
2457 else
2458 bank->sectors[i].is_protected = 0;
2459 }
2460
2461 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2462 }
2463
2464 static int cfi_protect_check(struct flash_bank *bank)
2465 {
2466 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2467
2468 if (bank->target->state != TARGET_HALTED)
2469 {
2470 LOG_ERROR("Target not halted");
2471 return ERROR_TARGET_NOT_HALTED;
2472 }
2473
2474 if (cfi_info->qry[0] != 'Q')
2475 return ERROR_FLASH_BANK_NOT_PROBED;
2476
2477 switch (cfi_info->pri_id)
2478 {
2479 case 1:
2480 case 3:
2481 return cfi_intel_protect_check(bank);
2482 break;
2483 case 2:
2484 return cfi_spansion_protect_check(bank);
2485 break;
2486 default:
2487 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2488 break;
2489 }
2490
2491 return ERROR_OK;
2492 }
2493
2494 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2495 {
2496 int printed;
2497 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2498
2499 if (cfi_info->qry[0] == (char)-1)
2500 {
2501 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2502 return ERROR_OK;
2503 }
2504
2505 if (cfi_info->not_cfi == 0)
2506 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2507 else
2508 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2509 buf += printed;
2510 buf_size -= printed;
2511
2512 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2513 cfi_info->manufacturer, cfi_info->device_id);
2514 buf += printed;
2515 buf_size -= printed;
2516
2517 if (cfi_info->not_cfi == 0)
2518 {
2519 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2520 buf += printed;
2521 buf_size -= printed;
2522
2523 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2524 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2525 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2526 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2527 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2528 buf += printed;
2529 buf_size -= printed;
2530
2531 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2532 1 << cfi_info->word_write_timeout_typ,
2533 1 << cfi_info->buf_write_timeout_typ,
2534 1 << cfi_info->block_erase_timeout_typ,
2535 1 << cfi_info->chip_erase_timeout_typ);
2536 buf += printed;
2537 buf_size -= printed;
2538
2539 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2540 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2541 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2542 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2543 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2544 buf += printed;
2545 buf_size -= printed;
2546
2547 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2548 cfi_info->dev_size,
2549 cfi_info->interface_desc,
2550 1 << cfi_info->max_buf_write_size);
2551 buf += printed;
2552 buf_size -= printed;
2553
2554 switch (cfi_info->pri_id)
2555 {
2556 case 1:
2557 case 3:
2558 cfi_intel_info(bank, buf, buf_size);
2559 break;
2560 case 2:
2561 cfi_spansion_info(bank, buf, buf_size);
2562 break;
2563 default:
2564 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2565 break;
2566 }
2567 }
2568
2569 return ERROR_OK;
2570 }
2571
2572 struct flash_driver cfi_flash = {
2573 .name = "cfi",
2574 .flash_bank_command = cfi_flash_bank_command,
2575 .erase = cfi_erase,
2576 .protect = cfi_protect,
2577 .write = cfi_write,
2578 .read = cfi_read,
2579 .probe = cfi_probe,
2580 .auto_probe = cfi_auto_probe,
2581 /* FIXME: access flash at bus_width size */
2582 .erase_check = default_flash_blank_check,
2583 .protect_check = cfi_protect_check,
2584 .info = cfi_info,
2585 };
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