1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
42 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
44 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
45 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
51 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
53 /* fixup after reading cmdset 0002 primary query table */
54 static const struct cfi_fixup cfi_0002_fixups
[] = {
55 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
59 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
60 {CFI_MFR_SST
, 0x236d, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
61 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_reversed_erase_regions
, NULL
},
62 {CFI_MFR_ST
, 0x22C4, cfi_fixup_reversed_erase_regions
, NULL
}, /* M29W160ET */
63 {CFI_MFR_FUJITSU
, 0x22ea, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
64 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
65 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
66 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
67 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
68 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
72 /* fixup after reading cmdset 0001 primary query table */
73 static const struct cfi_fixup cfi_0001_fixups
[] = {
77 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
79 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
80 const struct cfi_fixup
*f
;
82 for (f
= fixups
; f
->fixup
; f
++)
84 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
85 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
87 f
->fixup(bank
, f
->param
);
92 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
93 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
95 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
97 if (cfi_info
->x16_as_x8
) offset
*= 2;
99 /* while the sector list isn't built, only accesses to sector 0 work */
101 return bank
->base
+ offset
* bank
->bus_width
;
106 LOG_ERROR("BUG: sector list not yet built");
109 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
113 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
117 /* clear whole buffer, to ensure bits that exceed the bus_width
120 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
123 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
125 for (i
= bank
->bus_width
; i
> 0; i
--)
127 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
132 for (i
= 1; i
<= bank
->bus_width
; i
++)
134 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
139 static int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
141 uint8_t command
[CFI_MAX_BUS_WIDTH
];
143 cfi_command(bank
, cmd
, command
);
144 return target_write_memory(bank
->target
, address
, bank
->bus_width
, 1, command
);
147 /* read unsigned 8-bit value from the bank
148 * flash banks are expected to be made of similar chips
149 * the query result should be the same for all
151 static int cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
153 struct target
*target
= bank
->target
;
154 uint8_t data
[CFI_MAX_BUS_WIDTH
];
157 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
),
158 bank
->bus_width
, 1, data
);
159 if (retval
!= ERROR_OK
)
162 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
165 *val
= data
[bank
->bus_width
- 1];
170 /* read unsigned 8-bit value from the bank
171 * in case of a bank made of multiple chips,
172 * the individual values are ORed
174 static int cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
176 struct target
*target
= bank
->target
;
177 uint8_t data
[CFI_MAX_BUS_WIDTH
];
181 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
),
182 bank
->bus_width
, 1, data
);
183 if (retval
!= ERROR_OK
)
186 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
188 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
196 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
197 value
|= data
[bank
->bus_width
- 1 - i
];
204 static int cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint16_t *val
)
206 struct target
*target
= bank
->target
;
207 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
208 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
211 if (cfi_info
->x16_as_x8
)
214 for (i
= 0;i
< 2;i
++)
216 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
),
217 bank
->bus_width
, 1, &data
[i
* bank
->bus_width
]);
218 if (retval
!= ERROR_OK
)
223 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
),
224 bank
->bus_width
, 2, data
);
225 if (retval
!= ERROR_OK
)
229 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
230 *val
= data
[0] | data
[bank
->bus_width
] << 8;
232 *val
= data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
237 static int cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint32_t *val
)
239 struct target
*target
= bank
->target
;
240 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
241 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
244 if (cfi_info
->x16_as_x8
)
247 for (i
= 0;i
< 4;i
++)
249 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
),
250 bank
->bus_width
, 1, &data
[i
* bank
->bus_width
]);
251 if (retval
!= ERROR_OK
)
257 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
),
258 bank
->bus_width
, 4, data
);
259 if (retval
!= ERROR_OK
)
263 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
264 *val
= data
[0] | data
[bank
->bus_width
] << 8 |
265 data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
267 *val
= data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
268 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
273 static int cfi_reset(struct flash_bank
*bank
)
275 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
276 int retval
= ERROR_OK
;
278 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
283 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
288 if (cfi_info
->manufacturer
== 0x20 &&
289 (cfi_info
->device_id
== 0x227E || cfi_info
->device_id
== 0x7E))
291 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
292 * so we send an extra 0xF0 reset to fix the bug */
293 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
302 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
304 struct target
*target
= bank
->target
;
306 if (target
->state
!= TARGET_HALTED
)
308 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
312 cfi_send_command(bank
, 0x50, flash_address(bank
, 0, 0x0));
315 static int cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
, uint8_t *val
)
319 int retval
= ERROR_OK
;
325 LOG_ERROR("timeout while waiting for WSM to become ready");
329 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
330 if (retval
!= ERROR_OK
)
339 /* mask out bit 0 (reserved) */
340 status
= status
& 0xfe;
342 LOG_DEBUG("status: 0x%x", status
);
346 LOG_ERROR("status register: 0x%x", status
);
348 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
350 LOG_ERROR("Program suspended");
352 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
354 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
356 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
358 LOG_ERROR("Block Erase Suspended");
360 cfi_intel_clear_status_register(bank
);
369 static int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
371 uint8_t status
, oldstatus
;
372 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
375 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
376 if (retval
!= ERROR_OK
)
380 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
382 if (retval
!= ERROR_OK
)
385 if ((status
^ oldstatus
) & 0x40) {
386 if (status
& cfi_info
->status_poll_mask
& 0x20) {
387 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
388 if (retval
!= ERROR_OK
)
390 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
391 if (retval
!= ERROR_OK
)
393 if ((status
^ oldstatus
) & 0x40) {
394 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
395 return(ERROR_FLASH_OPERATION_FAILED
);
397 LOG_DEBUG("status: 0x%x", status
);
401 } else { /* no toggle: finished, OK */
402 LOG_DEBUG("status: 0x%x", status
);
408 } while (timeout
-- > 0);
410 LOG_ERROR("timeout, status: 0x%x", status
);
412 return(ERROR_FLASH_BUSY
);
415 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
418 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
419 struct cfi_intel_pri_ext
*pri_ext
;
421 if (cfi_info
->pri_ext
)
422 free(cfi_info
->pri_ext
);
424 pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
427 LOG_ERROR("Out of memory");
430 cfi_info
->pri_ext
= pri_ext
;
432 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
433 if (retval
!= ERROR_OK
)
435 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
436 if (retval
!= ERROR_OK
)
438 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
439 if (retval
!= ERROR_OK
)
442 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
444 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
448 LOG_ERROR("Could not read bank flash bank information");
449 return ERROR_FLASH_BANK_INVALID
;
452 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
453 if (retval
!= ERROR_OK
)
455 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
456 if (retval
!= ERROR_OK
)
459 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1],
460 pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
462 retval
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->feature_support
);
463 if (retval
!= ERROR_OK
)
465 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->suspend_cmd_support
);
466 if (retval
!= ERROR_OK
)
468 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa, &pri_ext
->blk_status_reg_mask
);
469 if (retval
!= ERROR_OK
)
472 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: "
473 "0x%x, blk_status_reg_mask: 0x%x",
474 pri_ext
->feature_support
,
475 pri_ext
->suspend_cmd_support
,
476 pri_ext
->blk_status_reg_mask
);
478 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc, &pri_ext
->vcc_optimal
);
479 if (retval
!= ERROR_OK
)
481 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd, &pri_ext
->vpp_optimal
);
482 if (retval
!= ERROR_OK
)
485 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
486 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
487 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
489 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe, &pri_ext
->num_protection_fields
);
490 if (retval
!= ERROR_OK
)
492 if (pri_ext
->num_protection_fields
!= 1)
494 LOG_WARNING("expected one protection register field, but found %i",
495 pri_ext
->num_protection_fields
);
498 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf, &pri_ext
->prot_reg_addr
);
499 if (retval
!= ERROR_OK
)
501 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11, &pri_ext
->fact_prot_reg_size
);
502 if (retval
!= ERROR_OK
)
504 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12, &pri_ext
->user_prot_reg_size
);
505 if (retval
!= ERROR_OK
)
508 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
509 "factory pre-programmed: %i, user programmable: %i",
510 pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
,
511 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
516 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
519 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
520 struct cfi_spansion_pri_ext
*pri_ext
;
522 if (cfi_info
->pri_ext
)
523 free(cfi_info
->pri_ext
);
525 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
528 LOG_ERROR("Out of memory");
531 cfi_info
->pri_ext
= pri_ext
;
533 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
534 if (retval
!= ERROR_OK
)
536 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
537 if (retval
!= ERROR_OK
)
539 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
540 if (retval
!= ERROR_OK
)
543 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
545 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
549 LOG_ERROR("Could not read spansion bank information");
550 return ERROR_FLASH_BANK_INVALID
;
553 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
554 if (retval
!= ERROR_OK
)
556 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
557 if (retval
!= ERROR_OK
)
560 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1],
561 pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
563 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->SiliconRevision
);
564 if (retval
!= ERROR_OK
)
566 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &pri_ext
->EraseSuspend
);
567 if (retval
!= ERROR_OK
)
569 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &pri_ext
->BlkProt
);
570 if (retval
!= ERROR_OK
)
572 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &pri_ext
->TmpBlkUnprotect
);
573 if (retval
!= ERROR_OK
)
575 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->BlkProtUnprot
);
576 if (retval
!= ERROR_OK
)
578 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10, &pri_ext
->SimultaneousOps
);
579 if (retval
!= ERROR_OK
)
581 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11, &pri_ext
->BurstMode
);
582 if (retval
!= ERROR_OK
)
584 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12, &pri_ext
->PageMode
);
585 if (retval
!= ERROR_OK
)
587 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13, &pri_ext
->VppMin
);
588 if (retval
!= ERROR_OK
)
590 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14, &pri_ext
->VppMax
);
591 if (retval
!= ERROR_OK
)
593 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15, &pri_ext
->TopBottom
);
594 if (retval
!= ERROR_OK
)
597 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
598 pri_ext
->SiliconRevision
, pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
600 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
601 "Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
602 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
604 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
607 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
608 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
609 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
611 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
613 /* default values for implementation specific workarounds */
614 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
615 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
616 pri_ext
->_reversed_geometry
= 0;
621 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
624 struct cfi_atmel_pri_ext atmel_pri_ext
;
625 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
626 struct cfi_spansion_pri_ext
*pri_ext
;
628 if (cfi_info
->pri_ext
)
629 free(cfi_info
->pri_ext
);
631 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
634 LOG_ERROR("Out of memory");
638 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
639 * but a different primary extended query table.
640 * We read the atmel table, and prepare a valid AMD/Spansion query table.
643 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
645 cfi_info
->pri_ext
= pri_ext
;
647 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &atmel_pri_ext
.pri
[0]);
648 if (retval
!= ERROR_OK
)
650 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &atmel_pri_ext
.pri
[1]);
651 if (retval
!= ERROR_OK
)
653 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &atmel_pri_ext
.pri
[2]);
654 if (retval
!= ERROR_OK
)
657 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R')
658 || (atmel_pri_ext
.pri
[2] != 'I'))
660 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
664 LOG_ERROR("Could not read atmel bank information");
665 return ERROR_FLASH_BANK_INVALID
;
668 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
669 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
670 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
672 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &atmel_pri_ext
.major_version
);
673 if (retval
!= ERROR_OK
)
675 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &atmel_pri_ext
.minor_version
);
676 if (retval
!= ERROR_OK
)
679 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0],
680 atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2],
681 atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
683 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
684 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
686 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &atmel_pri_ext
.features
);
687 if (retval
!= ERROR_OK
)
689 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &atmel_pri_ext
.bottom_boot
);
690 if (retval
!= ERROR_OK
)
692 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &atmel_pri_ext
.burst_mode
);
693 if (retval
!= ERROR_OK
)
695 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &atmel_pri_ext
.page_mode
);
696 if (retval
!= ERROR_OK
)
699 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
700 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
,
701 atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
703 if (atmel_pri_ext
.features
& 0x02)
704 pri_ext
->EraseSuspend
= 2;
706 if (atmel_pri_ext
.bottom_boot
)
707 pri_ext
->TopBottom
= 2;
709 pri_ext
->TopBottom
= 3;
711 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
712 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
717 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
719 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
721 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
723 return cfi_read_atmel_pri_ext(bank
);
727 return cfi_read_spansion_pri_ext(bank
);
731 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
734 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
735 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
737 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
741 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
742 pri_ext
->pri
[1], pri_ext
->pri
[2],
743 pri_ext
->major_version
, pri_ext
->minor_version
);
747 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
748 (pri_ext
->SiliconRevision
) >> 2,
749 (pri_ext
->SiliconRevision
) & 0x03);
753 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
754 pri_ext
->EraseSuspend
,
759 printed
= snprintf(buf
, buf_size
, "VppMin: %u.%x, VppMax: %u.%x\n",
760 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
761 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
766 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
769 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
770 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
772 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
776 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
777 pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
781 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", "
782 "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
783 pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
787 printed
= snprintf(buf
, buf_size
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
788 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
789 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
793 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, "
794 "factory pre-programmed: %i, user programmable: %i\n",
795 pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
,
796 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
801 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
803 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
805 struct cfi_flash_bank
*cfi_info
;
809 LOG_WARNING("incomplete flash_bank cfi configuration");
810 return ERROR_FLASH_BANK_INVALID
;
814 * - not exceed max value;
816 * - be equal to a power of 2.
817 * bus must be wide enought to hold one chip */
818 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
819 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
)
820 || (bank
->chip_width
== 0)
821 || (bank
->bus_width
== 0)
822 || (bank
->chip_width
& (bank
->chip_width
- 1))
823 || (bank
->bus_width
& (bank
->bus_width
- 1))
824 || (bank
->chip_width
> bank
->bus_width
))
826 LOG_ERROR("chip and bus width have to specified in bytes");
827 return ERROR_FLASH_BANK_INVALID
;
830 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
831 cfi_info
->probed
= 0;
832 cfi_info
->erase_region_info
= NULL
;
833 cfi_info
->pri_ext
= NULL
;
834 bank
->driver_priv
= cfi_info
;
836 cfi_info
->write_algorithm
= NULL
;
838 cfi_info
->x16_as_x8
= 0;
839 cfi_info
->jedec_probe
= 0;
840 cfi_info
->not_cfi
= 0;
842 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
844 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
846 cfi_info
->x16_as_x8
= 1;
848 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
850 cfi_info
->jedec_probe
= 1;
854 cfi_info
->write_algorithm
= NULL
;
856 /* bank wasn't probed yet */
857 cfi_info
->qry
[0] = 0xff;
862 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
865 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
868 cfi_intel_clear_status_register(bank
);
870 for (i
= first
; i
<= last
; i
++)
872 if ((retval
= cfi_send_command(bank
, 0x20, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
877 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
883 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
),
885 if (retval
!= ERROR_OK
)
889 bank
->sectors
[i
].is_erased
= 1;
892 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
897 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
898 return ERROR_FLASH_OPERATION_FAILED
;
902 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
905 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
908 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
909 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
912 for (i
= first
; i
<= last
; i
++)
914 if ((retval
= cfi_send_command(bank
, 0xaa,
915 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
920 if ((retval
= cfi_send_command(bank
, 0x55,
921 flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
926 if ((retval
= cfi_send_command(bank
, 0x80,
927 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
932 if ((retval
= cfi_send_command(bank
, 0xaa,
933 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
938 if ((retval
= cfi_send_command(bank
, 0x55,
939 flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
944 if ((retval
= cfi_send_command(bank
, 0x30,
945 flash_address(bank
, i
, 0x0))) != ERROR_OK
)
950 if (cfi_spansion_wait_status_busy(bank
,
951 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
953 bank
->sectors
[i
].is_erased
= 1;
957 if ((retval
= cfi_send_command(bank
, 0xf0,
958 flash_address(bank
, 0, 0x0))) != ERROR_OK
)
963 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
964 PRIx32
, i
, bank
->base
);
965 return ERROR_FLASH_OPERATION_FAILED
;
969 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
972 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
974 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
976 if (bank
->target
->state
!= TARGET_HALTED
)
978 LOG_ERROR("Target not halted");
979 return ERROR_TARGET_NOT_HALTED
;
982 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
984 return ERROR_FLASH_SECTOR_INVALID
;
987 if (cfi_info
->qry
[0] != 'Q')
988 return ERROR_FLASH_BANK_NOT_PROBED
;
990 switch (cfi_info
->pri_id
)
994 return cfi_intel_erase(bank
, first
, last
);
997 return cfi_spansion_erase(bank
, first
, last
);
1000 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1007 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1010 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1011 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1015 /* if the device supports neither legacy lock/unlock (bit 3) nor
1016 * instant individual block locking (bit 5).
1018 if (!(pri_ext
->feature_support
& 0x28))
1020 LOG_ERROR("lock/unlock not supported on flash");
1021 return ERROR_FLASH_OPERATION_FAILED
;
1024 cfi_intel_clear_status_register(bank
);
1026 for (i
= first
; i
<= last
; i
++)
1028 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1034 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1038 bank
->sectors
[i
].is_protected
= 1;
1042 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1046 bank
->sectors
[i
].is_protected
= 0;
1049 /* instant individual block locking doesn't require reading of the status register */
1050 if (!(pri_ext
->feature_support
& 0x20))
1052 /* Clear lock bits operation may take up to 1.4s */
1054 retval
= cfi_intel_wait_status_busy(bank
, 1400, &status
);
1055 if (retval
!= ERROR_OK
)
1060 uint8_t block_status
;
1061 /* read block lock bit, to verify status */
1062 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1066 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
1067 if (retval
!= ERROR_OK
)
1070 if ((block_status
& 0x1) != set
)
1072 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1074 if ((retval
= cfi_send_command(bank
, 0x70,
1075 flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1080 retval
= cfi_intel_wait_status_busy(bank
, 10, &status
);
1081 if (retval
!= ERROR_OK
)
1085 return ERROR_FLASH_OPERATION_FAILED
;
1095 /* if the device doesn't support individual block lock bits set/clear,
1096 * all blocks have been unlocked in parallel, so we set those that should be protected
1098 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
1100 /* FIX!!! this code path is broken!!!
1102 * The correct approach is:
1104 * 1. read out current protection status
1106 * 2. override read out protection status w/unprotected.
1108 * 3. re-protect what should be protected.
1111 for (i
= 0; i
< bank
->num_sectors
; i
++)
1113 if (bank
->sectors
[i
].is_protected
== 1)
1115 cfi_intel_clear_status_register(bank
);
1117 if ((retval
= cfi_send_command(bank
, 0x60,
1118 flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1123 if ((retval
= cfi_send_command(bank
, 0x01,
1124 flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1130 retval
= cfi_intel_wait_status_busy(bank
, 100, &status
);
1131 if (retval
!= ERROR_OK
)
1137 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
1140 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1142 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1144 if (bank
->target
->state
!= TARGET_HALTED
)
1146 LOG_ERROR("Target not halted");
1147 return ERROR_TARGET_NOT_HALTED
;
1150 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
1152 LOG_ERROR("Invalid sector range");
1153 return ERROR_FLASH_SECTOR_INVALID
;
1156 if (cfi_info
->qry
[0] != 'Q')
1157 return ERROR_FLASH_BANK_NOT_PROBED
;
1159 switch (cfi_info
->pri_id
)
1163 return cfi_intel_protect(bank
, set
, first
, last
);
1166 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
1171 /* Convert code image to target endian */
1172 /* FIXME create general block conversion fcts in target.c?) */
1173 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
,
1174 const uint32_t *src
, uint32_t count
)
1177 for (i
= 0; i
< count
; i
++)
1179 target_buffer_set_u32(target
, dest
, *src
);
1185 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
1187 struct target
*target
= bank
->target
;
1189 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1190 cfi_command(bank
, cmd
, buf
);
1191 switch (bank
->bus_width
)
1197 return target_buffer_get_u16(target
, buf
);
1200 return target_buffer_get_u32(target
, buf
);
1203 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1208 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
1209 uint32_t address
, uint32_t count
)
1211 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1212 struct target
*target
= bank
->target
;
1213 struct reg_param reg_params
[7];
1214 struct arm_algorithm armv4_5_info
;
1215 struct working_area
*source
;
1216 uint32_t buffer_size
= 32768;
1217 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1219 /* algorithm register usage:
1220 * r0: source address (in RAM)
1221 * r1: target address (in Flash)
1223 * r3: flash write command
1224 * r4: status byte (returned to host)
1225 * r5: busy test pattern
1226 * r6: error test pattern
1229 static const uint32_t word_32_code
[] = {
1230 0xe4904004, /* loop: ldr r4, [r0], #4 */
1231 0xe5813000, /* str r3, [r1] */
1232 0xe5814000, /* str r4, [r1] */
1233 0xe5914000, /* busy: ldr r4, [r1] */
1234 0xe0047005, /* and r7, r4, r5 */
1235 0xe1570005, /* cmp r7, r5 */
1236 0x1afffffb, /* bne busy */
1237 0xe1140006, /* tst r4, r6 */
1238 0x1a000003, /* bne done */
1239 0xe2522001, /* subs r2, r2, #1 */
1240 0x0a000001, /* beq done */
1241 0xe2811004, /* add r1, r1 #4 */
1242 0xeafffff2, /* b loop */
1243 0xeafffffe /* done: b -2 */
1246 static const uint32_t word_16_code
[] = {
1247 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1248 0xe1c130b0, /* strh r3, [r1] */
1249 0xe1c140b0, /* strh r4, [r1] */
1250 0xe1d140b0, /* busy ldrh r4, [r1] */
1251 0xe0047005, /* and r7, r4, r5 */
1252 0xe1570005, /* cmp r7, r5 */
1253 0x1afffffb, /* bne busy */
1254 0xe1140006, /* tst r4, r6 */
1255 0x1a000003, /* bne done */
1256 0xe2522001, /* subs r2, r2, #1 */
1257 0x0a000001, /* beq done */
1258 0xe2811002, /* add r1, r1 #2 */
1259 0xeafffff2, /* b loop */
1260 0xeafffffe /* done: b -2 */
1263 static const uint32_t word_8_code
[] = {
1264 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1265 0xe5c13000, /* strb r3, [r1] */
1266 0xe5c14000, /* strb r4, [r1] */
1267 0xe5d14000, /* busy ldrb r4, [r1] */
1268 0xe0047005, /* and r7, r4, r5 */
1269 0xe1570005, /* cmp r7, r5 */
1270 0x1afffffb, /* bne busy */
1271 0xe1140006, /* tst r4, r6 */
1272 0x1a000003, /* bne done */
1273 0xe2522001, /* subs r2, r2, #1 */
1274 0x0a000001, /* beq done */
1275 0xe2811001, /* add r1, r1 #1 */
1276 0xeafffff2, /* b loop */
1277 0xeafffffe /* done: b -2 */
1279 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1280 const uint32_t *target_code_src
;
1281 uint32_t target_code_size
;
1282 int retval
= ERROR_OK
;
1285 cfi_intel_clear_status_register(bank
);
1287 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1288 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1289 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1291 /* If we are setting up the write_algorith, we need target_code_src */
1292 /* if not we only need target_code_size. */
1294 /* However, we don't want to create multiple code paths, so we */
1295 /* do the unecessary evaluation of target_code_src, which the */
1296 /* compiler will probably nicely optimize away if not needed */
1298 /* prepare algorithm code for target endian */
1299 switch (bank
->bus_width
)
1302 target_code_src
= word_8_code
;
1303 target_code_size
= sizeof(word_8_code
);
1306 target_code_src
= word_16_code
;
1307 target_code_size
= sizeof(word_16_code
);
1310 target_code_src
= word_32_code
;
1311 target_code_size
= sizeof(word_32_code
);
1314 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1315 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1318 /* flash write code */
1319 if (!cfi_info
->write_algorithm
)
1321 if (target_code_size
> sizeof(target_code
))
1323 LOG_WARNING("Internal error - target code buffer to small. "
1324 "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1325 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1327 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1329 /* Get memory for block write handler */
1330 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1331 if (retval
!= ERROR_OK
)
1333 LOG_WARNING("No working area available, can't do block memory writes");
1334 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1337 /* write algorithm code to working area */
1338 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1339 target_code_size
, target_code
);
1340 if (retval
!= ERROR_OK
)
1342 LOG_ERROR("Unable to write block write code to target");
1347 /* Get a workspace buffer for the data to flash starting with 32k size.
1348 Half size until buffer would be smaller 256 Bytem then fail back */
1349 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1350 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1353 if (buffer_size
<= 256)
1355 LOG_WARNING("no large enough working area available, can't do block memory writes");
1356 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1361 /* setup algo registers */
1362 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1363 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1364 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1365 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1366 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1367 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1368 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1370 /* prepare command and status register patterns */
1371 write_command_val
= cfi_command_val(bank
, 0x40);
1372 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1373 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1375 LOG_DEBUG("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
,
1376 source
->address
, buffer_size
);
1378 /* Programming main loop */
1381 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1384 if ((retval
= target_write_buffer(target
, source
->address
,
1385 thisrun_count
, buffer
)) != ERROR_OK
)
1390 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1391 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1392 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1394 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1395 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1396 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1398 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1400 /* Execute algorithm, assume breakpoint for last instruction */
1401 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1402 cfi_info
->write_algorithm
->address
,
1403 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1404 10000, /* 10s should be enough for max. 32k of data */
1407 /* On failure try a fall back to direct word writes */
1408 if (retval
!= ERROR_OK
)
1410 cfi_intel_clear_status_register(bank
);
1411 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1412 retval
= ERROR_FLASH_OPERATION_FAILED
;
1413 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1414 /* FIXME To allow fall back or recovery, we must save the actual status
1415 * somewhere, so that a higher level code can start recovery. */
1419 /* Check return value from algo code */
1420 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1423 /* read status register (outputs debug inforation) */
1425 cfi_intel_wait_status_busy(bank
, 100, &status
);
1426 cfi_intel_clear_status_register(bank
);
1427 retval
= ERROR_FLASH_OPERATION_FAILED
;
1431 buffer
+= thisrun_count
;
1432 address
+= thisrun_count
;
1433 count
-= thisrun_count
;
1438 /* free up resources */
1441 target_free_working_area(target
, source
);
1443 if (cfi_info
->write_algorithm
)
1445 target_free_working_area(target
, cfi_info
->write_algorithm
);
1446 cfi_info
->write_algorithm
= NULL
;
1449 destroy_reg_param(®_params
[0]);
1450 destroy_reg_param(®_params
[1]);
1451 destroy_reg_param(®_params
[2]);
1452 destroy_reg_param(®_params
[3]);
1453 destroy_reg_param(®_params
[4]);
1454 destroy_reg_param(®_params
[5]);
1455 destroy_reg_param(®_params
[6]);
1460 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
1461 uint32_t address
, uint32_t count
)
1463 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1464 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1465 struct target
*target
= bank
->target
;
1466 struct reg_param reg_params
[10];
1467 struct arm_algorithm armv4_5_info
;
1468 struct working_area
*source
;
1469 uint32_t buffer_size
= 32768;
1471 int retval
= ERROR_OK
;
1473 /* input parameters - */
1474 /* R0 = source address */
1475 /* R1 = destination address */
1476 /* R2 = number of writes */
1477 /* R3 = flash write command */
1478 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1479 /* output parameters - */
1480 /* R5 = 0x80 ok 0x00 bad */
1481 /* temp registers - */
1482 /* R6 = value read from flash to test status */
1483 /* R7 = holding register */
1484 /* unlock registers - */
1485 /* R8 = unlock1_addr */
1486 /* R9 = unlock1_cmd */
1487 /* R10 = unlock2_addr */
1488 /* R11 = unlock2_cmd */
1490 static const uint32_t word_32_code
[] = {
1491 /* 00008100 <sp_32_code>: */
1492 0xe4905004, /* ldr r5, [r0], #4 */
1493 0xe5889000, /* str r9, [r8] */
1494 0xe58ab000, /* str r11, [r10] */
1495 0xe5883000, /* str r3, [r8] */
1496 0xe5815000, /* str r5, [r1] */
1497 0xe1a00000, /* nop */
1499 /* 00008110 <sp_32_busy>: */
1500 0xe5916000, /* ldr r6, [r1] */
1501 0xe0257006, /* eor r7, r5, r6 */
1502 0xe0147007, /* ands r7, r4, r7 */
1503 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1504 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1505 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1506 0xe5916000, /* ldr r6, [r1] */
1507 0xe0257006, /* eor r7, r5, r6 */
1508 0xe0147007, /* ands r7, r4, r7 */
1509 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1510 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1511 0x1a000004, /* bne 8154 <sp_32_done> */
1513 /* 00008140 <sp_32_cont>: */
1514 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1515 0x03a05080, /* moveq r5, #128 ; 0x80 */
1516 0x0a000001, /* beq 8154 <sp_32_done> */
1517 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1518 0xeaffffe8, /* b 8100 <sp_32_code> */
1520 /* 00008154 <sp_32_done>: */
1521 0xeafffffe /* b 8154 <sp_32_done> */
1524 static const uint32_t word_16_code
[] = {
1525 /* 00008158 <sp_16_code>: */
1526 0xe0d050b2, /* ldrh r5, [r0], #2 */
1527 0xe1c890b0, /* strh r9, [r8] */
1528 0xe1cab0b0, /* strh r11, [r10] */
1529 0xe1c830b0, /* strh r3, [r8] */
1530 0xe1c150b0, /* strh r5, [r1] */
1531 0xe1a00000, /* nop (mov r0,r0) */
1533 /* 00008168 <sp_16_busy>: */
1534 0xe1d160b0, /* ldrh r6, [r1] */
1535 0xe0257006, /* eor r7, r5, r6 */
1536 0xe0147007, /* ands r7, r4, r7 */
1537 0x0a000007, /* beq 8198 <sp_16_cont> */
1538 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1539 0x0afffff9, /* beq 8168 <sp_16_busy> */
1540 0xe1d160b0, /* ldrh r6, [r1] */
1541 0xe0257006, /* eor r7, r5, r6 */
1542 0xe0147007, /* ands r7, r4, r7 */
1543 0x0a000001, /* beq 8198 <sp_16_cont> */
1544 0xe3a05000, /* mov r5, #0 ; 0x0 */
1545 0x1a000004, /* bne 81ac <sp_16_done> */
1547 /* 00008198 <sp_16_cont>: */
1548 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1549 0x03a05080, /* moveq r5, #128 ; 0x80 */
1550 0x0a000001, /* beq 81ac <sp_16_done> */
1551 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1552 0xeaffffe8, /* b 8158 <sp_16_code> */
1554 /* 000081ac <sp_16_done>: */
1555 0xeafffffe /* b 81ac <sp_16_done> */
1558 static const uint32_t word_16_code_dq7only
[] = {
1560 0xe0d050b2, /* ldrh r5, [r0], #2 */
1561 0xe1c890b0, /* strh r9, [r8] */
1562 0xe1cab0b0, /* strh r11, [r10] */
1563 0xe1c830b0, /* strh r3, [r8] */
1564 0xe1c150b0, /* strh r5, [r1] */
1565 0xe1a00000, /* nop (mov r0,r0) */
1568 0xe1d160b0, /* ldrh r6, [r1] */
1569 0xe0257006, /* eor r7, r5, r6 */
1570 0xe2177080, /* ands r7, #0x80 */
1571 0x1afffffb, /* bne 8168 <sp_16_busy> */
1573 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1574 0x03a05080, /* moveq r5, #128 ; 0x80 */
1575 0x0a000001, /* beq 81ac <sp_16_done> */
1576 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1577 0xeafffff0, /* b 8158 <sp_16_code> */
1579 /* 000081ac <sp_16_done>: */
1580 0xeafffffe /* b 81ac <sp_16_done> */
1583 static const uint32_t word_8_code
[] = {
1584 /* 000081b0 <sp_16_code_end>: */
1585 0xe4d05001, /* ldrb r5, [r0], #1 */
1586 0xe5c89000, /* strb r9, [r8] */
1587 0xe5cab000, /* strb r11, [r10] */
1588 0xe5c83000, /* strb r3, [r8] */
1589 0xe5c15000, /* strb r5, [r1] */
1590 0xe1a00000, /* nop (mov r0,r0) */
1592 /* 000081c0 <sp_8_busy>: */
1593 0xe5d16000, /* ldrb r6, [r1] */
1594 0xe0257006, /* eor r7, r5, r6 */
1595 0xe0147007, /* ands r7, r4, r7 */
1596 0x0a000007, /* beq 81f0 <sp_8_cont> */
1597 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1598 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1599 0xe5d16000, /* ldrb r6, [r1] */
1600 0xe0257006, /* eor r7, r5, r6 */
1601 0xe0147007, /* ands r7, r4, r7 */
1602 0x0a000001, /* beq 81f0 <sp_8_cont> */
1603 0xe3a05000, /* mov r5, #0 ; 0x0 */
1604 0x1a000004, /* bne 8204 <sp_8_done> */
1606 /* 000081f0 <sp_8_cont>: */
1607 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1608 0x03a05080, /* moveq r5, #128 ; 0x80 */
1609 0x0a000001, /* beq 8204 <sp_8_done> */
1610 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1611 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1613 /* 00008204 <sp_8_done>: */
1614 0xeafffffe /* b 8204 <sp_8_done> */
1617 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1618 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1619 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1621 int target_code_size
;
1622 const uint32_t *target_code_src
;
1624 switch (bank
->bus_width
)
1627 target_code_src
= word_8_code
;
1628 target_code_size
= sizeof(word_8_code
);
1631 /* Check for DQ5 support */
1632 if( cfi_info
->status_poll_mask
& (1 << 5) )
1634 target_code_src
= word_16_code
;
1635 target_code_size
= sizeof(word_16_code
);
1639 /* No DQ5 support. Use DQ7 DATA# polling only. */
1640 target_code_src
= word_16_code_dq7only
;
1641 target_code_size
= sizeof(word_16_code_dq7only
);
1645 target_code_src
= word_32_code
;
1646 target_code_size
= sizeof(word_32_code
);
1649 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1650 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1653 /* flash write code */
1654 if (!cfi_info
->write_algorithm
)
1656 uint8_t *target_code
;
1658 /* convert bus-width dependent algorithm code to correct endiannes */
1659 target_code
= malloc(target_code_size
);
1660 if (target_code
== NULL
)
1662 LOG_ERROR("Out of memory");
1665 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1667 /* allocate working area */
1668 retval
= target_alloc_working_area(target
, target_code_size
,
1669 &cfi_info
->write_algorithm
);
1670 if (retval
!= ERROR_OK
)
1676 /* write algorithm code to working area */
1677 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1678 target_code_size
, target_code
)) != ERROR_OK
)
1686 /* the following code still assumes target code is fixed 24*4 bytes */
1688 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1691 if (buffer_size
<= 256)
1693 /* if we already allocated the writing code, but failed to get a
1694 * buffer, free the algorithm */
1695 if (cfi_info
->write_algorithm
)
1696 target_free_working_area(target
, cfi_info
->write_algorithm
);
1698 LOG_WARNING("not enough working area available, can't do block memory writes");
1699 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1703 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1704 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1705 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1706 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1707 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1708 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1709 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1710 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1711 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1712 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1716 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1718 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1719 if (retval
!= ERROR_OK
)
1724 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1725 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1726 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1727 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1728 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1729 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1730 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1731 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1732 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1734 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1735 cfi_info
->write_algorithm
->address
,
1736 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1737 10000, &armv4_5_info
);
1738 if (retval
!= ERROR_OK
)
1743 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1746 LOG_ERROR("flash write block failed status: 0x%" PRIx32
, status
);
1747 retval
= ERROR_FLASH_OPERATION_FAILED
;
1751 buffer
+= thisrun_count
;
1752 address
+= thisrun_count
;
1753 count
-= thisrun_count
;
1756 target_free_all_working_areas(target
);
1758 destroy_reg_param(®_params
[0]);
1759 destroy_reg_param(®_params
[1]);
1760 destroy_reg_param(®_params
[2]);
1761 destroy_reg_param(®_params
[3]);
1762 destroy_reg_param(®_params
[4]);
1763 destroy_reg_param(®_params
[5]);
1764 destroy_reg_param(®_params
[6]);
1765 destroy_reg_param(®_params
[7]);
1766 destroy_reg_param(®_params
[8]);
1767 destroy_reg_param(®_params
[9]);
1772 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1775 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1776 struct target
*target
= bank
->target
;
1778 cfi_intel_clear_status_register(bank
);
1779 if ((retval
= cfi_send_command(bank
, 0x40, address
)) != ERROR_OK
)
1784 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1790 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
),
1794 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1799 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
,
1800 bank
->base
, address
);
1801 return ERROR_FLASH_OPERATION_FAILED
;
1807 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
,
1808 uint32_t wordcount
, uint32_t address
)
1811 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1812 struct target
*target
= bank
->target
;
1814 /* Calculate buffer size and boundary mask */
1815 /* buffersize is (buffer size per chip) * (number of chips) */
1816 /* bufferwsize is buffersize in words */
1817 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1818 uint32_t buffermask
= buffersize
-1;
1819 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1821 /* Check for valid range */
1822 if (address
& buffermask
)
1824 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
1825 " not aligned to 2^%d boundary",
1826 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1827 return ERROR_FLASH_OPERATION_FAILED
;
1830 /* Check for valid size */
1831 if (wordcount
> bufferwsize
)
1833 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
,
1834 wordcount
, buffersize
);
1835 return ERROR_FLASH_OPERATION_FAILED
;
1838 /* Write to flash buffer */
1839 cfi_intel_clear_status_register(bank
);
1841 /* Initiate buffer operation _*/
1842 if ((retval
= cfi_send_command(bank
, 0xe8, address
)) != ERROR_OK
)
1847 retval
= cfi_intel_wait_status_busy(bank
,
1848 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1849 if (retval
!= ERROR_OK
)
1853 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1858 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
,
1859 bank
->base
, address
);
1860 return ERROR_FLASH_OPERATION_FAILED
;
1863 /* Write buffer wordcount-1 and data words */
1864 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1869 if ((retval
= target_write_memory(target
,
1870 address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1875 /* Commit write operation */
1876 if ((retval
= cfi_send_command(bank
, 0xd0, address
)) != ERROR_OK
)
1881 retval
= cfi_intel_wait_status_busy(bank
,
1882 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1883 if (retval
!= ERROR_OK
)
1888 if ((retval
= cfi_send_command(bank
, 0xff,
1889 flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1894 LOG_ERROR("Buffer write at base 0x%" PRIx32
1895 ", address %" PRIx32
" failed.", bank
->base
, address
);
1896 return ERROR_FLASH_OPERATION_FAILED
;
1902 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1905 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1906 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1907 struct target
*target
= bank
->target
;
1909 if ((retval
= cfi_send_command(bank
, 0xaa,
1910 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1915 if ((retval
= cfi_send_command(bank
, 0x55,
1916 flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1921 if ((retval
= cfi_send_command(bank
, 0xa0,
1922 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1927 if ((retval
= target_write_memory(target
,
1928 address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1933 if (cfi_spansion_wait_status_busy(bank
,
1934 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1936 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1941 LOG_ERROR("couldn't write word at base 0x%" PRIx32
1942 ", address %" PRIx32
, bank
->base
, address
);
1943 return ERROR_FLASH_OPERATION_FAILED
;
1949 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
,
1950 uint32_t wordcount
, uint32_t address
)
1953 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1954 struct target
*target
= bank
->target
;
1955 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1957 /* Calculate buffer size and boundary mask */
1958 /* buffersize is (buffer size per chip) * (number of chips) */
1959 /* bufferwsize is buffersize in words */
1960 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1961 uint32_t buffermask
= buffersize
-1;
1962 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1964 /* Check for valid range */
1965 if (address
& buffermask
)
1967 LOG_ERROR("Write address at base 0x%" PRIx32
1968 ", address %" PRIx32
" not aligned to 2^%d boundary",
1969 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1970 return ERROR_FLASH_OPERATION_FAILED
;
1973 /* Check for valid size */
1974 if (wordcount
> bufferwsize
)
1976 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %"
1977 PRId32
, wordcount
, buffersize
);
1978 return ERROR_FLASH_OPERATION_FAILED
;
1982 if ((retval
= cfi_send_command(bank
, 0xaa,
1983 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1988 if ((retval
= cfi_send_command(bank
, 0x55,
1989 flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1994 // Buffer load command
1995 if ((retval
= cfi_send_command(bank
, 0x25, address
)) != ERROR_OK
)
2000 /* Write buffer wordcount-1 and data words */
2001 if ((retval
= cfi_send_command(bank
,
2002 bufferwsize
-1, address
)) != ERROR_OK
)
2007 if ((retval
= target_write_memory(target
,
2008 address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
2013 /* Commit write operation */
2014 if ((retval
= cfi_send_command(bank
, 0x29, address
)) != ERROR_OK
)
2019 if (cfi_spansion_wait_status_busy(bank
,
2020 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
2022 if ((retval
= cfi_send_command(bank
, 0xf0,
2023 flash_address(bank
, 0, 0x0))) != ERROR_OK
)
2028 LOG_ERROR("couldn't write block at base 0x%" PRIx32
2029 ", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
2030 return ERROR_FLASH_OPERATION_FAILED
;
2036 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
2038 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2040 switch (cfi_info
->pri_id
)
2044 return cfi_intel_write_word(bank
, word
, address
);
2047 return cfi_spansion_write_word(bank
, word
, address
);
2050 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2054 return ERROR_FLASH_OPERATION_FAILED
;
2057 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
,
2058 uint32_t wordcount
, uint32_t address
)
2060 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2062 switch (cfi_info
->pri_id
)
2066 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
2069 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
2072 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2076 return ERROR_FLASH_OPERATION_FAILED
;
2079 static int cfi_read(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2081 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2082 struct target
*target
= bank
->target
;
2083 uint32_t address
= bank
->base
+ offset
;
2085 int align
; /* number of unaligned bytes */
2086 uint8_t current_word
[CFI_MAX_BUS_WIDTH
];
2090 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2091 (int)count
, (unsigned)offset
);
2093 if (bank
->target
->state
!= TARGET_HALTED
)
2095 LOG_ERROR("Target not halted");
2096 return ERROR_TARGET_NOT_HALTED
;
2099 if (offset
+ count
> bank
->size
)
2100 return ERROR_FLASH_DST_OUT_OF_BANK
;
2102 if (cfi_info
->qry
[0] != 'Q')
2103 return ERROR_FLASH_BANK_NOT_PROBED
;
2105 /* start at the first byte of the first word (bus_width size) */
2106 read_p
= address
& ~(bank
->bus_width
- 1);
2107 if ((align
= address
- read_p
) != 0)
2109 LOG_INFO("Fixup %d unaligned read head bytes", align
);
2111 /* read a complete word from flash */
2112 if ((retval
= target_read_memory(target
, read_p
,
2113 bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2116 /* take only bytes we need */
2117 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2118 *buffer
++ = current_word
[i
];
2120 read_p
+= bank
->bus_width
;
2123 align
= count
/ bank
->bus_width
;
2126 if ((retval
= target_read_memory(target
, read_p
,
2127 bank
->bus_width
, align
, buffer
)) != ERROR_OK
)
2130 read_p
+= align
* bank
->bus_width
;
2131 buffer
+= align
* bank
->bus_width
;
2132 count
-= align
* bank
->bus_width
;
2137 LOG_INFO("Fixup %d unaligned read tail bytes", count
);
2139 /* read a complete word from flash */
2140 if ((retval
= target_read_memory(target
, read_p
,
2141 bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2144 /* take only bytes we need */
2145 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2146 *buffer
++ = current_word
[i
];
2152 static int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2154 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2155 struct target
*target
= bank
->target
;
2156 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
2158 int align
; /* number of unaligned bytes */
2159 int blk_count
; /* number of bus_width bytes for block copy */
2160 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
2164 if (bank
->target
->state
!= TARGET_HALTED
)
2166 LOG_ERROR("Target not halted");
2167 return ERROR_TARGET_NOT_HALTED
;
2170 if (offset
+ count
> bank
->size
)
2171 return ERROR_FLASH_DST_OUT_OF_BANK
;
2173 if (cfi_info
->qry
[0] != 'Q')
2174 return ERROR_FLASH_BANK_NOT_PROBED
;
2176 /* start at the first byte of the first word (bus_width size) */
2177 write_p
= address
& ~(bank
->bus_width
- 1);
2178 if ((align
= address
- write_p
) != 0)
2180 LOG_INFO("Fixup %d unaligned head bytes", align
);
2182 /* read a complete word from flash */
2183 if ((retval
= target_read_memory(target
, write_p
,
2184 bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2187 /* replace only bytes that must be written */
2188 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2189 current_word
[i
] = *buffer
++;
2191 retval
= cfi_write_word(bank
, current_word
, write_p
);
2192 if (retval
!= ERROR_OK
)
2194 write_p
+= bank
->bus_width
;
2197 /* handle blocks of bus_size aligned bytes */
2198 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
2199 switch (cfi_info
->pri_id
)
2201 /* try block writes (fails without working area) */
2204 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
2207 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
2210 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2211 retval
= ERROR_FLASH_OPERATION_FAILED
;
2214 if (retval
== ERROR_OK
)
2216 /* Increment pointers and decrease count on succesful block write */
2217 buffer
+= blk_count
;
2218 write_p
+= blk_count
;
2223 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
2225 /* Calculate buffer size and boundary mask */
2226 /* buffersize is (buffer size per chip) * (number of chips) */
2227 /* bufferwsize is buffersize in words */
2228 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
2229 uint32_t buffermask
= buffersize
-1;
2230 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2232 /* fall back to memory writes */
2233 while (count
>= (uint32_t)bank
->bus_width
)
2236 if ((write_p
& 0xff) == 0)
2238 LOG_INFO("Programming at %08" PRIx32
", count %08"
2239 PRIx32
" bytes remaining", write_p
, count
);
2242 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
2244 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
2245 if (retval
== ERROR_OK
)
2247 buffer
+= buffersize
;
2248 write_p
+= buffersize
;
2249 count
-= buffersize
;
2253 /* try the slow way? */
2256 for (i
= 0; i
< bank
->bus_width
; i
++)
2257 current_word
[i
] = *buffer
++;
2259 retval
= cfi_write_word(bank
, current_word
, write_p
);
2260 if (retval
!= ERROR_OK
)
2263 write_p
+= bank
->bus_width
;
2264 count
-= bank
->bus_width
;
2272 /* return to read array mode, so we can read from flash again for padding */
2273 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2278 /* handle unaligned tail bytes */
2281 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2283 /* read a complete word from flash */
2284 if ((retval
= target_read_memory(target
, write_p
,
2285 bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2288 /* replace only bytes that must be written */
2289 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2290 current_word
[i
] = *buffer
++;
2292 retval
= cfi_write_word(bank
, current_word
, write_p
);
2293 if (retval
!= ERROR_OK
)
2297 /* return to read array mode */
2298 return cfi_reset(bank
);
2301 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2304 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2305 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2307 pri_ext
->_reversed_geometry
= 1;
2310 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2313 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2314 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2317 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2319 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2321 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2323 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2326 swap
= cfi_info
->erase_region_info
[i
];
2327 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2328 cfi_info
->erase_region_info
[j
] = swap
;
2333 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2335 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2336 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2337 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2339 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2340 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2344 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2346 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2349 if ((retval
= cfi_send_command(bank
, 0x98, flash_address(bank
, 0, address
))) != ERROR_OK
)
2354 retval
= cfi_query_u8(bank
, 0, 0x10, &cfi_info
->qry
[0]);
2355 if (retval
!= ERROR_OK
)
2357 retval
= cfi_query_u8(bank
, 0, 0x11, &cfi_info
->qry
[1]);
2358 if (retval
!= ERROR_OK
)
2360 retval
= cfi_query_u8(bank
, 0, 0x12, &cfi_info
->qry
[2]);
2361 if (retval
!= ERROR_OK
)
2364 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2365 cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2367 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2369 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2373 LOG_ERROR("Could not probe bank: no QRY");
2374 return ERROR_FLASH_BANK_INVALID
;
2380 static int cfi_probe(struct flash_bank
*bank
)
2382 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2383 struct target
*target
= bank
->target
;
2384 int num_sectors
= 0;
2387 uint32_t unlock1
= 0x555;
2388 uint32_t unlock2
= 0x2aa;
2390 uint8_t value_buf0
[CFI_MAX_BUS_WIDTH
], value_buf1
[CFI_MAX_BUS_WIDTH
];
2392 if (bank
->target
->state
!= TARGET_HALTED
)
2394 LOG_ERROR("Target not halted");
2395 return ERROR_TARGET_NOT_HALTED
;
2398 cfi_info
->probed
= 0;
2401 free(bank
->sectors
);
2402 bank
->sectors
= NULL
;
2404 if(cfi_info
->erase_region_info
)
2406 free(cfi_info
->erase_region_info
);
2407 cfi_info
->erase_region_info
= NULL
;
2410 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2411 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2413 if (cfi_info
->jedec_probe
)
2419 /* switch to read identifier codes mode ("AUTOSELECT") */
2420 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2424 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, unlock2
))) != ERROR_OK
)
2428 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2433 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x00),
2434 bank
->bus_width
, 1, value_buf0
)) != ERROR_OK
)
2438 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x01),
2439 bank
->bus_width
, 1, value_buf1
)) != ERROR_OK
)
2443 switch (bank
->chip_width
) {
2445 cfi_info
->manufacturer
= *value_buf0
;
2446 cfi_info
->device_id
= *value_buf1
;
2449 cfi_info
->manufacturer
= target_buffer_get_u16(target
, value_buf0
);
2450 cfi_info
->device_id
= target_buffer_get_u16(target
, value_buf1
);
2453 cfi_info
->manufacturer
= target_buffer_get_u32(target
, value_buf0
);
2454 cfi_info
->device_id
= target_buffer_get_u32(target
, value_buf1
);
2457 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank
->chip_width
);
2458 return ERROR_FLASH_OPERATION_FAILED
;
2461 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2462 cfi_info
->manufacturer
, cfi_info
->device_id
);
2463 /* switch back to read array mode */
2464 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2469 /* check device/manufacturer ID for known non-CFI flashes. */
2470 cfi_fixup_non_cfi(bank
);
2472 /* query only if this is a CFI compatible flash,
2473 * otherwise the relevant info has already been filled in
2475 if (cfi_info
->not_cfi
== 0)
2477 /* enter CFI query mode
2478 * according to JEDEC Standard No. 68.01,
2479 * a single bus sequence with address = 0x55, data = 0x98 should put
2480 * the device into CFI query mode.
2482 * SST flashes clearly violate this, and we will consider them incompatbile for now
2485 retval
= cfi_query_string(bank
, 0x55);
2486 if (retval
!= ERROR_OK
)
2489 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2490 * be harmless enough:
2492 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2494 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2495 retval
= cfi_query_string(bank
, 0x555);
2497 if (retval
!= ERROR_OK
)
2500 retval
= cfi_query_u16(bank
, 0, 0x13, &cfi_info
->pri_id
);
2501 if (retval
!= ERROR_OK
)
2503 retval
= cfi_query_u16(bank
, 0, 0x15, &cfi_info
->pri_addr
);
2504 if (retval
!= ERROR_OK
)
2506 retval
= cfi_query_u16(bank
, 0, 0x17, &cfi_info
->alt_id
);
2507 if (retval
!= ERROR_OK
)
2509 retval
= cfi_query_u16(bank
, 0, 0x19, &cfi_info
->alt_addr
);
2510 if (retval
!= ERROR_OK
)
2513 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2514 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1],
2515 cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
,
2516 cfi_info
->alt_id
, cfi_info
->alt_addr
);
2518 retval
= cfi_query_u8(bank
, 0, 0x1b, &cfi_info
->vcc_min
);
2519 if (retval
!= ERROR_OK
)
2521 retval
= cfi_query_u8(bank
, 0, 0x1c, &cfi_info
->vcc_max
);
2522 if (retval
!= ERROR_OK
)
2524 retval
= cfi_query_u8(bank
, 0, 0x1d, &cfi_info
->vpp_min
);
2525 if (retval
!= ERROR_OK
)
2527 retval
= cfi_query_u8(bank
, 0, 0x1e, &cfi_info
->vpp_max
);
2528 if (retval
!= ERROR_OK
)
2530 retval
= cfi_query_u8(bank
, 0, 0x1f, &cfi_info
->word_write_timeout_typ
);
2531 if (retval
!= ERROR_OK
)
2533 retval
= cfi_query_u8(bank
, 0, 0x20, &cfi_info
->buf_write_timeout_typ
);
2534 if (retval
!= ERROR_OK
)
2536 retval
= cfi_query_u8(bank
, 0, 0x21, &cfi_info
->block_erase_timeout_typ
);
2537 if (retval
!= ERROR_OK
)
2539 retval
= cfi_query_u8(bank
, 0, 0x22, &cfi_info
->chip_erase_timeout_typ
);
2540 if (retval
!= ERROR_OK
)
2542 retval
= cfi_query_u8(bank
, 0, 0x23, &cfi_info
->word_write_timeout_max
);
2543 if (retval
!= ERROR_OK
)
2545 retval
= cfi_query_u8(bank
, 0, 0x24, &cfi_info
->buf_write_timeout_max
);
2546 if (retval
!= ERROR_OK
)
2548 retval
= cfi_query_u8(bank
, 0, 0x25, &cfi_info
->block_erase_timeout_max
);
2549 if (retval
!= ERROR_OK
)
2551 retval
= cfi_query_u8(bank
, 0, 0x26, &cfi_info
->chip_erase_timeout_max
);
2552 if (retval
!= ERROR_OK
)
2555 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2556 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2557 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2558 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2559 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2561 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, "
2562 "typ. block erase timeout: %u, typ. chip erase timeout: %u",
2563 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2564 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2566 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, "
2567 "max. block erase timeout: %u, max. chip erase timeout: %u",
2568 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2569 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2570 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2571 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2574 retval
= cfi_query_u8(bank
, 0, 0x27, &data
);
2575 if (retval
!= ERROR_OK
)
2577 cfi_info
->dev_size
= 1 << data
;
2579 retval
= cfi_query_u16(bank
, 0, 0x28, &cfi_info
->interface_desc
);
2580 if (retval
!= ERROR_OK
)
2582 retval
= cfi_query_u16(bank
, 0, 0x2a, &cfi_info
->max_buf_write_size
);
2583 if (retval
!= ERROR_OK
)
2585 retval
= cfi_query_u8(bank
, 0, 0x2c, &cfi_info
->num_erase_regions
);
2586 if (retval
!= ERROR_OK
)
2589 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x",
2590 cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2592 if (cfi_info
->num_erase_regions
)
2594 cfi_info
->erase_region_info
= malloc(sizeof(*cfi_info
->erase_region_info
)
2595 * cfi_info
->num_erase_regions
);
2596 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2598 retval
= cfi_query_u32(bank
, 0, 0x2d + (4 * i
), &cfi_info
->erase_region_info
[i
]);
2599 if (retval
!= ERROR_OK
)
2601 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"", i
,
2602 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2603 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2608 cfi_info
->erase_region_info
= NULL
;
2611 /* We need to read the primary algorithm extended query table before calculating
2612 * the sector layout to be able to apply fixups
2614 switch (cfi_info
->pri_id
)
2616 /* Intel command set (standard and extended) */
2619 cfi_read_intel_pri_ext(bank
);
2621 /* AMD/Spansion, Atmel, ... command set */
2623 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2624 cfi_read_0002_pri_ext(bank
);
2627 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2631 /* return to read array mode
2632 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2634 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2638 } /* end CFI case */
2640 /* apply fixups depending on the primary command set */
2641 switch (cfi_info
->pri_id
)
2643 /* Intel command set (standard and extended) */
2646 cfi_fixup(bank
, cfi_0001_fixups
);
2648 /* AMD/Spansion, Atmel, ... command set */
2650 cfi_fixup(bank
, cfi_0002_fixups
);
2653 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2657 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2659 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
2660 " size flash was found", bank
->size
, cfi_info
->dev_size
);
2663 if (cfi_info
->num_erase_regions
== 0)
2665 /* a device might have only one erase block, spanning the whole device */
2666 bank
->num_sectors
= 1;
2667 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2669 bank
->sectors
[sector
].offset
= 0x0;
2670 bank
->sectors
[sector
].size
= bank
->size
;
2671 bank
->sectors
[sector
].is_erased
= -1;
2672 bank
->sectors
[sector
].is_protected
= -1;
2676 uint32_t offset
= 0;
2678 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2680 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2683 bank
->num_sectors
= num_sectors
;
2684 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2686 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2689 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2691 bank
->sectors
[sector
].offset
= offset
;
2692 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256)
2693 * bank
->bus_width
/ bank
->chip_width
;
2694 offset
+= bank
->sectors
[sector
].size
;
2695 bank
->sectors
[sector
].is_erased
= -1;
2696 bank
->sectors
[sector
].is_protected
= -1;
2700 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2702 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2703 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2707 cfi_info
->probed
= 1;
2712 static int cfi_auto_probe(struct flash_bank
*bank
)
2714 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2715 if (cfi_info
->probed
)
2717 return cfi_probe(bank
);
2720 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2723 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2724 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2727 /* check if block lock bits are supported on this device */
2728 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2729 return ERROR_FLASH_OPERATION_FAILED
;
2731 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
2736 for (i
= 0; i
< bank
->num_sectors
; i
++)
2738 uint8_t block_status
;
2739 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2740 if (retval
!= ERROR_OK
)
2743 if (block_status
& 1)
2744 bank
->sectors
[i
].is_protected
= 1;
2746 bank
->sectors
[i
].is_protected
= 0;
2749 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2752 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2755 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2756 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2759 if ((retval
= cfi_send_command(bank
, 0xaa,
2760 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2765 if ((retval
= cfi_send_command(bank
, 0x55,
2766 flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
2771 if ((retval
= cfi_send_command(bank
, 0x90,
2772 flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2777 for (i
= 0; i
< bank
->num_sectors
; i
++)
2779 uint8_t block_status
;
2780 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2781 if (retval
!= ERROR_OK
)
2784 if (block_status
& 1)
2785 bank
->sectors
[i
].is_protected
= 1;
2787 bank
->sectors
[i
].is_protected
= 0;
2790 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
2793 static int cfi_protect_check(struct flash_bank
*bank
)
2795 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2797 if (bank
->target
->state
!= TARGET_HALTED
)
2799 LOG_ERROR("Target not halted");
2800 return ERROR_TARGET_NOT_HALTED
;
2803 if (cfi_info
->qry
[0] != 'Q')
2804 return ERROR_FLASH_BANK_NOT_PROBED
;
2806 switch (cfi_info
->pri_id
)
2810 return cfi_intel_protect_check(bank
);
2813 return cfi_spansion_protect_check(bank
);
2816 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2823 static int get_cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2826 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2828 if (cfi_info
->qry
[0] == 0xff)
2830 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2834 if (cfi_info
->not_cfi
== 0)
2835 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2837 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2839 buf_size
-= printed
;
2841 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2842 cfi_info
->manufacturer
, cfi_info
->device_id
);
2844 buf_size
-= printed
;
2846 if (cfi_info
->not_cfi
== 0)
2848 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2849 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2850 cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2],
2851 cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2853 buf_size
-= printed
;
2855 printed
= snprintf(buf
, buf_size
, "Vcc min: %x.%x, Vcc max: %x.%x, "
2856 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2857 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2858 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2859 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2860 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2862 buf_size
-= printed
;
2864 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, "
2865 "typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2866 1 << cfi_info
->word_write_timeout_typ
,
2867 1 << cfi_info
->buf_write_timeout_typ
,
2868 1 << cfi_info
->block_erase_timeout_typ
,
2869 1 << cfi_info
->chip_erase_timeout_typ
);
2871 buf_size
-= printed
;
2873 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, "
2874 "max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2875 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2876 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2877 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2878 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2880 buf_size
-= printed
;
2882 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, "
2883 "max buffer write size: %x\n",
2885 cfi_info
->interface_desc
,
2886 1 << cfi_info
->max_buf_write_size
);
2888 buf_size
-= printed
;
2890 switch (cfi_info
->pri_id
)
2894 cfi_intel_info(bank
, buf
, buf_size
);
2897 cfi_spansion_info(bank
, buf
, buf_size
);
2900 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2908 struct flash_driver cfi_flash
= {
2910 .flash_bank_command
= cfi_flash_bank_command
,
2912 .protect
= cfi_protect
,
2916 .auto_probe
= cfi_auto_probe
,
2917 /* FIXME: access flash at bus_width size */
2918 .erase_check
= default_flash_blank_check
,
2919 .protect_check
= cfi_protect_check
,
2920 .info
= get_cfi_info
,
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