1 /***************************************************************************
2 * Copyright (C) 2017 by Tomas Vanek *
5 * Based on at91samd.c *
6 * Copyright (C) 2013 by Andrey Yurovsky *
7 * Andrey Yurovsky <yurovsky@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
28 #include "helper/binarybuffer.h"
30 #include <helper/time_support.h>
31 #include <target/cortex_m.h>
33 /* A note to prefixing.
34 * Definitions and functions inherited from at91samd.c without
35 * any change retained the original prefix samd_ so they eventually
36 * may go to samd_common.h and .c
37 * As currently there are only 3 short functions identical with
38 * the original source, no common file was created. */
40 #define SAME5_PAGES_PER_BLOCK 16
41 #define SAME5_NUM_PROT_BLOCKS 32
42 #define SAMD_PAGE_SIZE_MAX 1024
44 #define SAMD_FLASH 0x00000000 /* physical Flash memory */
45 #define SAMD_USER_ROW 0x00804000 /* User Row of Flash */
47 #define SAME5_PAC 0x40000000 /* Peripheral Access Control */
49 #define SAMD_DSU 0x41002000 /* Device Service Unit */
50 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
52 #define SAMD_DSU_STATUSA 1 /* DSU status register */
53 #define SAMD_DSU_DID 0x18 /* Device ID register */
54 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
56 #define SAME5_NVMCTRL_CTRLA 0x00 /* NVM control A register */
57 #define SAME5_NVMCTRL_CTRLB 0x04 /* NVM control B register */
58 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
59 #define SAME5_NVMCTRL_INTFLAG 0x10 /* NVM interrupt flag register */
60 #define SAME5_NVMCTRL_STATUS 0x12 /* NVM status register */
61 #define SAME5_NVMCTRL_ADDR 0x14 /* NVM address register */
62 #define SAME5_NVMCTRL_LOCK 0x18 /* NVM Lock section register */
64 #define SAMD_CMDEX_KEY 0xA5UL
65 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
67 /* NVMCTRL commands. */
68 #define SAME5_NVM_CMD_EP 0x00 /* Erase Page (User Page only) */
69 #define SAME5_NVM_CMD_EB 0x01 /* Erase Block */
70 #define SAME5_NVM_CMD_WP 0x03 /* Write Page */
71 #define SAME5_NVM_CMD_WQW 0x04 /* Write Quad Word */
72 #define SAME5_NVM_CMD_LR 0x11 /* Lock Region */
73 #define SAME5_NVM_CMD_UR 0x12 /* Unlock Region */
74 #define SAME5_NVM_CMD_PBC 0x15 /* Page Buffer Clear */
75 #define SAME5_NVM_CMD_SSB 0x16 /* Set Security Bit */
78 #define SAME5_NVMCTRL_CTRLA_WMODE_MASK 0x30
80 #define SAME5_NVMCTRL_INTFLAG_DONE (1 << 0)
81 #define SAME5_NVMCTRL_INTFLAG_ADDRE (1 << 1)
82 #define SAME5_NVMCTRL_INTFLAG_PROGE (1 << 2)
83 #define SAME5_NVMCTRL_INTFLAG_LOCKE (1 << 3)
84 #define SAME5_NVMCTRL_INTFLAG_ECCSE (1 << 4)
85 #define SAME5_NVMCTRL_INTFLAG_ECCDE (1 << 5)
86 #define SAME5_NVMCTRL_INTFLAG_NVME (1 << 6)
89 /* Known identifiers */
90 #define SAMD_PROCESSOR_M0 0x01
91 #define SAMD_PROCESSOR_M4 0x06
92 #define SAMD_FAMILY_D 0x00
93 #define SAMD_FAMILY_E 0x03
94 #define SAMD_SERIES_51 0x06
95 #define SAME_SERIES_51 0x01
96 #define SAME_SERIES_53 0x03
97 #define SAME_SERIES_54 0x04
99 /* Device ID macros */
100 #define SAMD_GET_PROCESSOR(id) (id >> 28)
101 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
102 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
103 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
105 /* Bits to mask user row */
106 #define NVMUSERROW_SAM_E5_D5_MASK ((uint64_t)0x7FFF00FF3C007FFF)
115 /* See SAM D5x/E5x Family Silicon Errata and Data Sheet Clarification
117 /* Known SAMD51 parts. */
118 static const struct samd_part samd51_parts
[] = {
119 { 0x00, "SAMD51P20A", 1024, 256 },
120 { 0x01, "SAMD51P19A", 512, 192 },
121 { 0x02, "SAMD51N20A", 1024, 256 },
122 { 0x03, "SAMD51N19A", 512, 192 },
123 { 0x04, "SAMD51J20A", 1024, 256 },
124 { 0x05, "SAMD51J19A", 512, 192 },
125 { 0x06, "SAMD51J18A", 256, 128 },
126 { 0x07, "SAMD51G19A", 512, 192 },
127 { 0x08, "SAMD51G18A", 256, 128 },
130 /* Known SAME51 parts. */
131 static const struct samd_part same51_parts
[] = {
132 { 0x00, "SAME51N20A", 1024, 256 },
133 { 0x01, "SAME51N19A", 512, 192 },
134 { 0x02, "SAME51J19A", 512, 192 },
135 { 0x03, "SAME51J18A", 256, 128 },
136 { 0x04, "SAME51J20A", 1024, 256 },
139 /* Known SAME53 parts. */
140 static const struct samd_part same53_parts
[] = {
141 { 0x02, "SAME53N20A", 1024, 256 },
142 { 0x03, "SAME53N19A", 512, 192 },
143 { 0x04, "SAME53J20A", 1024, 256 },
144 { 0x05, "SAME53J19A", 512, 192 },
145 { 0x06, "SAME53J18A", 256, 128 },
148 /* Known SAME54 parts. */
149 static const struct samd_part same54_parts
[] = {
150 { 0x00, "SAME54P20A", 1024, 256 },
151 { 0x01, "SAME54P19A", 512, 192 },
152 { 0x02, "SAME54N20A", 1024, 256 },
153 { 0x03, "SAME54N19A", 512, 192 },
156 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
157 * processor ID, family ID, and series ID are used to determine which exact
158 * family this is and then we can use the corresponding table. */
163 const struct samd_part
*parts
;
167 /* Known SAMD families */
168 static const struct samd_family samd_families
[] = {
169 { SAMD_PROCESSOR_M4
, SAMD_FAMILY_D
, SAMD_SERIES_51
,
170 samd51_parts
, ARRAY_SIZE(samd51_parts
) },
171 { SAMD_PROCESSOR_M4
, SAMD_FAMILY_E
, SAME_SERIES_51
,
172 same51_parts
, ARRAY_SIZE(same51_parts
) },
173 { SAMD_PROCESSOR_M4
, SAMD_FAMILY_E
, SAME_SERIES_53
,
174 same53_parts
, ARRAY_SIZE(same53_parts
) },
175 { SAMD_PROCESSOR_M4
, SAMD_FAMILY_E
, SAME_SERIES_54
,
176 same54_parts
, ARRAY_SIZE(same54_parts
) },
180 const struct samd_params
*par
;
187 struct target
*target
;
192 * Gives the family structure to specific device id.
193 * @param id The id of the device.
194 * @return On failure NULL, otherwise a pointer to the structure.
196 static const struct samd_family
*samd_find_family(uint32_t id
)
198 uint8_t processor
= SAMD_GET_PROCESSOR(id
);
199 uint8_t family
= SAMD_GET_FAMILY(id
);
200 uint8_t series
= SAMD_GET_SERIES(id
);
202 for (unsigned i
= 0; i
< ARRAY_SIZE(samd_families
); i
++) {
203 if (samd_families
[i
].processor
== processor
&&
204 samd_families
[i
].series
== series
&&
205 samd_families
[i
].family
== family
)
206 return &samd_families
[i
];
213 * Gives the part structure to specific device id.
214 * @param id The id of the device.
215 * @return On failure NULL, otherwise a pointer to the structure.
217 static const struct samd_part
*samd_find_part(uint32_t id
)
219 uint8_t devsel
= SAMD_GET_DEVSEL(id
);
220 const struct samd_family
*family
= samd_find_family(id
);
224 for (unsigned i
= 0; i
< family
->num_parts
; i
++) {
225 if (family
->parts
[i
].id
== devsel
)
226 return &family
->parts
[i
];
232 static int same5_protect_check(struct flash_bank
*bank
)
237 res
= target_read_u32(bank
->target
,
238 SAMD_NVMCTRL
+ SAME5_NVMCTRL_LOCK
, &lock
);
242 /* Lock bits are active-low */
243 for (unsigned int prot_block
= 0; prot_block
< bank
->num_prot_blocks
; prot_block
++)
244 bank
->prot_blocks
[prot_block
].is_protected
= !(lock
& (1u<<prot_block
));
249 static int samd_get_flash_page_info(struct target
*target
,
250 uint32_t *sizep
, int *nump
)
255 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_PARAM
, ¶m
);
256 if (res
== ERROR_OK
) {
257 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
258 * so 0 is 8KB and 7 is 1024KB. */
260 *sizep
= (8 << ((param
>> 16) & 0x7));
261 /* The NVMP field (bits 15:0) indicates the total number of pages */
263 *nump
= param
& 0xFFFF;
265 LOG_ERROR("Couldn't read NVM Parameters register");
271 static int same5_probe(struct flash_bank
*bank
)
275 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
276 const struct samd_part
*part
;
281 res
= target_read_u32(bank
->target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
282 if (res
!= ERROR_OK
) {
283 LOG_ERROR("Couldn't read Device ID register");
287 part
= samd_find_part(id
);
289 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32
, id
);
293 bank
->size
= part
->flash_kb
* 1024;
295 res
= samd_get_flash_page_info(bank
->target
, &chip
->page_size
,
297 if (res
!= ERROR_OK
) {
298 LOG_ERROR("Couldn't determine Flash page size");
302 /* Sanity check: the total flash size in the DSU should match the page size
303 * multiplied by the number of pages. */
304 if (bank
->size
!= chip
->num_pages
* chip
->page_size
) {
305 LOG_WARNING("SAM: bank size doesn't match NVM parameters. "
306 "Identified %" PRIu32
"KB Flash but NVMCTRL reports %u %" PRIu32
"B pages",
307 part
->flash_kb
, chip
->num_pages
, chip
->page_size
);
310 /* Erase granularity = 1 block = 16 pages */
311 chip
->sector_size
= chip
->page_size
* SAME5_PAGES_PER_BLOCK
;
313 /* Allocate the sector table */
314 bank
->num_sectors
= chip
->num_pages
/ SAME5_PAGES_PER_BLOCK
;
315 bank
->sectors
= alloc_block_array(0, chip
->sector_size
, bank
->num_sectors
);
319 /* 16 protection blocks per device */
320 chip
->prot_block_size
= bank
->size
/ SAME5_NUM_PROT_BLOCKS
;
322 /* Allocate the table of protection blocks */
323 bank
->num_prot_blocks
= SAME5_NUM_PROT_BLOCKS
;
324 bank
->prot_blocks
= alloc_block_array(0, chip
->prot_block_size
, bank
->num_prot_blocks
);
325 if (!bank
->prot_blocks
)
328 same5_protect_check(bank
);
333 LOG_INFO("SAM MCU: %s (%" PRIu32
"KB Flash, %" PRIu32
"KB RAM)", part
->name
,
334 part
->flash_kb
, part
->ram_kb
);
339 static int same5_wait_and_check_error(struct target
*target
)
342 /* Table 54-40 lists the maximum erase block time as 200 ms.
343 * Include some margin.
345 int timeout_ms
= 200 * 5;
346 int64_t ts_start
= timeval_ms();
350 ret
= target_read_u16(target
,
351 SAMD_NVMCTRL
+ SAME5_NVMCTRL_INTFLAG
, &intflag
);
352 if (ret
!= ERROR_OK
) {
353 LOG_ERROR("SAM: error reading the NVMCTRL_INTFLAG register");
356 if (intflag
& SAME5_NVMCTRL_INTFLAG_DONE
)
359 } while (timeval_ms() - ts_start
< timeout_ms
);
361 if (!(intflag
& SAME5_NVMCTRL_INTFLAG_DONE
)) {
362 LOG_ERROR("SAM: NVM programming timed out");
363 ret
= ERROR_FLASH_OPERATION_FAILED
;
366 if (intflag
& SAME5_NVMCTRL_INTFLAG_ECCSE
)
367 LOG_ERROR("SAM: ECC Single Error");
369 if (intflag
& SAME5_NVMCTRL_INTFLAG_ECCDE
) {
370 LOG_ERROR("SAM: ECC Double Error");
371 ret
= ERROR_FLASH_OPERATION_FAILED
;
374 if (intflag
& SAME5_NVMCTRL_INTFLAG_ADDRE
) {
375 LOG_ERROR("SAM: Addr Error");
376 ret
= ERROR_FLASH_OPERATION_FAILED
;
379 if (intflag
& SAME5_NVMCTRL_INTFLAG_NVME
) {
380 LOG_ERROR("SAM: NVM Error");
381 ret
= ERROR_FLASH_OPERATION_FAILED
;
384 if (intflag
& SAME5_NVMCTRL_INTFLAG_LOCKE
) {
385 LOG_ERROR("SAM: NVM lock error");
386 ret
= ERROR_FLASH_PROTECTED
;
389 if (intflag
& SAME5_NVMCTRL_INTFLAG_PROGE
) {
390 LOG_ERROR("SAM: NVM programming error");
391 ret
= ERROR_FLASH_OPER_UNSUPPORTED
;
394 /* Clear the error conditions by writing a one to them */
395 ret2
= target_write_u16(target
,
396 SAMD_NVMCTRL
+ SAME5_NVMCTRL_INTFLAG
, intflag
);
397 if (ret2
!= ERROR_OK
)
398 LOG_ERROR("Can't clear NVM error conditions");
403 static int same5_issue_nvmctrl_command(struct target
*target
, uint16_t cmd
)
407 if (target
->state
!= TARGET_HALTED
) {
408 LOG_ERROR("Target not halted");
409 return ERROR_TARGET_NOT_HALTED
;
412 /* Issue the NVM command */
413 /* 32-bit write is used to ensure atomic operation on ST-Link */
414 res
= target_write_u32(target
,
415 SAMD_NVMCTRL
+ SAME5_NVMCTRL_CTRLB
, SAMD_NVM_CMD(cmd
));
419 /* Check to see if the NVM command resulted in an error condition. */
420 return same5_wait_and_check_error(target
);
424 * Erases a flash block or page at the given address.
425 * @param target Pointer to the target structure.
426 * @param address The address of the row.
427 * @return On success ERROR_OK, on failure an errorcode.
429 static int same5_erase_block(struct target
*target
, uint32_t address
)
433 /* Set an address contained in the block to be erased */
434 res
= target_write_u32(target
,
435 SAMD_NVMCTRL
+ SAME5_NVMCTRL_ADDR
, address
);
437 /* Issue the Erase Block command. */
439 res
= same5_issue_nvmctrl_command(target
,
440 address
== SAMD_USER_ROW
? SAME5_NVM_CMD_EP
: SAME5_NVM_CMD_EB
);
442 if (res
!= ERROR_OK
) {
443 LOG_ERROR("Failed to erase block containing %08" PRIx32
, address
);
451 static int same5_pre_write_check(struct target
*target
)
456 if (target
->state
!= TARGET_HALTED
) {
457 LOG_ERROR("Target not halted");
458 return ERROR_TARGET_NOT_HALTED
;
461 /* Check if manual write mode is set */
462 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAME5_NVMCTRL_CTRLA
, &nvm_ctrla
);
466 if (nvm_ctrla
& SAME5_NVMCTRL_CTRLA_WMODE_MASK
) {
467 LOG_ERROR("The flash controller must be in manual write mode. Issue 'reset init' and retry.");
476 * Modify the contents of the User Row in Flash. The User Row itself
477 * has a size of one page and contains a combination of "fuses" and
478 * calibration data. Bits which have a value of zero in the mask will
480 * @param target Pointer to the target structure.
481 * @param data Pointer to the value to write.
482 * @param mask Pointer to bitmask, 0 -> value stays untouched.
483 * @param offset Offset in user row where new data will be applied.
484 * @param count Size of buffer and mask in bytes.
485 * @return On success ERROR_OK, on failure an errorcode.
487 static int same5_modify_user_row_masked(struct target
*target
,
488 const uint8_t *data
, const uint8_t *mask
,
489 uint32_t offset
, uint32_t count
)
493 /* Retrieve the MCU's flash page size, in bytes. */
495 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
496 if (res
!= ERROR_OK
) {
497 LOG_ERROR("Couldn't determine Flash page size");
501 /* Make sure the size is sane. */
502 assert(page_size
<= SAMD_PAGE_SIZE_MAX
&&
503 page_size
>= offset
+ count
);
505 uint8_t buf
[SAMD_PAGE_SIZE_MAX
];
506 /* Read the user row (comprising one page) by words. */
507 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
511 /* Modify buffer and check if really changed */
512 bool changed
= false;
514 for (i
= 0; i
< count
; i
++) {
515 uint8_t old_b
= buf
[offset
+i
];
516 uint8_t new_b
= (old_b
& ~mask
[i
]) | (data
[i
] & mask
[i
]);
517 buf
[offset
+i
] = new_b
;
525 res
= same5_pre_write_check(target
);
529 res
= same5_erase_block(target
, SAMD_USER_ROW
);
530 if (res
!= ERROR_OK
) {
531 LOG_ERROR("Couldn't erase user row");
535 /* Write the page buffer back out to the target using Write Quad Word */
536 for (i
= 0; i
< page_size
; i
+= 4 * 4) {
537 res
= target_write_memory(target
, SAMD_USER_ROW
+ i
, 4, 4, buf
+ i
);
541 /* Trigger flash write */
542 res
= same5_issue_nvmctrl_command(target
, SAME5_NVM_CMD_WQW
);
551 * Modifies the user row register to the given value.
552 * @param target Pointer to the target structure.
553 * @param value The value to write.
554 * @param startb The bit-offset by which the given value is shifted.
555 * @param endb The bit-offset of the last bit in value to write.
556 * @return On success ERROR_OK, on failure an errorcode.
558 static int same5_modify_user_row(struct target
*target
, uint32_t value
,
559 uint8_t startb
, uint8_t endb
)
561 uint8_t buf_val
[8] = { 0 };
562 uint8_t buf_mask
[8] = { 0 };
564 assert(startb
<= endb
&& endb
< 64);
565 buf_set_u32(buf_val
, startb
, endb
+ 1 - startb
, value
);
566 buf_set_u32(buf_mask
, startb
, endb
+ 1 - startb
, 0xffffffff);
568 return same5_modify_user_row_masked(target
,
569 buf_val
, buf_mask
, 0, 8);
572 static int same5_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
577 /* We can issue lock/unlock region commands with the target running but
578 * the settings won't persist unless we're able to modify the LOCK regions
579 * and that requires the target to be halted. */
580 if (bank
->target
->state
!= TARGET_HALTED
) {
581 LOG_ERROR("Target not halted");
582 return ERROR_TARGET_NOT_HALTED
;
585 for (unsigned int prot_block
= first
; prot_block
<= last
; prot_block
++) {
586 if (set
!= bank
->prot_blocks
[prot_block
].is_protected
) {
587 /* Load an address that is within this protection block (we use offset 0) */
588 res
= target_write_u32(bank
->target
,
589 SAMD_NVMCTRL
+ SAME5_NVMCTRL_ADDR
,
590 bank
->prot_blocks
[prot_block
].offset
);
594 /* Tell the controller to lock that block */
595 res
= same5_issue_nvmctrl_command(bank
->target
,
596 set
? SAME5_NVM_CMD_LR
: SAME5_NVM_CMD_UR
);
602 /* We've now applied our changes, however they will be undone by the next
603 * reset unless we also apply them to the LOCK bits in the User Page.
604 * A '1' means unlocked and a '0' means locked. */
605 const uint8_t lock
[4] = { 0, 0, 0, 0 };
606 const uint8_t unlock
[4] = { 0xff, 0xff, 0xff, 0xff };
607 uint8_t mask
[4] = { 0, 0, 0, 0 };
609 buf_set_u32(mask
, first
, last
+ 1 - first
, 0xffffffff);
611 res
= same5_modify_user_row_masked(bank
->target
,
612 set
? lock
: unlock
, mask
, 8, 4);
614 LOG_WARNING("SAM: protect settings were not made persistent!");
619 same5_protect_check(bank
);
624 static int same5_erase(struct flash_bank
*bank
, unsigned int first
,
628 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
630 if (bank
->target
->state
!= TARGET_HALTED
) {
631 LOG_ERROR("Target not halted");
633 return ERROR_TARGET_NOT_HALTED
;
637 return ERROR_FLASH_BANK_NOT_PROBED
;
639 /* For each sector to be erased */
640 for (unsigned int s
= first
; s
<= last
; s
++) {
641 res
= same5_erase_block(bank
->target
, bank
->sectors
[s
].offset
);
642 if (res
!= ERROR_OK
) {
643 LOG_ERROR("SAM: failed to erase sector %d at 0x%08" PRIx32
, s
, bank
->sectors
[s
].offset
);
652 static int same5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
653 uint32_t offset
, uint32_t count
)
660 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
663 res
= same5_pre_write_check(bank
->target
);
668 return ERROR_FLASH_BANK_NOT_PROBED
;
670 res
= same5_issue_nvmctrl_command(bank
->target
, SAME5_NVM_CMD_PBC
);
671 if (res
!= ERROR_OK
) {
672 LOG_ERROR("%s: %d", __func__
, __LINE__
);
677 nb
= chip
->page_size
- offset
% chip
->page_size
;
681 address
= bank
->base
+ offset
;
682 pg_offset
= offset
% chip
->page_size
;
684 if (offset
% 4 || (offset
+ nb
) % 4) {
685 /* Either start or end of write is not word aligned */
687 pb
= malloc(chip
->page_size
);
692 /* Set temporary page buffer to 0xff and overwrite the relevant part */
693 memset(pb
, 0xff, chip
->page_size
);
694 memcpy(pb
+ pg_offset
, buffer
, nb
);
696 /* Align start address to a word boundary */
697 address
-= offset
% 4;
698 pg_offset
-= offset
% 4;
699 assert(pg_offset
% 4 == 0);
701 /* Extend length to whole words */
702 nw
= (nb
+ offset
% 4 + 3) / 4;
703 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
705 /* Now we have original data extended by 0xff bytes
706 * to the nearest word boundary on both start and end */
707 res
= target_write_memory(bank
->target
, address
, 4, nw
, pb
+ pg_offset
);
711 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
713 /* Word aligned data, use direct write from buffer */
714 res
= target_write_memory(bank
->target
, address
, 4, nw
, buffer
);
716 if (res
!= ERROR_OK
) {
717 LOG_ERROR("%s: %d", __func__
, __LINE__
);
721 res
= same5_issue_nvmctrl_command(bank
->target
, SAME5_NVM_CMD_WP
);
722 if (res
!= ERROR_OK
) {
723 LOG_ERROR("%s: write failed at address 0x%08" PRIx32
, __func__
, address
);
727 /* We're done with the page contents */
739 FLASH_BANK_COMMAND_HANDLER(same5_flash_bank_command
)
741 if (bank
->base
!= SAMD_FLASH
) {
742 LOG_ERROR("Address " TARGET_ADDR_FMT
" invalid bank address (try "
743 "0x%08x[same5] )", bank
->base
, SAMD_FLASH
);
747 struct samd_info
*chip
;
748 chip
= calloc(1, sizeof(*chip
));
750 LOG_ERROR("No memory for flash bank chip info");
754 chip
->target
= bank
->target
;
755 chip
->probed
= false;
757 bank
->driver_priv
= chip
;
763 COMMAND_HANDLER(same5_handle_chip_erase_command
)
765 struct target
*target
= get_current_target(CMD_CTX
);
769 /* Enable access to the DSU by disabling the write protect bit */
770 target_write_u32(target
, SAME5_PAC
, (1<<16) | (1<<5) | (1<<1));
771 /* intentionally without error checking - not accessible on secured chip */
773 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
774 * perform the erase. */
775 int res
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_CTRL_EXT
, (1<<4));
777 command_print(CMD
, "chip erase started");
779 command_print(CMD
, "write to DSU CTRL failed");
785 COMMAND_HANDLER(same5_handle_userpage_command
)
788 struct target
*target
= get_current_target(CMD_CTX
);
793 command_print(CMD
, "Too much Arguments given.");
794 return ERROR_COMMAND_SYNTAX_ERROR
;
798 uint64_t mask
= NVMUSERROW_SAM_E5_D5_MASK
;
799 uint64_t value
= strtoull(CMD_ARGV
[0], NULL
, 0);
802 uint64_t mask_temp
= strtoull(CMD_ARGV
[1], NULL
, 0);
806 uint8_t val_buf
[8], mask_buf
[8];
807 target_buffer_set_u64(target
, val_buf
, value
);
808 target_buffer_set_u64(target
, mask_buf
, mask
);
810 res
= same5_modify_user_row_masked(target
,
811 val_buf
, mask_buf
, 0, sizeof(val_buf
));
815 int res2
= target_read_memory(target
, SAMD_USER_ROW
, 4, 2, buffer
);
816 if (res2
== ERROR_OK
) {
817 uint64_t value
= target_buffer_get_u64(target
, buffer
);
818 command_print(CMD
, "USER PAGE: 0x%016"PRIX64
, value
);
820 LOG_ERROR("USER PAGE could not be read.");
830 COMMAND_HANDLER(same5_handle_bootloader_command
)
833 struct target
*target
= get_current_target(CMD_CTX
);
838 unsigned long size
= strtoul(CMD_ARGV
[0], NULL
, 0);
839 uint32_t code
= (size
+ 8191) / 8192;
841 command_print(CMD
, "Invalid bootloader size. Please "
842 "see datasheet for a list valid sizes.");
843 return ERROR_COMMAND_SYNTAX_ERROR
;
846 res
= same5_modify_user_row(target
, 15 - code
, 26, 29);
850 int res2
= target_read_u32(target
, SAMD_USER_ROW
, &val
);
851 if (res2
== ERROR_OK
) {
852 uint32_t code
= (val
>> 26) & 0xf; /* grab size code */
853 uint32_t size
= (15 - code
) * 8192;
854 command_print(CMD
, "Bootloader protected in the first %"
855 PRIu32
" bytes", size
);
865 COMMAND_HANDLER(samd_handle_reset_deassert
)
867 struct target
*target
= get_current_target(CMD_CTX
);
869 enum reset_types jtag_reset_config
= jtag_get_reset_config();
873 /* If the target has been unresponsive before, try to re-establish
874 * communication now - CPU is held in reset by DSU, DAP is working */
875 if (!target_was_examined(target
))
876 target_examine_one(target
);
879 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
880 * so we just release reset held by DSU
882 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
884 * After vectreset DSU release is not needed however makes no harm
886 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
887 res
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
889 res
= target_write_u32(target
, DCB_DEMCR
,
890 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
891 /* do not return on error here, releasing DSU reset is more important */
894 /* clear CPU Reset Phase Extension bit */
895 int res2
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_STATUSA
, (1<<1));
896 if (res2
!= ERROR_OK
)
902 static const struct command_registration same5_exec_command_handlers
[] = {
904 .name
= "dsu_reset_deassert",
906 .handler
= samd_handle_reset_deassert
,
907 .mode
= COMMAND_EXEC
,
908 .help
= "Deassert internal reset held by DSU."
911 .name
= "chip-erase",
913 .handler
= same5_handle_chip_erase_command
,
914 .mode
= COMMAND_EXEC
,
915 .help
= "Erase the entire Flash by using the Chip-"
916 "Erase feature in the Device Service Unit (DSU).",
919 .name
= "bootloader",
920 .usage
= "[size_in_bytes]",
921 .handler
= same5_handle_bootloader_command
,
922 .mode
= COMMAND_EXEC
,
923 .help
= "Show or set the bootloader protection size, stored in the User Row. "
924 "Changes are stored immediately but take affect after the MCU is "
929 .usage
= "[value] [mask]",
930 .handler
= same5_handle_userpage_command
,
931 .mode
= COMMAND_EXEC
,
932 .help
= "Show or set the first 64-bit part of user page "
933 "located at address 0x804000. Use the optional mask argument "
934 "to prevent changes at positions where the bitvalue is zero. "
935 "For security reasons the reserved-bits are masked out "
936 "in background and therefore cannot be changed.",
938 COMMAND_REGISTRATION_DONE
941 static const struct command_registration same5_command_handlers
[] = {
945 .help
= "atsame5 flash command group",
947 .chain
= same5_exec_command_handlers
,
949 COMMAND_REGISTRATION_DONE
952 const struct flash_driver atsame5_flash
= {
954 .commands
= same5_command_handlers
,
955 .flash_bank_command
= same5_flash_bank_command
,
956 .erase
= same5_erase
,
957 .protect
= same5_protect
,
958 .write
= same5_write
,
959 .read
= default_flash_read
,
960 .probe
= same5_probe
,
961 .auto_probe
= same5_probe
,
962 .erase_check
= default_flash_blank_check
,
963 .protect_check
= same5_protect_check
,
964 .free_driver_priv
= default_flash_free_driver_priv
,
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