1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include "helper/binarybuffer.h"
26 #include <target/cortex_m.h>
28 #define SAMD_NUM_SECTORS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
40 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
41 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
42 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
43 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
44 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
45 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
46 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
48 #define SAMD_CMDEX_KEY 0xA5UL
49 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
51 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
52 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
53 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
54 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
55 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
56 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
57 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
58 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
59 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
60 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
61 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
62 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
65 #define SAMD_NVM_CTRLB_MANW 0x80
67 /* Known identifiers */
68 #define SAMD_PROCESSOR_M0 0x01
69 #define SAMD_FAMILY_D 0x00
70 #define SAMD_FAMILY_L 0x01
71 #define SAMD_FAMILY_C 0x02
72 #define SAMD_SERIES_20 0x00
73 #define SAMD_SERIES_21 0x01
74 #define SAMD_SERIES_22 0x02
75 #define SAMD_SERIES_10 0x02
76 #define SAMD_SERIES_11 0x03
77 #define SAMD_SERIES_09 0x04
79 /* Device ID macros */
80 #define SAMD_GET_PROCESSOR(id) (id >> 28)
81 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
82 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
83 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
92 /* Known SAMD09 parts. DID reset values missing in RM, see
93 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
94 static const struct samd_part samd09_parts
[] = {
95 { 0x0, "SAMD09D14A", 16, 4 },
96 { 0x7, "SAMD09C13A", 8, 4 },
99 /* Known SAMD10 parts */
100 static const struct samd_part samd10_parts
[] = {
101 { 0x0, "SAMD10D14AMU", 16, 4 },
102 { 0x1, "SAMD10D13AMU", 8, 4 },
103 { 0x2, "SAMD10D12AMU", 4, 4 },
104 { 0x3, "SAMD10D14ASU", 16, 4 },
105 { 0x4, "SAMD10D13ASU", 8, 4 },
106 { 0x5, "SAMD10D12ASU", 4, 4 },
107 { 0x6, "SAMD10C14A", 16, 4 },
108 { 0x7, "SAMD10C13A", 8, 4 },
109 { 0x8, "SAMD10C12A", 4, 4 },
112 /* Known SAMD11 parts */
113 static const struct samd_part samd11_parts
[] = {
114 { 0x0, "SAMD11D14AMU", 16, 4 },
115 { 0x1, "SAMD11D13AMU", 8, 4 },
116 { 0x2, "SAMD11D12AMU", 4, 4 },
117 { 0x3, "SAMD11D14ASU", 16, 4 },
118 { 0x4, "SAMD11D13ASU", 8, 4 },
119 { 0x5, "SAMD11D12ASU", 4, 4 },
120 { 0x6, "SAMD11C14A", 16, 4 },
121 { 0x7, "SAMD11C13A", 8, 4 },
122 { 0x8, "SAMD11C12A", 4, 4 },
125 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
126 static const struct samd_part samd20_parts
[] = {
127 { 0x0, "SAMD20J18A", 256, 32 },
128 { 0x1, "SAMD20J17A", 128, 16 },
129 { 0x2, "SAMD20J16A", 64, 8 },
130 { 0x3, "SAMD20J15A", 32, 4 },
131 { 0x4, "SAMD20J14A", 16, 2 },
132 { 0x5, "SAMD20G18A", 256, 32 },
133 { 0x6, "SAMD20G17A", 128, 16 },
134 { 0x7, "SAMD20G16A", 64, 8 },
135 { 0x8, "SAMD20G15A", 32, 4 },
136 { 0x9, "SAMD20G14A", 16, 2 },
137 { 0xA, "SAMD20E18A", 256, 32 },
138 { 0xB, "SAMD20E17A", 128, 16 },
139 { 0xC, "SAMD20E16A", 64, 8 },
140 { 0xD, "SAMD20E15A", 32, 4 },
141 { 0xE, "SAMD20E14A", 16, 2 },
144 /* Known SAMD21 parts. */
145 static const struct samd_part samd21_parts
[] = {
146 { 0x0, "SAMD21J18A", 256, 32 },
147 { 0x1, "SAMD21J17A", 128, 16 },
148 { 0x2, "SAMD21J16A", 64, 8 },
149 { 0x3, "SAMD21J15A", 32, 4 },
150 { 0x4, "SAMD21J14A", 16, 2 },
151 { 0x5, "SAMD21G18A", 256, 32 },
152 { 0x6, "SAMD21G17A", 128, 16 },
153 { 0x7, "SAMD21G16A", 64, 8 },
154 { 0x8, "SAMD21G15A", 32, 4 },
155 { 0x9, "SAMD21G14A", 16, 2 },
156 { 0xA, "SAMD21E18A", 256, 32 },
157 { 0xB, "SAMD21E17A", 128, 16 },
158 { 0xC, "SAMD21E16A", 64, 8 },
159 { 0xD, "SAMD21E15A", 32, 4 },
160 { 0xE, "SAMD21E14A", 16, 2 },
161 /* Below are B Variants (Table 3-7 from rev I of datasheet) */
162 { 0x20, "SAMD21J16B", 64, 8 },
163 { 0x21, "SAMD21J15B", 32, 4 },
164 { 0x23, "SAMD21G16B", 64, 8 },
165 { 0x24, "SAMD21G15B", 32, 4 },
166 { 0x26, "SAMD21E16B", 64, 8 },
167 { 0x27, "SAMD21E15B", 32, 4 },
170 /* Known SAMR21 parts. */
171 static const struct samd_part samr21_parts
[] = {
172 { 0x19, "SAMR21G18A", 256, 32 },
173 { 0x1A, "SAMR21G17A", 128, 32 },
174 { 0x1B, "SAMR21G16A", 64, 32 },
175 { 0x1C, "SAMR21E18A", 256, 32 },
176 { 0x1D, "SAMR21E17A", 128, 32 },
177 { 0x1E, "SAMR21E16A", 64, 32 },
180 /* Known SAML21 parts. */
181 static const struct samd_part saml21_parts
[] = {
182 { 0x00, "SAML21J18A", 256, 32 },
183 { 0x01, "SAML21J17A", 128, 16 },
184 { 0x02, "SAML21J16A", 64, 8 },
185 { 0x05, "SAML21G18A", 256, 32 },
186 { 0x06, "SAML21G17A", 128, 16 },
187 { 0x07, "SAML21G16A", 64, 8 },
188 { 0x0A, "SAML21E18A", 256, 32 },
189 { 0x0B, "SAML21E17A", 128, 16 },
190 { 0x0C, "SAML21E16A", 64, 8 },
191 { 0x0D, "SAML21E15A", 32, 4 },
192 { 0x0F, "SAML21J18B", 256, 32 },
193 { 0x10, "SAML21J17B", 128, 16 },
194 { 0x11, "SAML21J16B", 64, 8 },
195 { 0x14, "SAML21G18B", 256, 32 },
196 { 0x15, "SAML21G17B", 128, 16 },
197 { 0x16, "SAML21G16B", 64, 8 },
198 { 0x19, "SAML21E18B", 256, 32 },
199 { 0x1A, "SAML21E17B", 128, 16 },
200 { 0x1B, "SAML21E16B", 64, 8 },
201 { 0x1C, "SAML21E15B", 32, 4 },
204 /* Known SAML22 parts. */
205 static const struct samd_part saml22_parts
[] = {
206 { 0x00, "SAML22N18A", 256, 32 },
207 { 0x01, "SAML22N17A", 128, 16 },
208 { 0x02, "SAML22N16A", 64, 8 },
209 { 0x05, "SAML22J18A", 256, 32 },
210 { 0x06, "SAML22J17A", 128, 16 },
211 { 0x07, "SAML22J16A", 64, 8 },
212 { 0x0A, "SAML22G18A", 256, 32 },
213 { 0x0B, "SAML22G17A", 128, 16 },
214 { 0x0C, "SAML22G16A", 64, 8 },
217 /* Known SAMC20 parts. */
218 static const struct samd_part samc20_parts
[] = {
219 { 0x00, "SAMC20J18A", 256, 32 },
220 { 0x01, "SAMC20J17A", 128, 16 },
221 { 0x02, "SAMC20J16A", 64, 8 },
222 { 0x03, "SAMC20J15A", 32, 4 },
223 { 0x05, "SAMC20G18A", 256, 32 },
224 { 0x06, "SAMC20G17A", 128, 16 },
225 { 0x07, "SAMC20G16A", 64, 8 },
226 { 0x08, "SAMC20G15A", 32, 4 },
227 { 0x0A, "SAMC20E18A", 256, 32 },
228 { 0x0B, "SAMC20E17A", 128, 16 },
229 { 0x0C, "SAMC20E16A", 64, 8 },
230 { 0x0D, "SAMC20E15A", 32, 4 },
233 /* Known SAMC21 parts. */
234 static const struct samd_part samc21_parts
[] = {
235 { 0x00, "SAMC21J18A", 256, 32 },
236 { 0x01, "SAMC21J17A", 128, 16 },
237 { 0x02, "SAMC21J16A", 64, 8 },
238 { 0x03, "SAMC21J15A", 32, 4 },
239 { 0x05, "SAMC21G18A", 256, 32 },
240 { 0x06, "SAMC21G17A", 128, 16 },
241 { 0x07, "SAMC21G16A", 64, 8 },
242 { 0x08, "SAMC21G15A", 32, 4 },
243 { 0x0A, "SAMC21E18A", 256, 32 },
244 { 0x0B, "SAMC21E17A", 128, 16 },
245 { 0x0C, "SAMC21E16A", 64, 8 },
246 { 0x0D, "SAMC21E15A", 32, 4 },
249 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
250 * processor ID, family ID, and series ID are used to determine which exact
251 * family this is and then we can use the corresponding table. */
256 const struct samd_part
*parts
;
260 /* Known SAMD families */
261 static const struct samd_family samd_families
[] = {
262 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_20
,
263 samd20_parts
, ARRAY_SIZE(samd20_parts
) },
264 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
265 samd21_parts
, ARRAY_SIZE(samd21_parts
) },
266 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
267 samr21_parts
, ARRAY_SIZE(samr21_parts
) },
268 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_09
,
269 samd09_parts
, ARRAY_SIZE(samd09_parts
) },
270 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_10
,
271 samd10_parts
, ARRAY_SIZE(samd10_parts
) },
272 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_11
,
273 samd11_parts
, ARRAY_SIZE(samd11_parts
) },
274 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_21
,
275 saml21_parts
, ARRAY_SIZE(saml21_parts
) },
276 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_22
,
277 saml22_parts
, ARRAY_SIZE(saml22_parts
) },
278 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_20
,
279 samc20_parts
, ARRAY_SIZE(samc20_parts
) },
280 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_21
,
281 samc21_parts
, ARRAY_SIZE(samc21_parts
) },
290 struct target
*target
;
291 struct samd_info
*next
;
294 static struct samd_info
*samd_chips
;
298 static const struct samd_part
*samd_find_part(uint32_t id
)
300 uint8_t processor
= SAMD_GET_PROCESSOR(id
);
301 uint8_t family
= SAMD_GET_FAMILY(id
);
302 uint8_t series
= SAMD_GET_SERIES(id
);
303 uint8_t devsel
= SAMD_GET_DEVSEL(id
);
305 for (unsigned i
= 0; i
< ARRAY_SIZE(samd_families
); i
++) {
306 if (samd_families
[i
].processor
== processor
&&
307 samd_families
[i
].series
== series
&&
308 samd_families
[i
].family
== family
) {
309 for (unsigned j
= 0; j
< samd_families
[i
].num_parts
; j
++) {
310 if (samd_families
[i
].parts
[j
].id
== devsel
)
311 return &samd_families
[i
].parts
[j
];
319 static int samd_protect_check(struct flash_bank
*bank
)
324 res
= target_read_u16(bank
->target
,
325 SAMD_NVMCTRL
+ SAMD_NVMCTRL_LOCK
, &lock
);
329 /* Lock bits are active-low */
330 for (int i
= 0; i
< bank
->num_sectors
; i
++)
331 bank
->sectors
[i
].is_protected
= !(lock
& (1<<i
));
336 static int samd_get_flash_page_info(struct target
*target
,
337 uint32_t *sizep
, int *nump
)
342 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_PARAM
, ¶m
);
343 if (res
== ERROR_OK
) {
344 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
345 * so 0 is 8KB and 7 is 1024KB. */
347 *sizep
= (8 << ((param
>> 16) & 0x7));
348 /* The NVMP field (bits 15:0) indicates the total number of pages */
350 *nump
= param
& 0xFFFF;
352 LOG_ERROR("Couldn't read NVM Parameters register");
358 static int samd_probe(struct flash_bank
*bank
)
362 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
363 const struct samd_part
*part
;
368 res
= target_read_u32(bank
->target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
369 if (res
!= ERROR_OK
) {
370 LOG_ERROR("Couldn't read Device ID register");
374 part
= samd_find_part(id
);
376 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32
, id
);
380 bank
->size
= part
->flash_kb
* 1024;
382 chip
->sector_size
= bank
->size
/ SAMD_NUM_SECTORS
;
384 res
= samd_get_flash_page_info(bank
->target
, &chip
->page_size
,
386 if (res
!= ERROR_OK
) {
387 LOG_ERROR("Couldn't determine Flash page size");
391 /* Sanity check: the total flash size in the DSU should match the page size
392 * multiplied by the number of pages. */
393 if (bank
->size
!= chip
->num_pages
* chip
->page_size
) {
394 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
395 "Identified %" PRIu32
"KB Flash but NVMCTRL reports %u %" PRIu32
"B pages",
396 part
->flash_kb
, chip
->num_pages
, chip
->page_size
);
399 /* Allocate the sector table */
400 bank
->num_sectors
= SAMD_NUM_SECTORS
;
401 bank
->sectors
= calloc(bank
->num_sectors
, sizeof((bank
->sectors
)[0]));
405 /* Fill out the sector information: all SAMD sectors are the same size and
406 * there is always a fixed number of them. */
407 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
408 bank
->sectors
[i
].size
= chip
->sector_size
;
409 bank
->sectors
[i
].offset
= i
* chip
->sector_size
;
410 /* mark as unknown */
411 bank
->sectors
[i
].is_erased
= -1;
412 bank
->sectors
[i
].is_protected
= -1;
415 samd_protect_check(bank
);
420 LOG_INFO("SAMD MCU: %s (%" PRIu32
"KB Flash, %" PRIu32
"KB RAM)", part
->name
,
421 part
->flash_kb
, part
->ram_kb
);
426 static int samd_check_error(struct target
*target
)
431 ret
= target_read_u16(target
,
432 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, &status
);
433 if (ret
!= ERROR_OK
) {
434 LOG_ERROR("Can't read NVM status");
438 if ((status
& 0x001C) == 0)
441 if (status
& (1 << 4)) { /* NVME */
442 LOG_ERROR("SAMD: NVM Error");
443 ret
= ERROR_FLASH_OPERATION_FAILED
;
446 if (status
& (1 << 3)) { /* LOCKE */
447 LOG_ERROR("SAMD: NVM lock error");
448 ret
= ERROR_FLASH_PROTECTED
;
451 if (status
& (1 << 2)) { /* PROGE */
452 LOG_ERROR("SAMD: NVM programming error");
453 ret
= ERROR_FLASH_OPER_UNSUPPORTED
;
456 /* Clear the error conditions by writing a one to them */
457 ret2
= target_write_u16(target
,
458 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, status
);
459 if (ret2
!= ERROR_OK
)
460 LOG_ERROR("Can't clear NVM error conditions");
465 static int samd_issue_nvmctrl_command(struct target
*target
, uint16_t cmd
)
469 if (target
->state
!= TARGET_HALTED
) {
470 LOG_ERROR("Target not halted");
471 return ERROR_TARGET_NOT_HALTED
;
474 /* Issue the NVM command */
475 res
= target_write_u16(target
,
476 SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLA
, SAMD_NVM_CMD(cmd
));
480 /* Check to see if the NVM command resulted in an error condition. */
481 return samd_check_error(target
);
484 static int samd_erase_row(struct target
*target
, uint32_t address
)
488 /* Set an address contained in the row to be erased */
489 res
= target_write_u32(target
,
490 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
, address
>> 1);
492 /* Issue the Erase Row command to erase that row. */
494 res
= samd_issue_nvmctrl_command(target
,
495 address
== SAMD_USER_ROW
? SAMD_NVM_CMD_EAR
: SAMD_NVM_CMD_ER
);
497 if (res
!= ERROR_OK
) {
498 LOG_ERROR("Failed to erase row containing %08" PRIx32
, address
);
505 static bool is_user_row_reserved_bit(uint8_t bit
)
507 /* See Table 9-3 in the SAMD20 datasheet for more information. */
512 /* Voltage regulator internal configuration with default value of 0x70,
513 * may not be changed. */
515 /* 41 is voltage regulator internal configuration and must not be
516 * changed. 42 through 47 are reserved. */
526 /* Modify the contents of the User Row in Flash. These are described in Table
527 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
528 * and contains a combination of "fuses" and calibration data in bits 24:17.
529 * We therefore try not to erase the row's contents unless we absolutely have
530 * to and we don't permit modifying reserved bits. */
531 static int samd_modify_user_row(struct target
*target
, uint32_t value
,
532 uint8_t startb
, uint8_t endb
)
536 bool manual_wp
= true;
538 if (is_user_row_reserved_bit(startb
) || is_user_row_reserved_bit(endb
)) {
539 LOG_ERROR("Can't modify bits in the requested range");
543 /* Check if we need to do manual page write commands */
544 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
546 manual_wp
= (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
) != 0;
548 /* Retrieve the MCU's page size, in bytes. This is also the size of the
549 * entire User Row. */
551 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
552 if (res
!= ERROR_OK
) {
553 LOG_ERROR("Couldn't determine Flash page size");
557 /* Make sure the size is sane before we allocate. */
558 assert(page_size
> 0 && page_size
<= SAMD_PAGE_SIZE_MAX
);
560 /* Make sure we're within the single page that comprises the User Row. */
561 if (startb
>= (page_size
* 8) || endb
>= (page_size
* 8)) {
562 LOG_ERROR("Can't modify bits outside the User Row page range");
566 uint8_t *buf
= malloc(page_size
);
570 /* Read the user row (comprising one page) by words. */
571 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
575 /* We will need to erase before writing if the new value needs a '1' in any
576 * position for which the current value had a '0'. Otherwise we can avoid
578 uint32_t cur
= buf_get_u32(buf
, startb
, endb
- startb
+ 1);
579 if ((~cur
) & value
) {
580 res
= samd_erase_row(target
, SAMD_USER_ROW
);
581 if (res
!= ERROR_OK
) {
582 LOG_ERROR("Couldn't erase user row");
588 buf_set_u32(buf
, startb
, endb
- startb
+ 1, value
);
590 /* Write the page buffer back out to the target. */
591 res
= target_write_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
596 /* Trigger flash write */
597 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_WAP
);
599 res
= samd_check_error(target
);
608 static int samd_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
610 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
612 /* We can issue lock/unlock region commands with the target running but
613 * the settings won't persist unless we're able to modify the LOCK regions
614 * and that requires the target to be halted. */
615 if (bank
->target
->state
!= TARGET_HALTED
) {
616 LOG_ERROR("Target not halted");
617 return ERROR_TARGET_NOT_HALTED
;
622 for (int s
= first
; s
<= last
; s
++) {
623 if (set
!= bank
->sectors
[s
].is_protected
) {
624 /* Load an address that is within this sector (we use offset 0) */
625 res
= target_write_u32(bank
->target
,
626 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
,
627 ((s
* chip
->sector_size
) >> 1));
631 /* Tell the controller to lock that sector */
632 res
= samd_issue_nvmctrl_command(bank
->target
,
633 set
? SAMD_NVM_CMD_LR
: SAMD_NVM_CMD_UR
);
639 /* We've now applied our changes, however they will be undone by the next
640 * reset unless we also apply them to the LOCK bits in the User Page. The
641 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
642 * corresponding to Sector 15. A '1' means unlocked and a '0' means
643 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
645 res
= samd_modify_user_row(bank
->target
, set
? 0x0000 : 0xFFFF,
646 48 + first
, 48 + last
);
648 LOG_WARNING("SAMD: protect settings were not made persistent!");
653 samd_protect_check(bank
);
658 static int samd_erase(struct flash_bank
*bank
, int first
, int last
)
662 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
664 if (bank
->target
->state
!= TARGET_HALTED
) {
665 LOG_ERROR("Target not halted");
667 return ERROR_TARGET_NOT_HALTED
;
671 if (samd_probe(bank
) != ERROR_OK
)
672 return ERROR_FLASH_BANK_NOT_PROBED
;
675 /* The SAMD NVM has row erase granularity. There are four pages in a row
676 * and the number of rows in a sector depends on the sector size, which in
677 * turn depends on the Flash capacity as there is a fixed number of
679 rows_in_sector
= chip
->sector_size
/ (chip
->page_size
* 4);
681 /* For each sector to be erased */
682 for (int s
= first
; s
<= last
; s
++) {
683 if (bank
->sectors
[s
].is_protected
) {
684 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s
);
685 return ERROR_FLASH_OPERATION_FAILED
;
688 /* For each row in that sector */
689 for (int r
= s
* rows_in_sector
; r
< (s
+ 1) * rows_in_sector
; r
++) {
690 res
= samd_erase_row(bank
->target
, r
* chip
->page_size
* 4);
691 if (res
!= ERROR_OK
) {
692 LOG_ERROR("SAMD: failed to erase sector %d", s
);
702 static int samd_write(struct flash_bank
*bank
, const uint8_t *buffer
,
703 uint32_t offset
, uint32_t count
)
711 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
715 if (bank
->target
->state
!= TARGET_HALTED
) {
716 LOG_ERROR("Target not halted");
717 return ERROR_TARGET_NOT_HALTED
;
721 if (samd_probe(bank
) != ERROR_OK
)
722 return ERROR_FLASH_BANK_NOT_PROBED
;
725 /* Check if we need to do manual page write commands */
726 res
= target_read_u32(bank
->target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
731 if (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
)
736 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_PBC
);
737 if (res
!= ERROR_OK
) {
738 LOG_ERROR("%s: %d", __func__
, __LINE__
);
743 nb
= chip
->page_size
- offset
% chip
->page_size
;
747 address
= bank
->base
+ offset
;
748 pg_offset
= offset
% chip
->page_size
;
750 if (offset
% 4 || (offset
+ nb
) % 4) {
751 /* Either start or end of write is not word aligned */
753 pb
= malloc(chip
->page_size
);
758 /* Set temporary page buffer to 0xff and overwrite the relevant part */
759 memset(pb
, 0xff, chip
->page_size
);
760 memcpy(pb
+ pg_offset
, buffer
, nb
);
762 /* Align start address to a word boundary */
763 address
-= offset
% 4;
764 pg_offset
-= offset
% 4;
765 assert(pg_offset
% 4 == 0);
767 /* Extend length to whole words */
768 nw
= (nb
+ offset
% 4 + 3) / 4;
769 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
771 /* Now we have original data extended by 0xff bytes
772 * to the nearest word boundary on both start and end */
773 res
= target_write_memory(bank
->target
, address
, 4, nw
, pb
+ pg_offset
);
777 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
779 /* Word aligned data, use direct write from buffer */
780 res
= target_write_memory(bank
->target
, address
, 4, nw
, buffer
);
782 if (res
!= ERROR_OK
) {
783 LOG_ERROR("%s: %d", __func__
, __LINE__
);
787 /* Devices with errata 13134 have automatic page write enabled by default
788 * For other devices issue a write page CMD to the NVM
789 * If the page has not been written up to the last word
790 * then issue CMD_WP always */
791 if (manual_wp
|| pg_offset
+ 4 * nw
< chip
->page_size
) {
792 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_WP
);
794 /* Access through AHB is stalled while flash is being programmed */
797 res
= samd_check_error(bank
->target
);
800 if (res
!= ERROR_OK
) {
801 LOG_ERROR("%s: write failed at address 0x%08" PRIx32
, __func__
, address
);
805 /* We're done with the page contents */
818 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command
)
820 struct samd_info
*chip
= samd_chips
;
823 if (chip
->target
== bank
->target
)
829 /* Create a new chip */
830 chip
= calloc(1, sizeof(*chip
));
834 chip
->target
= bank
->target
;
835 chip
->probed
= false;
837 bank
->driver_priv
= chip
;
839 /* Insert it into the chips list (at head) */
840 chip
->next
= samd_chips
;
844 if (bank
->base
!= SAMD_FLASH
) {
845 LOG_ERROR("Address 0x%08" PRIx32
" invalid bank address (try 0x%08" PRIx32
846 "[at91samd series] )",
847 bank
->base
, SAMD_FLASH
);
854 COMMAND_HANDLER(samd_handle_info_command
)
859 COMMAND_HANDLER(samd_handle_chip_erase_command
)
861 struct target
*target
= get_current_target(CMD_CTX
);
864 /* Enable access to the DSU by disabling the write protect bit */
865 target_write_u32(target
, SAMD_PAC1
, (1<<1));
866 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
867 * perform the erase. */
868 target_write_u8(target
, SAMD_DSU
, (1<<4));
870 command_print(CMD_CTX
, "chip erased");
876 COMMAND_HANDLER(samd_handle_set_security_command
)
879 struct target
*target
= get_current_target(CMD_CTX
);
881 if (CMD_ARGC
< 1 || (CMD_ARGC
>= 1 && (strcmp(CMD_ARGV
[0], "enable")))) {
882 command_print(CMD_CTX
, "supply the \"enable\" argument to proceed.");
883 return ERROR_COMMAND_SYNTAX_ERROR
;
887 if (target
->state
!= TARGET_HALTED
) {
888 LOG_ERROR("Target not halted");
889 return ERROR_TARGET_NOT_HALTED
;
892 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_SSB
);
894 /* Check (and clear) error conditions */
896 command_print(CMD_CTX
, "chip secured on next power-cycle");
898 command_print(CMD_CTX
, "failed to secure chip");
904 COMMAND_HANDLER(samd_handle_eeprom_command
)
907 struct target
*target
= get_current_target(CMD_CTX
);
910 if (target
->state
!= TARGET_HALTED
) {
911 LOG_ERROR("Target not halted");
912 return ERROR_TARGET_NOT_HALTED
;
916 int val
= atoi(CMD_ARGV
[0]);
922 /* Try to match size in bytes with corresponding size code */
923 for (code
= 0; code
<= 6; code
++) {
924 if (val
== (2 << (13 - code
)))
929 command_print(CMD_CTX
, "Invalid EEPROM size. Please see "
930 "datasheet for a list valid sizes.");
931 return ERROR_COMMAND_SYNTAX_ERROR
;
935 res
= samd_modify_user_row(target
, code
, 4, 6);
938 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
939 if (res
== ERROR_OK
) {
940 uint32_t size
= ((val
>> 4) & 0x7); /* grab size code */
943 command_print(CMD_CTX
, "EEPROM is disabled");
945 /* Otherwise, 6 is 256B, 0 is 16KB */
946 command_print(CMD_CTX
, "EEPROM size is %u bytes",
956 COMMAND_HANDLER(samd_handle_bootloader_command
)
959 struct target
*target
= get_current_target(CMD_CTX
);
962 if (target
->state
!= TARGET_HALTED
) {
963 LOG_ERROR("Target not halted");
964 return ERROR_TARGET_NOT_HALTED
;
967 /* Retrieve the MCU's page size, in bytes. */
969 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
970 if (res
!= ERROR_OK
) {
971 LOG_ERROR("Couldn't determine Flash page size");
976 int val
= atoi(CMD_ARGV
[0]);
982 /* Try to match size in bytes with corresponding size code */
983 for (code
= 0; code
<= 6; code
++) {
984 if ((unsigned int)val
== (2UL << (8UL - code
)) * page_size
)
989 command_print(CMD_CTX
, "Invalid bootloader size. Please "
990 "see datasheet for a list valid sizes.");
991 return ERROR_COMMAND_SYNTAX_ERROR
;
996 res
= samd_modify_user_row(target
, code
, 0, 2);
999 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
1000 if (res
== ERROR_OK
) {
1001 uint32_t size
= (val
& 0x7); /* grab size code */
1007 nb
= (2 << (8 - size
)) * page_size
;
1009 /* There are 4 pages per row */
1010 command_print(CMD_CTX
, "Bootloader size is %" PRIu32
" bytes (%" PRIu32
" rows)",
1011 nb
, (uint32_t)(nb
/ (page_size
* 4)));
1021 COMMAND_HANDLER(samd_handle_reset_deassert
)
1023 struct target
*target
= get_current_target(CMD_CTX
);
1024 int retval
= ERROR_OK
;
1025 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1027 /* If the target has been unresponsive before, try to re-establish
1028 * communication now - CPU is held in reset by DSU, DAP is working */
1029 if (!target_was_examined(target
))
1030 target_examine_one(target
);
1031 target_poll(target
);
1033 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1034 * so we just release reset held by DSU
1036 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1038 * After vectreset DSU release is not needed however makes no harm
1040 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
1041 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1042 if (retval
== ERROR_OK
)
1043 retval
= target_write_u32(target
, DCB_DEMCR
,
1044 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1045 /* do not return on error here, releasing DSU reset is more important */
1048 /* clear CPU Reset Phase Extension bit */
1049 int retval2
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_STATUSA
, (1<<1));
1050 if (retval2
!= ERROR_OK
)
1056 static const struct command_registration at91samd_exec_command_handlers
[] = {
1058 .name
= "dsu_reset_deassert",
1059 .handler
= samd_handle_reset_deassert
,
1060 .mode
= COMMAND_EXEC
,
1061 .help
= "deasert internal reset held by DSU"
1065 .handler
= samd_handle_info_command
,
1066 .mode
= COMMAND_EXEC
,
1067 .help
= "Print information about the current at91samd chip"
1068 "and its flash configuration.",
1071 .name
= "chip-erase",
1072 .handler
= samd_handle_chip_erase_command
,
1073 .mode
= COMMAND_EXEC
,
1074 .help
= "Erase the entire Flash by using the Chip"
1075 "Erase feature in the Device Service Unit (DSU).",
1078 .name
= "set-security",
1079 .handler
= samd_handle_set_security_command
,
1080 .mode
= COMMAND_EXEC
,
1081 .help
= "Secure the chip's Flash by setting the Security Bit."
1082 "This makes it impossible to read the Flash contents."
1083 "The only way to undo this is to issue the chip-erase"
1088 .usage
= "[size_in_bytes]",
1089 .handler
= samd_handle_eeprom_command
,
1090 .mode
= COMMAND_EXEC
,
1091 .help
= "Show or set the EEPROM size setting, stored in the User Row."
1092 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1093 "Changes are stored immediately but take affect after the MCU is"
1097 .name
= "bootloader",
1098 .usage
= "[size_in_bytes]",
1099 .handler
= samd_handle_bootloader_command
,
1100 .mode
= COMMAND_EXEC
,
1101 .help
= "Show or set the bootloader size, stored in the User Row."
1102 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1103 "Changes are stored immediately but take affect after the MCU is"
1106 COMMAND_REGISTRATION_DONE
1109 static const struct command_registration at91samd_command_handlers
[] = {
1112 .mode
= COMMAND_ANY
,
1113 .help
= "at91samd flash command group",
1115 .chain
= at91samd_exec_command_handlers
,
1117 COMMAND_REGISTRATION_DONE
1120 struct flash_driver at91samd_flash
= {
1122 .commands
= at91samd_command_handlers
,
1123 .flash_bank_command
= samd_flash_bank_command
,
1124 .erase
= samd_erase
,
1125 .protect
= samd_protect
,
1126 .write
= samd_write
,
1127 .read
= default_flash_read
,
1128 .probe
= samd_probe
,
1129 .auto_probe
= samd_probe
,
1130 .erase_check
= default_flash_blank_check
,
1131 .protect_check
= samd_protect_check
,
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