1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ****************************************************************************/
23 /***************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
28 * [<chip_type> <banks>
29 * <sectors_per_bank> <pages_per_sector>
30 * <page_size> <num_nvmbits>
33 * <ext_freq_khz> - MUST be used if clock is from external source,
34 * CAN be used if main oscillator frequency is known (recommended)
36 * ==== RECOMMENDED (covers clock speed) ============
37 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
38 * (if auto-detect fails; provides clock spec)
39 * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
40 * (auto-detect everything except the clock)
41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
42 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
43 * (if auto-detect fails)
44 * flash bank at91sam7 0 0 0 0 $_TARGETNAME
45 * (old style, auto-detect everything)
46 ****************************************************************************/
53 #include <helper/binarybuffer.h>
55 /* AT91SAM7 control registers */
56 #define DBGU_CIDR 0xFFFFF240
57 #define CKGR_MCFR 0xFFFFFC24
58 #define CKGR_MOR 0xFFFFFC20
59 #define CKGR_MCFR_MAINRDY 0x10000
60 #define CKGR_PLLR 0xFFFFFC2c
61 #define CKGR_PLLR_DIV 0xff
62 #define CKGR_PLLR_MUL 0x07ff0000
63 #define PMC_MCKR 0xFFFFFC30
64 #define PMC_MCKR_CSS 0x03
65 #define PMC_MCKR_PRES 0x1c
67 /* Flash Controller Commands */
77 /* MC_FSR bit definitions */
81 /* AT91SAM7 constants */
84 /* Flash timing modes */
85 #define FMR_TIMING_NONE 0
86 #define FMR_TIMING_NVBITS 1
87 #define FMR_TIMING_FLASH 2
89 /* Flash size constants */
90 #define FLASH_SIZE_8KB 1
91 #define FLASH_SIZE_16KB 2
92 #define FLASH_SIZE_32KB 3
93 #define FLASH_SIZE_64KB 5
94 #define FLASH_SIZE_128KB 7
95 #define FLASH_SIZE_256KB 9
96 #define FLASH_SIZE_512KB 10
97 #define FLASH_SIZE_1024KB 12
98 #define FLASH_SIZE_2048KB 14
100 static int at91sam7_protect_check(struct flash_bank
*bank
);
101 static int at91sam7_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
,
104 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
);
105 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
);
106 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
);
107 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
);
109 static const uint32_t MC_FMR
[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
110 static const uint32_t MC_FCR
[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
111 static const uint32_t MC_FSR
[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
113 static const char *EPROC
[8] = {
114 "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
117 struct at91sam7_flash_bank
{
118 /* chip id register */
121 uint16_t cidr_nvptyp
;
123 uint16_t cidr_sramsiz
;
124 uint16_t cidr_nvpsiz
;
125 uint16_t cidr_nvpsiz2
;
127 uint16_t cidr_version
;
128 const char *target_name
;
130 /* flash auto-detection */
131 uint8_t flash_autodetection
;
134 uint16_t pages_per_sector
;
136 uint16_t pages_in_lockregion
;
139 uint16_t num_lockbits_on
;
141 uint16_t num_nvmbits
;
142 uint16_t num_nvmbits_on
;
147 * 1: fmcn for nvbits (1uS)
148 * 2: fmcn for flash (1.5uS) */
151 /* main clock status */
155 /* external clock frequency */
161 static long SRAMSIZ
[16] = {
181 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
)
184 target_read_u32(target
, MC_FSR
[bank_number
], &fsr
);
189 /* Read clock configuration and set at91sam7_info->mck_freq */
190 static void at91sam7_read_clock_info(struct flash_bank
*bank
)
192 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
193 struct target
*target
= bank
->target
;
194 uint32_t mckr
, mcfr
, pllr
, mor
;
195 unsigned long tmp
= 0, mainfreq
;
197 /* Read Clock Generator Main Oscillator Register */
198 target_read_u32(target
, CKGR_MOR
, &mor
);
199 /* Read Clock Generator Main Clock Frequency Register */
200 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
201 /* Read Master Clock Register*/
202 target_read_u32(target
, PMC_MCKR
, &mckr
);
203 /* Read Clock Generator PLL Register */
204 target_read_u32(target
, CKGR_PLLR
, &pllr
);
206 at91sam7_info
->mck_valid
= 0;
207 at91sam7_info
->mck_freq
= 0;
208 switch (mckr
& PMC_MCKR_CSS
) {
209 case 0: /* Slow Clock */
210 at91sam7_info
->mck_valid
= 1;
214 case 1: /* Main Clock */
215 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
216 (at91sam7_info
->ext_freq
== 0)) {
217 at91sam7_info
->mck_valid
= 1;
218 tmp
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
219 } else if (at91sam7_info
->ext_freq
!= 0) {
220 at91sam7_info
->mck_valid
= 1;
221 tmp
= at91sam7_info
->ext_freq
;
225 case 2: /* Reserved */
228 case 3: /* PLL Clock */
229 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
230 (at91sam7_info
->ext_freq
== 0)) {
231 target_read_u32(target
, CKGR_PLLR
, &pllr
);
232 if (!(pllr
& CKGR_PLLR_DIV
))
234 at91sam7_info
->mck_valid
= 1;
235 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
236 /* Integer arithmetic should have sufficient precision
237 * as long as PLL is properly configured. */
238 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
)*
239 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
240 } else if ((at91sam7_info
->ext_freq
!= 0) &&
241 ((pllr
&CKGR_PLLR_DIV
) != 0)) {
242 at91sam7_info
->mck_valid
= 1;
243 tmp
= at91sam7_info
->ext_freq
/ (pllr
&CKGR_PLLR_DIV
)*
244 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
249 /* Prescaler adjust */
250 if ((((mckr
& PMC_MCKR_PRES
) >> 2) == 7) || (tmp
== 0)) {
251 at91sam7_info
->mck_valid
= 0;
252 at91sam7_info
->mck_freq
= 0;
253 } else if (((mckr
& PMC_MCKR_PRES
) >> 2) != 0)
254 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
256 at91sam7_info
->mck_freq
= tmp
;
259 /* Setup the timimg registers for nvbits or normal flash */
260 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
)
262 uint32_t fmr
, fmcn
= 0, fws
= 0;
263 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
264 struct target
*target
= bank
->target
;
266 if (mode
&& (mode
!= at91sam7_info
->flashmode
)) {
267 /* Always round up (ceil) */
268 if (mode
== FMR_TIMING_NVBITS
) {
269 if (at91sam7_info
->cidr_arch
== 0x60) {
270 /* AT91SAM7A3 uses master clocks in 100 ns */
271 fmcn
= (at91sam7_info
->mck_freq
/10000000ul) + 1;
273 /* master clocks in 1uS for ARCH 0x7 types */
274 fmcn
= (at91sam7_info
->mck_freq
/1000000ul) + 1;
276 } else if (mode
== FMR_TIMING_FLASH
) {
277 /* main clocks in 1.5uS */
278 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+
279 (at91sam7_info
->mck_freq
/2000000ul) + 1;
282 /* hard overclocking */
286 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
287 if (at91sam7_info
->mck_freq
<= 33333ul)
289 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
290 if (at91sam7_info
->mck_freq
> 30000000ul)
293 LOG_DEBUG("fmcn[%i]: %i", bank
->bank_number
, (int)(fmcn
));
294 fmr
= fmcn
<< 16 | fws
<< 8;
295 target_write_u32(target
, MC_FMR
[bank
->bank_number
], fmr
);
298 at91sam7_info
->flashmode
= mode
;
301 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
)
305 while ((!((status
= at91sam7_get_flash_status(bank
->target
,
306 bank
->bank_number
)) & waitbits
)) && (timeout
-- > 0)) {
307 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", (int)bank
->bank_number
, status
);
311 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", bank
->bank_number
, status
);
314 LOG_ERROR("status register: 0x%" PRIx32
"", status
);
316 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
318 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
320 LOG_ERROR("Security Bit Set, Operation Abort");
326 /* Send one command to the AT91SAM flash controller */
327 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
)
330 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
331 struct target
*target
= bank
->target
;
333 fcr
= (0x5A << 24) | ((pagen
&0x3FF) << 8) | cmd
;
334 target_write_u32(target
, MC_FCR
[bank
->bank_number
], fcr
);
335 LOG_DEBUG("Flash command: 0x%" PRIx32
", flash bank: %i, page number: %u",
337 bank
->bank_number
+ 1,
340 if ((at91sam7_info
->cidr_arch
== 0x60) && ((cmd
== SLB
) | (cmd
== CLB
))) {
341 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
342 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
343 return ERROR_FLASH_OPERATION_FAILED
;
347 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
348 return ERROR_FLASH_OPERATION_FAILED
;
353 /* Read device id register, main clock frequency register and fill in driver info structure */
354 static int at91sam7_read_part_info(struct flash_bank
*bank
)
356 struct at91sam7_flash_bank
*at91sam7_info
;
357 struct target
*target
= bank
->target
;
362 uint8_t banks_num
= 0;
363 uint16_t num_nvmbits
= 0;
364 uint16_t sectors_num
= 0;
365 uint16_t pages_per_sector
= 0;
366 uint16_t page_size
= 0;
369 uint32_t base_address
= 0;
370 char *target_name_t
= "Unknown";
372 at91sam7_info
= bank
->driver_priv
;
374 if (at91sam7_info
->cidr
!= 0) {
375 /* flash already configured, update clock and check for protected sectors */
376 struct flash_bank
*fb
= bank
;
377 struct flash_bank
*t_bank
= bank
;
380 /* re-calculate master clock frequency */
381 at91sam7_read_clock_info(t_bank
);
384 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
386 /* check protect state */
387 at91sam7_protect_check(t_bank
);
396 /* Read and parse chip identification register */
397 target_read_u32(target
, DBGU_CIDR
, &cidr
);
399 LOG_WARNING("Cannot identify target as an AT91SAM");
400 return ERROR_FLASH_OPERATION_FAILED
;
403 if (at91sam7_info
->flash_autodetection
== 0) {
404 /* banks and sectors are already created, based on data from input file */
405 struct flash_bank
*fb
= bank
;
406 struct flash_bank
*t_bank
= bank
;
408 at91sam7_info
= t_bank
->driver_priv
;
410 at91sam7_info
->cidr
= cidr
;
411 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
412 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
413 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
414 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
415 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
416 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
417 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
418 at91sam7_info
->cidr_version
= cidr
&0x001F;
420 /* calculate master clock frequency */
421 at91sam7_read_clock_info(t_bank
);
424 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
426 /* check protect state */
427 at91sam7_protect_check(t_bank
);
436 arch
= (cidr
>> 20)&0x00FF;
438 /* check flash size */
439 switch ((cidr
>> 8)&0x000F) {
443 case FLASH_SIZE_16KB
:
446 pages_per_sector
= 32;
448 base_address
= 0x00100000;
451 target_name_t
= "AT91SAM7S161/16";
455 case FLASH_SIZE_32KB
:
458 pages_per_sector
= 32;
460 base_address
= 0x00100000;
463 target_name_t
= "AT91SAM7S321/32";
467 target_name_t
= "AT91SAM7SE32";
471 case FLASH_SIZE_64KB
:
474 pages_per_sector
= 32;
476 base_address
= 0x00100000;
479 target_name_t
= "AT91SAM7S64";
483 case FLASH_SIZE_128KB
:
486 pages_per_sector
= 64;
488 base_address
= 0x00100000;
491 target_name_t
= "AT91SAM7S128";
495 target_name_t
= "AT91SAM7XC128";
499 target_name_t
= "AT91SAM7SE128";
503 target_name_t
= "AT91SAM7X128";
507 case FLASH_SIZE_256KB
:
510 pages_per_sector
= 64;
512 base_address
= 0x00100000;
515 target_name_t
= "AT91SAM7A3";
519 target_name_t
= "AT91SAM7S256";
523 target_name_t
= "AT91SAM7XC256";
527 target_name_t
= "AT91SAM7SE256";
531 target_name_t
= "AT91SAM7X256";
535 case FLASH_SIZE_512KB
:
538 pages_per_sector
= 64;
540 base_address
= 0x00100000;
543 target_name_t
= "AT91SAM7S512";
547 target_name_t
= "AT91SAM7XC512";
551 target_name_t
= "AT91SAM7SE512";
555 target_name_t
= "AT91SAM7X512";
559 case FLASH_SIZE_1024KB
:
562 case FLASH_SIZE_2048KB
:
566 if (strcmp(target_name_t
, "Unknown") == 0) {
568 "Target autodetection failed! Please specify target parameters in configuration file");
569 return ERROR_FLASH_OPERATION_FAILED
;
572 ext_freq
= at91sam7_info
->ext_freq
;
574 /* calculate bank size */
575 bank_size
= sectors_num
* pages_per_sector
* page_size
;
577 for (bnk
= 0; bnk
< banks_num
; bnk
++) {
578 struct flash_bank
*t_bank
= bank
;
581 /* create a new flash bank element */
582 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
584 fb
->driver
= bank
->driver
;
585 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
586 fb
->name
= "sam7_probed";
589 /* link created bank in 'flash_banks' list */
592 t_bank
= t_bank
->next
;
595 t_bank
->bank_number
= bnk
;
596 t_bank
->base
= base_address
+ bnk
* bank_size
;
597 t_bank
->size
= bank_size
;
598 t_bank
->chip_width
= 0;
599 t_bank
->bus_width
= 4;
600 t_bank
->num_sectors
= sectors_num
;
602 /* allocate sectors */
603 t_bank
->sectors
= malloc(sectors_num
* sizeof(struct flash_sector
));
604 for (sec
= 0; sec
< sectors_num
; sec
++) {
605 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
606 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
607 t_bank
->sectors
[sec
].is_erased
= -1;
608 t_bank
->sectors
[sec
].is_protected
= -1;
611 at91sam7_info
= t_bank
->driver_priv
;
613 at91sam7_info
->cidr
= cidr
;
614 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
615 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
616 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
617 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
618 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
619 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
620 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
621 at91sam7_info
->cidr_version
= cidr
&0x001F;
623 at91sam7_info
->target_name
= target_name_t
;
624 at91sam7_info
->flashmode
= 0;
625 at91sam7_info
->ext_freq
= ext_freq
;
626 at91sam7_info
->num_nvmbits
= num_nvmbits
;
627 at91sam7_info
->num_nvmbits_on
= 0;
628 at91sam7_info
->pagesize
= page_size
;
629 at91sam7_info
->pages_per_sector
= pages_per_sector
;
631 /* calculate master clock frequency */
632 at91sam7_read_clock_info(t_bank
);
635 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
637 /* check protect state */
638 at91sam7_protect_check(t_bank
);
641 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
642 at91sam7_info
->cidr_nvptyp
,
643 at91sam7_info
->cidr_arch
);
648 static int at91sam7_erase_check(struct flash_bank
*bank
)
650 struct target
*target
= bank
->target
;
658 if (bank
->target
->state
!= TARGET_HALTED
) {
659 LOG_ERROR("Target not halted");
660 return ERROR_TARGET_NOT_HALTED
;
663 /* Configure the flash controller timing */
664 at91sam7_read_clock_info(bank
);
665 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
668 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++) {
669 retval
= target_blank_check_memory(target
,
670 bank
->base
+ bank
->sectors
[nSector
].offset
,
671 bank
->sectors
[nSector
].size
,
673 if (retval
!= ERROR_OK
) {
678 bank
->sectors
[nSector
].is_erased
= 1;
680 bank
->sectors
[nSector
].is_erased
= 0;
686 LOG_USER("Running slow fallback erase check - add working memory");
688 buffer
= malloc(bank
->sectors
[0].size
);
689 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++) {
690 bank
->sectors
[nSector
].is_erased
= 1;
691 retval
= target_read_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
, 4,
692 bank
->sectors
[nSector
].size
/4, buffer
);
693 if (retval
!= ERROR_OK
)
696 for (nByte
= 0; nByte
< bank
->sectors
[nSector
].size
; nByte
++) {
697 if (buffer
[nByte
] != 0xFF) {
698 bank
->sectors
[nSector
].is_erased
= 0;
708 static int at91sam7_protect_check(struct flash_bank
*bank
)
710 uint8_t lock_pos
, gpnvm_pos
;
713 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
715 if (at91sam7_info
->cidr
== 0)
716 return ERROR_FLASH_BANK_NOT_PROBED
;
717 if (bank
->target
->state
!= TARGET_HALTED
) {
718 LOG_ERROR("Target not halted");
719 return ERROR_TARGET_NOT_HALTED
;
722 status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
);
723 at91sam7_info
->lockbits
= (status
>> 16);
725 at91sam7_info
->num_lockbits_on
= 0;
726 for (lock_pos
= 0; lock_pos
< bank
->num_sectors
; lock_pos
++) {
727 if (((status
>> (16 + lock_pos
))&(0x0001)) == 1) {
728 at91sam7_info
->num_lockbits_on
++;
729 bank
->sectors
[lock_pos
].is_protected
= 1;
731 bank
->sectors
[lock_pos
].is_protected
= 0;
734 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
735 status
= at91sam7_get_flash_status(bank
->target
, 0);
737 at91sam7_info
->securitybit
= (status
>> 4)&0x01;
738 at91sam7_info
->nvmbits
= (status
>> 8)&0xFF;
740 at91sam7_info
->num_nvmbits_on
= 0;
741 for (gpnvm_pos
= 0; gpnvm_pos
< at91sam7_info
->num_nvmbits
; gpnvm_pos
++) {
742 if (((status
>> (8 + gpnvm_pos
))&(0x01)) == 1)
743 at91sam7_info
->num_nvmbits_on
++;
749 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command
)
751 struct flash_bank
*t_bank
= bank
;
752 struct at91sam7_flash_bank
*at91sam7_info
;
753 struct target
*target
= t_bank
->target
;
755 uint32_t base_address
;
757 uint32_t ext_freq
= 0;
764 uint16_t pages_per_sector
;
766 uint16_t num_nvmbits
;
772 at91sam7_info
= malloc(sizeof(struct at91sam7_flash_bank
));
773 t_bank
->driver_priv
= at91sam7_info
;
775 /* part wasn't probed for info yet */
776 at91sam7_info
->cidr
= 0;
777 at91sam7_info
->flashmode
= 0;
778 at91sam7_info
->ext_freq
= 0;
779 at91sam7_info
->flash_autodetection
= 0;
782 at91sam7_info
->flash_autodetection
= 1;
786 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], base_address
);
788 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[3], chip_width
);
789 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[4], bus_width
);
791 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[8], banks_num
);
792 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[9], num_sectors
);
793 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[10], pages_per_sector
);
794 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[11], page_size
);
795 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[12], num_nvmbits
);
797 if (CMD_ARGC
== 14) {
799 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[13], freq
);
800 ext_freq
= freq
* 1000;
801 at91sam7_info
->ext_freq
= ext_freq
;
804 if ((bus_width
== 0) || (banks_num
== 0) || (num_sectors
== 0) ||
805 (pages_per_sector
== 0) || (page_size
== 0) || (num_nvmbits
== 0)) {
806 at91sam7_info
->flash_autodetection
= 1;
810 target_name_t
= calloc(strlen(CMD_ARGV
[7]) + 1, sizeof(char));
811 strcpy(target_name_t
, CMD_ARGV
[7]);
813 /* calculate bank size */
814 bank_size
= num_sectors
* pages_per_sector
* page_size
;
816 for (bnk
= 0; bnk
< banks_num
; bnk
++) {
819 /* create a new bank element */
820 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
822 fb
->driver
= bank
->driver
;
823 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
824 fb
->name
= "sam7_probed";
827 /* link created bank in 'flash_banks' list */
830 t_bank
= t_bank
->next
;
833 t_bank
->bank_number
= bnk
;
834 t_bank
->base
= base_address
+ bnk
* bank_size
;
835 t_bank
->size
= bank_size
;
836 t_bank
->chip_width
= chip_width
;
837 t_bank
->bus_width
= bus_width
;
838 t_bank
->num_sectors
= num_sectors
;
840 /* allocate sectors */
841 t_bank
->sectors
= malloc(num_sectors
* sizeof(struct flash_sector
));
842 for (sec
= 0; sec
< num_sectors
; sec
++) {
843 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
844 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
845 t_bank
->sectors
[sec
].is_erased
= -1;
846 t_bank
->sectors
[sec
].is_protected
= -1;
849 at91sam7_info
= t_bank
->driver_priv
;
851 at91sam7_info
->target_name
= target_name_t
;
852 at91sam7_info
->flashmode
= 0;
853 at91sam7_info
->ext_freq
= ext_freq
;
854 at91sam7_info
->num_nvmbits
= num_nvmbits
;
855 at91sam7_info
->num_nvmbits_on
= 0;
856 at91sam7_info
->pagesize
= page_size
;
857 at91sam7_info
->pages_per_sector
= pages_per_sector
;
863 static int at91sam7_erase(struct flash_bank
*bank
, int first
, int last
)
865 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
867 uint32_t nbytes
, pos
;
871 if (at91sam7_info
->cidr
== 0)
872 return ERROR_FLASH_BANK_NOT_PROBED
;
874 if (bank
->target
->state
!= TARGET_HALTED
) {
875 LOG_ERROR("Target not halted");
876 return ERROR_TARGET_NOT_HALTED
;
879 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
880 return ERROR_FLASH_SECTOR_INVALID
;
883 if ((first
== 0) && (last
== (bank
->num_sectors
-1)))
886 /* Configure the flash controller timing */
887 at91sam7_read_clock_info(bank
);
888 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
891 if (at91sam7_flash_command(bank
, EA
, 0) != ERROR_OK
)
892 return ERROR_FLASH_OPERATION_FAILED
;
894 /* allocate and clean buffer */
895 nbytes
= (last
- first
+ 1) * bank
->sectors
[first
].size
;
896 buffer
= malloc(nbytes
* sizeof(uint8_t));
897 for (pos
= 0; pos
< nbytes
; pos
++)
900 if (at91sam7_write(bank
, buffer
, bank
->sectors
[first
].offset
, nbytes
) != ERROR_OK
) {
902 return ERROR_FLASH_OPERATION_FAILED
;
908 /* mark erased sectors */
909 for (sec
= first
; sec
<= last
; sec
++)
910 bank
->sectors
[sec
].is_erased
= 1;
915 static int at91sam7_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
921 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
923 if (at91sam7_info
->cidr
== 0)
924 return ERROR_FLASH_BANK_NOT_PROBED
;
926 if (bank
->target
->state
!= TARGET_HALTED
) {
927 LOG_ERROR("Target not halted");
928 return ERROR_TARGET_NOT_HALTED
;
931 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
932 return ERROR_FLASH_SECTOR_INVALID
;
934 /* Configure the flash controller timing */
935 at91sam7_read_clock_info(bank
);
936 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
938 for (sector
= first
; sector
<= last
; sector
++) {
944 /* if we lock a page from one sector then entire sector will be locked, also,
945 * if we unlock a page from a locked sector, entire sector will be unlocked */
946 pagen
= sector
* at91sam7_info
->pages_per_sector
;
948 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
949 return ERROR_FLASH_OPERATION_FAILED
;
952 at91sam7_protect_check(bank
);
957 static int at91sam7_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
960 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
961 struct target
*target
= bank
->target
;
962 uint32_t dst_min_alignment
, wcount
, bytes_remaining
= count
;
963 uint32_t first_page
, last_page
, pagen
, buffer_pos
;
965 if (at91sam7_info
->cidr
== 0)
966 return ERROR_FLASH_BANK_NOT_PROBED
;
968 if (bank
->target
->state
!= TARGET_HALTED
) {
969 LOG_ERROR("Target not halted");
970 return ERROR_TARGET_NOT_HALTED
;
973 if (offset
+ count
> bank
->size
)
974 return ERROR_FLASH_DST_OUT_OF_BANK
;
976 dst_min_alignment
= at91sam7_info
->pagesize
;
978 if (offset
% dst_min_alignment
) {
979 LOG_WARNING("offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"",
982 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
985 if (at91sam7_info
->cidr_arch
== 0)
986 return ERROR_FLASH_BANK_NOT_PROBED
;
988 first_page
= offset
/dst_min_alignment
;
989 last_page
= DIV_ROUND_UP(offset
+ count
, dst_min_alignment
);
991 LOG_DEBUG("first_page: %i, last_page: %i, count %i",
996 /* Configure the flash controller timing */
997 at91sam7_read_clock_info(bank
);
998 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
1000 for (pagen
= first_page
; pagen
< last_page
; pagen
++) {
1001 if (bytes_remaining
< dst_min_alignment
)
1002 count
= bytes_remaining
;
1004 count
= dst_min_alignment
;
1005 bytes_remaining
-= count
;
1007 /* Write one block to the PageWriteBuffer */
1008 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
1009 wcount
= DIV_ROUND_UP(count
, 4);
1010 retval
= target_write_memory(target
, bank
->base
+ pagen
*dst_min_alignment
, 4,
1011 wcount
, buffer
+ buffer_pos
);
1012 if (retval
!= ERROR_OK
)
1015 /* Send Write Page command to Flash Controller */
1016 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
1017 return ERROR_FLASH_OPERATION_FAILED
;
1018 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32
"", bank
->bank_number
, pagen
);
1024 static int at91sam7_probe(struct flash_bank
*bank
)
1026 /* we can't probe on an at91sam7
1027 * if this is an at91sam7, it has the configured flash */
1030 if (bank
->target
->state
!= TARGET_HALTED
) {
1031 LOG_ERROR("Target not halted");
1032 return ERROR_TARGET_NOT_HALTED
;
1035 retval
= at91sam7_read_part_info(bank
);
1036 if (retval
!= ERROR_OK
)
1042 static int get_at91sam7_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1045 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
1047 if (at91sam7_info
->cidr
== 0)
1048 return ERROR_FLASH_BANK_NOT_PROBED
;
1050 printed
= snprintf(buf
, buf_size
,
1051 "\n at91sam7 driver information: Chip is %s\n",
1052 at91sam7_info
->target_name
);
1055 buf_size
-= printed
;
1057 printed
= snprintf(buf
,
1059 " Cidr: 0x%8.8" PRIx32
" | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
1060 "Flashsize: 0x%8.8" PRIx32
"\n",
1061 at91sam7_info
->cidr
,
1062 at91sam7_info
->cidr_arch
,
1063 EPROC
[at91sam7_info
->cidr_eproc
],
1064 at91sam7_info
->cidr_version
,
1068 buf_size
-= printed
;
1070 printed
= snprintf(buf
, buf_size
,
1071 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1072 (unsigned)(at91sam7_info
->mck_freq
/ 1000),
1073 (unsigned)(at91sam7_info
->ext_freq
/ 1000));
1076 buf_size
-= printed
;
1078 printed
= snprintf(buf
,
1080 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i\n",
1081 at91sam7_info
->pagesize
,
1083 at91sam7_info
->num_lockbits_on
,
1084 at91sam7_info
->lockbits
,
1085 at91sam7_info
->pages_per_sector
*at91sam7_info
->num_lockbits_on
);
1088 buf_size
-= printed
;
1090 snprintf(buf
, buf_size
,
1091 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1092 at91sam7_info
->securitybit
, at91sam7_info
->num_nvmbits
,
1093 at91sam7_info
->num_nvmbits_on
, at91sam7_info
->nvmbits
);
1099 * On AT91SAM7S: When the gpnvm bits are set with
1100 * > at91sam7 gpnvm bitnr set
1101 * the changes are not visible in the flash controller status register MC_FSR
1102 * until the processor has been reset.
1103 * On the Olimex board this requires a power cycle.
1104 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1105 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1106 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1108 COMMAND_HANDLER(at91sam7_handle_gpnvm_command
)
1110 struct flash_bank
*bank
;
1114 struct at91sam7_flash_bank
*at91sam7_info
;
1118 return ERROR_COMMAND_SYNTAX_ERROR
;
1120 bank
= get_flash_bank_by_num_noprobe(0);
1122 return ERROR_FLASH_BANK_INVALID
;
1123 if (strcmp(bank
->driver
->name
, "at91sam7")) {
1124 command_print(CMD_CTX
, "not an at91sam7 flash bank '%s'", CMD_ARGV
[0]);
1125 return ERROR_FLASH_BANK_INVALID
;
1127 if (bank
->target
->state
!= TARGET_HALTED
) {
1128 LOG_ERROR("target has to be halted to perform flash operation");
1129 return ERROR_TARGET_NOT_HALTED
;
1132 if (strcmp(CMD_ARGV
[1], "set") == 0)
1134 else if (strcmp(CMD_ARGV
[1], "clear") == 0)
1137 return ERROR_COMMAND_SYNTAX_ERROR
;
1139 at91sam7_info
= bank
->driver_priv
;
1140 if (at91sam7_info
->cidr
== 0) {
1141 retval
= at91sam7_read_part_info(bank
);
1142 if (retval
!= ERROR_OK
)
1146 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], bit
);
1147 if ((bit
< 0) || (bit
>= at91sam7_info
->num_nvmbits
)) {
1148 command_print(CMD_CTX
,
1149 "gpnvm bit '#%s' is out of bounds for target %s",
1151 at91sam7_info
->target_name
);
1155 /* Configure the flash controller timing */
1156 at91sam7_read_clock_info(bank
);
1157 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1159 if (at91sam7_flash_command(bank
, flashcmd
, bit
) != ERROR_OK
)
1160 return ERROR_FLASH_OPERATION_FAILED
;
1162 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1163 status
= at91sam7_get_flash_status(bank
->target
, 0);
1164 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32
,
1169 /* check protect state */
1170 at91sam7_protect_check(bank
);
1175 static const struct command_registration at91sam7_exec_command_handlers
[] = {
1178 .handler
= at91sam7_handle_gpnvm_command
,
1179 .mode
= COMMAND_EXEC
,
1180 .help
= "set or clear one General Purpose Non-Volatile Memory "
1182 .usage
= "bitnum ('set'|'clear')",
1184 COMMAND_REGISTRATION_DONE
1186 static const struct command_registration at91sam7_command_handlers
[] = {
1189 .mode
= COMMAND_ANY
,
1190 .help
= "at91sam7 flash command group",
1192 .chain
= at91sam7_exec_command_handlers
,
1194 COMMAND_REGISTRATION_DONE
1197 struct flash_driver at91sam7_flash
= {
1199 .usage
= "gpnvm <bit> <set | clear>",
1200 .commands
= at91sam7_command_handlers
,
1201 .flash_bank_command
= at91sam7_flash_bank_command
,
1202 .erase
= at91sam7_erase
,
1203 .protect
= at91sam7_protect
,
1204 .write
= at91sam7_write
,
1205 .read
= default_flash_read
,
1206 .probe
= at91sam7_probe
,
1207 .auto_probe
= at91sam7_probe
,
1208 .erase_check
= at91sam7_erase_check
,
1209 .protect_check
= at91sam7_protect_check
,
1210 .info
= get_at91sam7_info
,
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