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[openocd.git] / src / flash / nor / ambiqmicro.c
1 /******************************************************************************
2 *
3 * @file ambiqmicro.c
4 *
5 * @brief Ambiq Micro flash driver.
6 *
7 *****************************************************************************/
8
9 /******************************************************************************
10 * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
11 *
12 * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
13 *
14 * Copyright (c) 2015-2016, Ambiq Micro, Inc.
15 *
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are met:
20 *
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 *
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * 3. Neither the name of the copyright holder nor the names of its
29 * contributors may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGE.
43 *
44 *****************************************************************************/
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "jtag/interface.h"
50 #include "imp.h"
51 #include "target/algorithm.h"
52 #include "target/armv7m.h"
53 #include "target/cortex_m.h"
54
55 /** Check error, log error. */
56 #define CHECK_STATUS(rc, msg) { \
57 if (rc != ERROR_OK) { \
58 LOG_ERROR("status(%d):%s\n", rc, msg); } }
59
60 /*
61 * Address and Key defines.
62 */
63 #define PROGRAM_KEY (0x12344321)
64 #define OTP_PROGRAM_KEY (0x87655678)
65
66 #define FLASH_PROGRAM_MAIN_FROM_SRAM 0x0800005d
67 #define FLASH_PROGRAM_OTP_FROM_SRAM 0x08000061
68 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM 0x08000065
69 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM 0x08000069
70
71
72 static const uint32_t apollo_flash_size[] = {
73 1 << 15,
74 1 << 16,
75 1 << 17,
76 1 << 18,
77 1 << 19,
78 1 << 20,
79 1 << 21
80 };
81
82 static const uint32_t apollo_sram_size[] = {
83 1 << 15,
84 1 << 16,
85 1 << 17,
86 1 << 18,
87 1 << 19,
88 1 << 20,
89 1 << 21
90 };
91
92 struct ambiqmicro_flash_bank {
93 /* chip id register */
94
95 uint32_t probed;
96
97 const char *target_name;
98 uint8_t target_class;
99
100 uint32_t sramsiz;
101 uint32_t flshsiz;
102
103 /* flash geometry */
104 uint32_t num_pages;
105 uint32_t pagesize;
106 uint32_t pages_in_lockregion;
107
108 /* nv memory bits */
109 uint16_t num_lockbits;
110
111 /* main clock status */
112 uint32_t rcc;
113 uint32_t rcc2;
114 uint8_t mck_valid;
115 uint8_t xtal_mask;
116 uint32_t iosc_freq;
117 uint32_t mck_freq;
118 const char *iosc_desc;
119 const char *mck_desc;
120 };
121
122 static struct {
123 uint8_t class;
124 uint8_t partno;
125 const char *partname;
126 } ambiqmicroParts[6] = {
127 {0xFF, 0x00, "Unknown"},
128 {0x01, 0x00, "Apollo"},
129 {0x02, 0x00, "Apollo2"},
130 {0x03, 0x00, "Unknown"},
131 {0x04, 0x00, "Unknown"},
132 {0x05, 0x00, "Apollo"},
133 };
134
135 static char *ambiqmicroClassname[6] = {
136 "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
137 };
138
139 /***************************************************************************
140 * openocd command interface *
141 ***************************************************************************/
142
143 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
144 */
145 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
146 {
147 struct ambiqmicro_flash_bank *ambiqmicro_info;
148
149 if (CMD_ARGC < 6)
150 return ERROR_COMMAND_SYNTAX_ERROR;
151
152 ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
153
154 bank->driver_priv = ambiqmicro_info;
155
156 ambiqmicro_info->target_name = "Unknown target";
157
158 /* part wasn't probed yet */
159 ambiqmicro_info->probed = 0;
160
161 return ERROR_OK;
162 }
163
164 static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
165 {
166 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
167 int printed;
168 char *classname;
169
170 if (ambiqmicro_info->probed == 0) {
171 LOG_ERROR("Target not probed");
172 return ERROR_FLASH_BANK_NOT_PROBED;
173 }
174
175 /* Check class name in range. */
176 if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
177 classname = ambiqmicroClassname[ambiqmicro_info->target_class];
178 else
179 classname = ambiqmicroClassname[0];
180
181 printed = snprintf(buf,
182 buf_size,
183 "\nAmbiq Micro information: Chip is "
184 "class %d (%s) %s\n",
185 ambiqmicro_info->target_class,
186 classname,
187 ambiqmicro_info->target_name);
188
189 if ((printed < 0))
190 return ERROR_BUF_TOO_SMALL;
191 return ERROR_OK;
192 }
193
194 /***************************************************************************
195 * chip identification and status *
196 ***************************************************************************/
197
198 /* Fill in driver info structure */
199 static int ambiqmicro_read_part_info(struct flash_bank *bank)
200 {
201 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
202 struct target *target = bank->target;
203 uint32_t PartNum = 0;
204 int retval;
205
206 /*
207 * Read Part Number.
208 */
209 retval = target_read_u32(target, 0x40020000, &PartNum);
210 if (retval != ERROR_OK) {
211 LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
212 /* Set PartNum to default device */
213 PartNum = 0;
214 }
215 LOG_DEBUG("Part number: 0x%x", PartNum);
216
217 /*
218 * Determine device class.
219 */
220 ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
221
222 switch (ambiqmicro_info->target_class) {
223 case 1: /* 1 - Apollo */
224 case 5: /* 5 - Apollo Bootloader */
225 bank->base = bank->bank_number * 0x40000;
226 ambiqmicro_info->pagesize = 2048;
227 ambiqmicro_info->flshsiz =
228 apollo_flash_size[(PartNum & 0x00F00000) >> 20];
229 ambiqmicro_info->sramsiz =
230 apollo_sram_size[(PartNum & 0x000F0000) >> 16];
231 ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
232 ambiqmicro_info->pagesize;
233 if (ambiqmicro_info->num_pages > 128) {
234 ambiqmicro_info->num_pages = 128;
235 ambiqmicro_info->flshsiz = 1024 * 256;
236 }
237 break;
238
239 default:
240 LOG_INFO("Unknown Class. Using Apollo-64 as default.");
241
242 bank->base = bank->bank_number * 0x40000;
243 ambiqmicro_info->pagesize = 2048;
244 ambiqmicro_info->flshsiz = apollo_flash_size[1];
245 ambiqmicro_info->sramsiz = apollo_sram_size[0];
246 ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
247 ambiqmicro_info->pagesize;
248 if (ambiqmicro_info->num_pages > 128) {
249 ambiqmicro_info->num_pages = 128;
250 ambiqmicro_info->flshsiz = 1024 * 256;
251 }
252 break;
253
254 }
255
256 if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
257 ambiqmicro_info->target_name =
258 ambiqmicroParts[ambiqmicro_info->target_class].partname;
259 else
260 ambiqmicro_info->target_name =
261 ambiqmicroParts[0].partname;
262
263 LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
264 ambiqmicro_info->num_pages,
265 ambiqmicro_info->pagesize,
266 ambiqmicro_info->flshsiz,
267 ambiqmicro_info->sramsiz);
268
269 return ERROR_OK;
270 }
271
272 /***************************************************************************
273 * flash operations *
274 ***************************************************************************/
275
276 static int ambiqmicro_protect_check(struct flash_bank *bank)
277 {
278 struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
279 int status = ERROR_OK;
280 uint32_t i;
281
282
283 if (ambiqmicro->probed == 0) {
284 LOG_ERROR("Target not probed");
285 return ERROR_FLASH_BANK_NOT_PROBED;
286 }
287
288 for (i = 0; i < (unsigned) bank->num_sectors; i++)
289 bank->sectors[i].is_protected = -1;
290
291 return status;
292 }
293 /** Read flash status from bootloader. */
294 static int check_flash_status(struct target *target, uint32_t address)
295 {
296 uint32_t retflash;
297 int rc;
298 rc = target_read_u32(target, address, &retflash);
299 /* target connection failed. */
300 if (rc != ERROR_OK) {
301 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
302 __FILE__, __LINE__, __func__, rc);
303 return rc;
304 }
305 /* target flash failed, unknown cause. */
306 if (retflash != 0) {
307 LOG_ERROR("Flash not happy: status(0x%x)", retflash);
308 return ERROR_FLASH_OPERATION_FAILED;
309 }
310 return ERROR_OK;
311 }
312
313 static int ambiqmicro_exec_command(struct target *target,
314 uint32_t command,
315 uint32_t flash_return_address)
316 {
317 int retval, retflash;
318
319 retval = target_resume(
320 target,
321 false,
322 command,
323 true,
324 true);
325
326 CHECK_STATUS(retval, "error executing ambiqmicro command");
327
328 /*
329 * Wait for halt.
330 */
331 for (;; ) {
332 target_poll(target);
333 if (target->state == TARGET_HALTED)
334 break;
335 else if (target->state == TARGET_RUNNING ||
336 target->state == TARGET_DEBUG_RUNNING) {
337 /*
338 * Keep polling until target halts.
339 */
340 target_poll(target);
341 alive_sleep(100);
342 LOG_DEBUG("state = %d", target->state);
343 } else {
344 LOG_ERROR("Target not halted or running %d", target->state);
345 break;
346 }
347 }
348
349 /*
350 * Read return value, flash error takes precedence.
351 */
352 retflash = check_flash_status(target, flash_return_address);
353 if (retflash != ERROR_OK)
354 retval = retflash;
355
356 /* Return code from target_resume OR flash. */
357 return retval;
358 }
359
360 static int ambiqmicro_mass_erase(struct flash_bank *bank)
361 {
362 struct target *target = NULL;
363 struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
364 int retval = ERROR_OK;
365
366 ambiqmicro_info = bank->driver_priv;
367 target = bank->target;
368
369 if (target->state != TARGET_HALTED) {
370 LOG_ERROR("Target not halted");
371 return ERROR_TARGET_NOT_HALTED;
372 }
373
374 if (ambiqmicro_info->probed == 0) {
375 LOG_ERROR("Target not probed");
376 return ERROR_FLASH_BANK_NOT_PROBED;
377 }
378
379 /*
380 * Clear Bootloader bit.
381 */
382 retval = target_write_u32(target, 0x400201a0, 0x0);
383 CHECK_STATUS(retval, "error clearing bootloader bit.");
384
385 /*
386 * Set up the SRAM.
387 */
388
389 /*
390 * Bank.
391 */
392 retval = target_write_u32(target, 0x10000000, bank->bank_number);
393 CHECK_STATUS(retval, "error writing target SRAM parameters.");
394
395 /*
396 * Write Key.
397 */
398 retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
399 CHECK_STATUS(retval, "error writing target SRAM parameters.");
400
401 /*
402 * Breakpoint.
403 */
404 retval = target_write_u32(target, 0x10000008, 0xfffffffe);
405 CHECK_STATUS(retval, "error writing target SRAM parameters.");
406
407 /*
408 * Erase the main array.
409 */
410 LOG_INFO("Mass erase on bank %d.", bank->bank_number);
411
412 /*
413 * passed pc, addr = ROM function, handle breakpoints, not debugging.
414 */
415 retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
416 CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
417 if (retval != ERROR_OK)
418 return retval;
419
420 /*
421 * Set Bootloader bit, regardless of command execution.
422 */
423 retval = target_write_u32(target, 0x400201a0, 0x1);
424 CHECK_STATUS(retval, "error setting bootloader bit.");
425
426 return retval;
427 }
428
429
430 static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
431 {
432 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
433 struct target *target = bank->target;
434 uint32_t retval = ERROR_OK;
435
436 if (bank->target->state != TARGET_HALTED) {
437 LOG_ERROR("Target not halted");
438 return ERROR_TARGET_NOT_HALTED;
439 }
440
441 if (ambiqmicro_info->probed == 0) {
442 LOG_ERROR("Target not probed");
443 return ERROR_FLASH_BANK_NOT_PROBED;
444 }
445
446 /*
447 * Check pages.
448 * Fix num_pages for the device.
449 */
450 if ((first < 0) || (last < first) || (last >= (int)ambiqmicro_info->num_pages))
451 return ERROR_FLASH_SECTOR_INVALID;
452
453 /*
454 * Just Mass Erase if all pages are given.
455 * TODO: Fix num_pages for the device
456 */
457 if ((first == 0) && (last == ((int)ambiqmicro_info->num_pages-1)))
458 return ambiqmicro_mass_erase(bank);
459
460 /*
461 * Clear Bootloader bit.
462 */
463 retval = target_write_u32(target, 0x400201a0, 0x0);
464 CHECK_STATUS(retval, "error clearing bootloader bit.");
465
466 /*
467 * Set up the SRAM.
468 */
469
470 /*
471 * Bank.
472 */
473 retval = target_write_u32(target, 0x10000000, bank->bank_number);
474 CHECK_STATUS(retval, "error writing target SRAM parameters.");
475
476 /*
477 * Number of pages to erase.
478 */
479 retval = target_write_u32(target, 0x10000004, 1 + (last-first));
480 CHECK_STATUS(retval, "error writing target SRAM parameters.");
481
482 /*
483 * Write Key.
484 */
485 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
486 CHECK_STATUS(retval, "error writing target SRAM parameters.");
487
488 /*
489 * Breakpoint.
490 */
491 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
492 CHECK_STATUS(retval, "error writing target SRAM parameters.");
493
494 /*
495 * Pointer to flash address.
496 */
497 retval = target_write_u32(target, 0x10000010, first);
498 CHECK_STATUS(retval, "error writing target SRAM parameters.");
499 if (retval != ERROR_OK)
500 return retval;
501
502 /*
503 * Erase the pages.
504 */
505 LOG_INFO("Erasing pages %d to %d on bank %d", first, last, bank->bank_number);
506
507 /*
508 * passed pc, addr = ROM function, handle breakpoints, not debugging.
509 */
510 retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
511 CHECK_STATUS(retval, "error executing flash page erase");
512 if (retval != ERROR_OK)
513 return retval;
514
515 LOG_INFO("%d pages erased!", 1+(last-first));
516
517 if (first == 0) {
518 /*
519 * Set Bootloader bit.
520 */
521 retval = target_write_u32(target, 0x400201a0, 0x1);
522 CHECK_STATUS(retval, "error setting bootloader bit.");
523 if (retval != ERROR_OK)
524 return retval;
525 }
526
527 return retval;
528 }
529
530 static int ambiqmicro_protect(struct flash_bank *bank, int set, int first, int last)
531 {
532 /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
533 * struct target *target = bank->target; */
534
535 /*
536 * TODO
537 */
538 LOG_INFO("Not yet implemented");
539
540 if (bank->target->state != TARGET_HALTED) {
541 LOG_ERROR("Target not halted");
542 return ERROR_TARGET_NOT_HALTED;
543 }
544
545 return ERROR_OK;
546 }
547
548 static int ambiqmicro_write_block(struct flash_bank *bank,
549 const uint8_t *buffer, uint32_t offset, uint32_t count)
550 {
551 /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
552 struct target *target = bank->target;
553 uint32_t address = bank->base + offset;
554 uint32_t buffer_pointer = 0x10000010;
555 uint32_t maxbuffer;
556 uint32_t thisrun_count;
557 int retval = ERROR_OK;
558
559 if (((count%4) != 0) || ((offset%4) != 0)) {
560 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
561 return ERROR_FAIL;
562 }
563
564 /*
565 * Max buffer size for this device.
566 * Hard code 6kB for the buffer.
567 */
568 maxbuffer = 0x1800;
569
570 LOG_INFO("Flashing main array");
571
572 while (count > 0) {
573 if (count > maxbuffer)
574 thisrun_count = maxbuffer;
575 else
576 thisrun_count = count;
577
578 /*
579 * Set up the SRAM.
580 */
581
582 /*
583 * Pointer to flash.
584 */
585 retval = target_write_u32(target, 0x10000000, address);
586 CHECK_STATUS(retval, "error writing target SRAM parameters.");
587
588 /*
589 * Number of 32-bit words to program.
590 */
591 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
592 CHECK_STATUS(retval, "error writing target SRAM parameters.");
593
594 /*
595 * Write Key.
596 */
597 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
598 CHECK_STATUS(retval, "error writing target SRAM parameters.");
599
600 /*
601 * Breakpoint.
602 */
603 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
604 CHECK_STATUS(retval, "error writing target SRAM parameters.");
605
606 /*
607 * Write Buffer.
608 */
609 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
610
611 if (retval != ERROR_OK) {
612 CHECK_STATUS(retval, "error writing target SRAM parameters.");
613 break;
614 }
615
616 LOG_DEBUG("address = 0x%08x", address);
617
618 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
619 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
620 if (retval != ERROR_OK)
621 break;
622 buffer += thisrun_count;
623 address += thisrun_count;
624 count -= thisrun_count;
625 }
626
627
628 LOG_INFO("Main array flashed");
629
630 /*
631 * Clear Bootloader bit.
632 */
633 retval = target_write_u32(target, 0x400201a0, 0x0);
634 CHECK_STATUS(retval, "error clearing bootloader bit");
635
636 return retval;
637 }
638
639 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
640 uint32_t offset, uint32_t count)
641 {
642 uint32_t retval;
643
644 /* try using a block write */
645 retval = ambiqmicro_write_block(bank, buffer, offset, count);
646 if (retval != ERROR_OK)
647 LOG_ERROR("write failed");
648
649 return retval;
650 }
651
652 static int ambiqmicro_probe(struct flash_bank *bank)
653 {
654 struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
655 uint32_t retval;
656
657 /* If this is a ambiqmicro chip, it has flash; probe() is just
658 * to figure out how much is present. Only do it once.
659 */
660 if (ambiqmicro_info->probed == 1) {
661 LOG_INFO("Target already probed");
662 return ERROR_OK;
663 }
664
665 /* ambiqmicro_read_part_info() already handled error checking and
666 * reporting. Note that it doesn't write, so we don't care about
667 * whether the target is halted or not.
668 */
669 retval = ambiqmicro_read_part_info(bank);
670 if (retval != ERROR_OK)
671 return retval;
672
673 if (bank->sectors) {
674 free(bank->sectors);
675 bank->sectors = NULL;
676 }
677
678 /* provide this for the benefit of the NOR flash framework */
679 bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
680 bank->num_sectors = ambiqmicro_info->num_pages;
681 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
682 for (int i = 0; i < bank->num_sectors; i++) {
683 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
684 bank->sectors[i].size = ambiqmicro_info->pagesize;
685 bank->sectors[i].is_erased = -1;
686 bank->sectors[i].is_protected = -1;
687 }
688
689 /*
690 * Part has been probed.
691 */
692 ambiqmicro_info->probed = 1;
693
694 return retval;
695 }
696
697 static int ambiqmicro_otp_program(struct flash_bank *bank,
698 uint32_t offset, uint32_t count)
699 {
700 struct target *target = NULL;
701 struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
702 uint32_t retval = ERROR_OK;
703
704 ambiqmicro_info = bank->driver_priv;
705 target = bank->target;
706
707 if (target->state != TARGET_HALTED) {
708 LOG_ERROR("Target not halted");
709 return ERROR_TARGET_NOT_HALTED;
710 }
711
712 if (ambiqmicro_info->probed == 0) {
713 LOG_ERROR("Target not probed");
714 return ERROR_FLASH_BANK_NOT_PROBED;
715 }
716
717 if (count > 256) {
718 LOG_ERROR("Count must be < 256");
719 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
720 }
721
722 /*
723 * Clear Bootloader bit.
724 */
725 retval = target_write_u32(target, 0x400201a0, 0x0);
726 CHECK_STATUS(retval, "error clearing bootloader bit.");
727
728 /*
729 * Set up the SRAM.
730 */
731
732 /*
733 * Bank.
734 */
735 retval = target_write_u32(target, 0x10000000, offset);
736 CHECK_STATUS(retval, "error setting target SRAM parameters.");
737
738 /*
739 * Num of words to program.
740 */
741 retval = target_write_u32(target, 0x10000004, count);
742 CHECK_STATUS(retval, "error setting target SRAM parameters.");
743
744 /*
745 * Write Key.
746 */
747 retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
748 CHECK_STATUS(retval, "error setting target SRAM parameters.");
749
750 /*
751 * Breakpoint.
752 */
753 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
754 CHECK_STATUS(retval, "error setting target SRAM parameters.");
755 if (retval != ERROR_OK)
756 return retval;
757
758 /*
759 * Program OTP.
760 */
761 LOG_INFO("Programming OTP offset 0x%08x", offset);
762
763 /*
764 * passed pc, addr = ROM function, handle breakpoints, not debugging.
765 */
766 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
767 CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
768
769 LOG_INFO("Programming OTP finished.");
770
771 return retval;
772 }
773
774
775
776 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
777 {
778 int i;
779
780 if (CMD_ARGC < 1)
781 return ERROR_COMMAND_SYNTAX_ERROR;
782
783 struct flash_bank *bank;
784 uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
785 if (ERROR_OK != retval)
786 return retval;
787
788 if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
789 /* set all sectors as erased */
790 for (i = 0; i < bank->num_sectors; i++)
791 bank->sectors[i].is_erased = 1;
792
793 command_print(CMD, "ambiqmicro mass erase complete");
794 } else
795 command_print(CMD, "ambiqmicro mass erase failed");
796
797 return ERROR_OK;
798 }
799
800 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
801 {
802 struct flash_bank *bank;
803 uint32_t first, last;
804 uint32_t retval;
805
806 if (CMD_ARGC < 3)
807 return ERROR_COMMAND_SYNTAX_ERROR;
808
809 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
810 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
811
812 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
813 if (ERROR_OK != retval)
814 return retval;
815
816 if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
817 command_print(CMD, "ambiqmicro page erase complete");
818 else
819 command_print(CMD, "ambiqmicro page erase failed");
820
821 return ERROR_OK;
822 }
823
824
825 /**
826 * Program the otp block.
827 */
828 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
829 {
830 struct flash_bank *bank;
831 uint32_t offset, count;
832 uint32_t retval;
833
834 if (CMD_ARGC < 3)
835 return ERROR_COMMAND_SYNTAX_ERROR;
836
837 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
838 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
839
840 command_print(CMD, "offset=0x%08x count=%d", offset, count);
841
842 CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
843
844 retval = ambiqmicro_otp_program(bank, offset, count);
845
846 if (retval != ERROR_OK)
847 LOG_ERROR("error check log");
848
849 return ERROR_OK;
850 }
851
852
853
854 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
855 {
856 .name = "mass_erase",
857 .usage = "<bank>",
858 .handler = ambiqmicro_handle_mass_erase_command,
859 .mode = COMMAND_EXEC,
860 .help = "Erase entire device",
861 },
862 {
863 .name = "page_erase",
864 .usage = "<bank> <first> <last>",
865 .handler = ambiqmicro_handle_page_erase_command,
866 .mode = COMMAND_EXEC,
867 .help = "Erase device pages",
868 },
869 {
870 .name = "program_otp",
871 .handler = ambiqmicro_handle_program_otp_command,
872 .mode = COMMAND_EXEC,
873 .usage = "<bank> <offset> <count>",
874 .help =
875 "Program OTP (assumes you have already written array starting at 0x10000010)",
876 },
877 COMMAND_REGISTRATION_DONE
878 };
879 static const struct command_registration ambiqmicro_command_handlers[] = {
880 {
881 .name = "ambiqmicro",
882 .mode = COMMAND_EXEC,
883 .help = "ambiqmicro flash command group",
884 .usage = "Support for Ambiq Micro parts.",
885 .chain = ambiqmicro_exec_command_handlers,
886 },
887 COMMAND_REGISTRATION_DONE
888 };
889
890 const struct flash_driver ambiqmicro_flash = {
891 .name = "ambiqmicro",
892 .commands = ambiqmicro_command_handlers,
893 .flash_bank_command = ambiqmicro_flash_bank_command,
894 .erase = ambiqmicro_erase,
895 .protect = ambiqmicro_protect,
896 .write = ambiqmicro_write,
897 .read = default_flash_read,
898 .probe = ambiqmicro_probe,
899 .auto_probe = ambiqmicro_probe,
900 .erase_check = default_flash_blank_check,
901 .protect_check = ambiqmicro_protect_check,
902 .info = get_ambiqmicro_info,
903 .free_driver_priv = default_flash_free_driver_priv,
904 };
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