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ARMv7-M: make DAP commands verify target is an ARMv7-M
[openocd.git] / src / flash / nand / mx3.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "imp.h"
39 #include "mx3.h"
40 #include <target/target.h>
41
42 static const char target_not_halted_err_msg[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg[] =
45 "minimal granularity is one half-word, %" PRId32 " is incorrect";
46 static const char sram_buffer_bounds_err_msg[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
48 static const char get_status_register_err_msg[] = "can't get NAND status";
49 static uint32_t in_sram_address;
50 unsigned char sign_of_sequental_byte_read;
51
52 static int test_iomux_settings (struct target * target, uint32_t value,
53 uint32_t mask, const char *text);
54 static int initialize_nf_controller (struct nand_device *nand);
55 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
56 static int get_next_halfword_from_sram_buffer (struct target * target,
57 uint16_t * value);
58 static int poll_for_complete_op (struct target * target, const char *text);
59 static int validate_target_state (struct nand_device *nand);
60 static int do_data_output (struct nand_device *nand);
61
62 static int imx31_command (struct nand_device *nand, uint8_t command);
63 static int imx31_address (struct nand_device *nand, uint8_t address);
64 static int imx31_controller_ready (struct nand_device *nand, int tout);
65
66 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
67 {
68 struct mx3_nf_controller *mx3_nf_info;
69 mx3_nf_info = malloc (sizeof (struct mx3_nf_controller));
70 if (mx3_nf_info == NULL)
71 {
72 LOG_ERROR ("no memory for nand controller");
73 return ERROR_FAIL;
74 }
75
76 nand->controller_priv = mx3_nf_info;
77
78 mx3_nf_info->target = get_target (CMD_ARGV[1]);
79 if (mx3_nf_info->target == NULL)
80 {
81 LOG_ERROR ("target '%s' not defined", CMD_ARGV[1]);
82 return ERROR_FAIL;
83 }
84 if (CMD_ARGC < 3)
85 {
86 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
87 return ERROR_FAIL;
88 }
89 /*
90 * check hwecc requirements
91 */
92 {
93 int hwecc_needed;
94 hwecc_needed = strcmp (CMD_ARGV[2], "hwecc");
95 if (hwecc_needed == 0)
96 {
97 mx3_nf_info->flags.hw_ecc_enabled = 1;
98 }
99 else
100 {
101 mx3_nf_info->flags.hw_ecc_enabled = 0;
102 }
103 }
104
105 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
106 mx3_nf_info->fin = MX3_NF_FIN_NONE;
107 mx3_nf_info->flags.target_little_endian =
108 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
109 /*
110 * testing host endianess
111 */
112 {
113 int x = 1;
114 if (*(char *) &x == 1)
115 {
116 mx3_nf_info->flags.host_little_endian = 1;
117 }
118 else
119 {
120 mx3_nf_info->flags.host_little_endian = 0;
121 }
122 }
123 return ERROR_OK;
124 }
125
126 static int imx31_init (struct nand_device *nand)
127 {
128 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
129 struct target *target = mx3_nf_info->target;
130
131 {
132 /*
133 * validate target state
134 */
135 int validate_target_result;
136 validate_target_result = validate_target_state(nand);
137 if (validate_target_result != ERROR_OK)
138 {
139 return validate_target_result;
140 }
141 }
142
143 {
144 uint16_t buffsize_register_content;
145 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
146 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
147 }
148
149 {
150 uint32_t pcsr_register_content;
151 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
152 if (!nand->bus_width)
153 {
154 nand->bus_width =
155 (pcsr_register_content & 0x80000000) ? 16 : 8;
156 }
157 else
158 {
159 pcsr_register_content |=
160 ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
161 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
162 }
163
164 if (!nand->page_size)
165 {
166 nand->page_size =
167 (pcsr_register_content & 0x40000000) ? 2048 : 512;
168 }
169 else
170 {
171 pcsr_register_content |=
172 ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
173 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
174 }
175 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048))
176 {
177 LOG_ERROR
178 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
179 }
180 }
181
182 {
183 uint32_t cgr_register_content;
184 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
185 if (!(cgr_register_content & 0x00000300))
186 {
187 LOG_ERROR ("clock gating to EMI disabled");
188 return ERROR_FAIL;
189 }
190 }
191
192 {
193 uint32_t gpr_register_content;
194 target_read_u32 (target, MX3_GPR, &gpr_register_content);
195 if (gpr_register_content & 0x00000060)
196 {
197 LOG_ERROR ("pins mode overrided by GPR");
198 return ERROR_FAIL;
199 }
200 }
201
202 {
203 /*
204 * testing IOMUX settings; must be in "functional-mode output and
205 * functional-mode input" mode
206 */
207 int test_iomux;
208 test_iomux = ERROR_OK;
209 test_iomux |=
210 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
211 test_iomux |=
212 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
213 test_iomux |=
214 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
215 if (nand->bus_width == 16)
216 {
217 test_iomux |=
218 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
219 "d8,d9,d10");
220 test_iomux |=
221 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
222 "d11,d12,d13,d14");
223 test_iomux |=
224 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
225 }
226 test_iomux |=
227 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
228 "nfwp,nfce,nfrb");
229 test_iomux |=
230 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
231 "nfwe,nfre,nfale,nfcle");
232 if (test_iomux != ERROR_OK)
233 {
234 return ERROR_FAIL;
235 }
236 }
237
238 initialize_nf_controller (nand);
239
240 {
241 int retval;
242 uint16_t nand_status_content;
243 retval = ERROR_OK;
244 retval |= imx31_command (nand, NAND_CMD_STATUS);
245 retval |= imx31_address (nand, 0x00);
246 retval |= do_data_output (nand);
247 if (retval != ERROR_OK)
248 {
249 LOG_ERROR (get_status_register_err_msg);
250 return ERROR_FAIL;
251 }
252 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
253 if (!(nand_status_content & 0x0080))
254 {
255 /*
256 * is host-big-endian correctly ??
257 */
258 LOG_INFO ("NAND read-only");
259 mx3_nf_info->flags.nand_readonly = 1;
260 }
261 else
262 {
263 mx3_nf_info->flags.nand_readonly = 0;
264 }
265 }
266 return ERROR_OK;
267 }
268
269 static int imx31_read_data (struct nand_device *nand, void *data)
270 {
271 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
272 struct target *target = mx3_nf_info->target;
273 {
274 /*
275 * validate target state
276 */
277 int validate_target_result;
278 validate_target_result = validate_target_state (nand);
279 if (validate_target_result != ERROR_OK)
280 {
281 return validate_target_result;
282 }
283 }
284
285 {
286 /*
287 * get data from nand chip
288 */
289 int try_data_output_from_nand_chip;
290 try_data_output_from_nand_chip = do_data_output (nand);
291 if (try_data_output_from_nand_chip != ERROR_OK)
292 {
293 return try_data_output_from_nand_chip;
294 }
295 }
296
297 if (nand->bus_width == 16)
298 {
299 get_next_halfword_from_sram_buffer (target, data);
300 }
301 else
302 {
303 get_next_byte_from_sram_buffer (target, data);
304 }
305
306 return ERROR_OK;
307 }
308
309 static int imx31_write_data (struct nand_device *nand, uint16_t data)
310 {
311 LOG_ERROR ("write_data() not implemented");
312 return ERROR_NAND_OPERATION_FAILED;
313 }
314
315 static int imx31_nand_ready (struct nand_device *nand, int timeout)
316 {
317 return imx31_controller_ready (nand, timeout);
318 }
319
320 static int imx31_reset (struct nand_device *nand)
321 {
322 /*
323 * validate target state
324 */
325 int validate_target_result;
326 validate_target_result = validate_target_state (nand);
327 if (validate_target_result != ERROR_OK)
328 {
329 return validate_target_result;
330 }
331 initialize_nf_controller (nand);
332 return ERROR_OK;
333 }
334
335 static int imx31_command (struct nand_device *nand, uint8_t command)
336 {
337 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
338 struct target *target = mx3_nf_info->target;
339 {
340 /*
341 * validate target state
342 */
343 int validate_target_result;
344 validate_target_result = validate_target_state (nand);
345 if (validate_target_result != ERROR_OK)
346 {
347 return validate_target_result;
348 }
349 }
350
351 switch (command)
352 {
353 case NAND_CMD_READOOB:
354 command = NAND_CMD_READ0;
355 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
356 * data_read() and
357 * read_block_data() to
358 * spare area in SRAM
359 * buffer */
360 break;
361 case NAND_CMD_READ1:
362 command = NAND_CMD_READ0;
363 /*
364 * offset == one half of page size
365 */
366 in_sram_address =
367 MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
368 default:
369 in_sram_address = MX3_NF_MAIN_BUFFER0;
370 }
371
372 target_write_u16 (target, MX3_NF_FCMD, command);
373 /*
374 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
375 */
376 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
377 {
378 int poll_result;
379 poll_result = poll_for_complete_op (target, "command");
380 if (poll_result != ERROR_OK)
381 {
382 return poll_result;
383 }
384 }
385 /*
386 * reset cursor to begin of the buffer
387 */
388 sign_of_sequental_byte_read = 0;
389 switch (command)
390 {
391 case NAND_CMD_READID:
392 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
393 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
394 break;
395 case NAND_CMD_STATUS:
396 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
397 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
398 break;
399 case NAND_CMD_READ0:
400 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
401 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
402 break;
403 default:
404 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
405 }
406 return ERROR_OK;
407 }
408
409 static int imx31_address (struct nand_device *nand, uint8_t address)
410 {
411 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
412 struct target *target = mx3_nf_info->target;
413 {
414 /*
415 * validate target state
416 */
417 int validate_target_result;
418 validate_target_result = validate_target_state (nand);
419 if (validate_target_result != ERROR_OK)
420 {
421 return validate_target_result;
422 }
423 }
424
425 target_write_u16 (target, MX3_NF_FADDR, address);
426 /*
427 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
428 */
429 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
430 {
431 int poll_result;
432 poll_result = poll_for_complete_op (target, "address");
433 if (poll_result != ERROR_OK)
434 {
435 return poll_result;
436 }
437 }
438 return ERROR_OK;
439 }
440
441 static int imx31_controller_ready (struct nand_device *nand, int tout)
442 {
443 uint16_t poll_complete_status;
444 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
445 struct target *target = mx3_nf_info->target;
446
447 {
448 /*
449 * validate target state
450 */
451 int validate_target_result;
452 validate_target_result = validate_target_state (nand);
453 if (validate_target_result != ERROR_OK)
454 {
455 return validate_target_result;
456 }
457 }
458
459 do
460 {
461 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
462 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
463 {
464 return tout;
465 }
466 alive_sleep (1);
467 }
468 while (tout-- > 0);
469 return tout;
470 }
471
472 static int imx31_write_page (struct nand_device *nand, uint32_t page,
473 uint8_t * data, uint32_t data_size, uint8_t * oob,
474 uint32_t oob_size)
475 {
476 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
477 struct target *target = mx3_nf_info->target;
478
479 if (data_size % 2)
480 {
481 LOG_ERROR (data_block_size_err_msg, data_size);
482 return ERROR_NAND_OPERATION_FAILED;
483 }
484 if (oob_size % 2)
485 {
486 LOG_ERROR (data_block_size_err_msg, oob_size);
487 return ERROR_NAND_OPERATION_FAILED;
488 }
489 if (!data)
490 {
491 LOG_ERROR ("nothing to program");
492 return ERROR_NAND_OPERATION_FAILED;
493 }
494 {
495 /*
496 * validate target state
497 */
498 int retval;
499 retval = validate_target_state (nand);
500 if (retval != ERROR_OK)
501 {
502 return retval;
503 }
504 }
505 {
506 int retval = ERROR_OK;
507 retval |= imx31_command(nand, NAND_CMD_SEQIN);
508 retval |= imx31_address(nand, 0x00);
509 retval |= imx31_address(nand, page & 0xff);
510 retval |= imx31_address(nand, (page >> 8) & 0xff);
511 if (nand->address_cycles >= 4)
512 {
513 retval |= imx31_address (nand, (page >> 16) & 0xff);
514 if (nand->address_cycles >= 5)
515 {
516 retval |= imx31_address (nand, (page >> 24) & 0xff);
517 }
518 }
519 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
520 if (oob)
521 {
522 if (mx3_nf_info->flags.hw_ecc_enabled)
523 {
524 /*
525 * part of spare block will be overrided by hardware
526 * ECC generator
527 */
528 LOG_DEBUG
529 ("part of spare block will be overrided by hardware ECC generator");
530 }
531 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
532 oob);
533 }
534 /*
535 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
536 */
537 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
538 {
539 int poll_result;
540 poll_result = poll_for_complete_op (target, "data input");
541 if (poll_result != ERROR_OK)
542 {
543 return poll_result;
544 }
545 }
546 retval |= imx31_command (nand, NAND_CMD_PAGEPROG);
547 if (retval != ERROR_OK)
548 {
549 return retval;
550 }
551
552 /*
553 * check status register
554 */
555 {
556 uint16_t nand_status_content;
557 retval = ERROR_OK;
558 retval |= imx31_command(nand, NAND_CMD_STATUS);
559 retval |= imx31_address(nand, 0x00);
560 retval |= do_data_output(nand);
561 if (retval != ERROR_OK)
562 {
563 LOG_ERROR (get_status_register_err_msg);
564 return retval;
565 }
566 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
567 if (nand_status_content & 0x0001)
568 {
569 /*
570 * is host-big-endian correctly ??
571 */
572 return ERROR_NAND_OPERATION_FAILED;
573 }
574 }
575 }
576 return ERROR_OK;
577 }
578
579 static int imx31_read_page (struct nand_device *nand, uint32_t page,
580 uint8_t * data, uint32_t data_size, uint8_t * oob,
581 uint32_t oob_size)
582 {
583 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
584 struct target *target = mx3_nf_info->target;
585
586 if (data_size % 2)
587 {
588 LOG_ERROR (data_block_size_err_msg, data_size);
589 return ERROR_NAND_OPERATION_FAILED;
590 }
591 if (oob_size % 2)
592 {
593 LOG_ERROR (data_block_size_err_msg, oob_size);
594 return ERROR_NAND_OPERATION_FAILED;
595 }
596
597 {
598 /*
599 * validate target state
600 */
601 int retval;
602 retval = validate_target_state(nand);
603 if (retval != ERROR_OK)
604 {
605 return retval;
606 }
607 }
608 {
609 int retval = ERROR_OK;
610 retval |= imx31_command(nand, NAND_CMD_READ0);
611 retval |= imx31_address(nand, 0x00);
612 retval |= imx31_address(nand, page & 0xff);
613 retval |= imx31_address(nand, (page >> 8) & 0xff);
614 if (nand->address_cycles >= 4)
615 {
616 retval |= imx31_address(nand, (page >> 16) & 0xff);
617 if (nand->address_cycles >= 5)
618 {
619 retval |= imx31_address(nand, (page >> 24) & 0xff);
620 retval |= imx31_command(nand, NAND_CMD_READSTART);
621 }
622 }
623 retval |= do_data_output (nand);
624 if (retval != ERROR_OK)
625 {
626 return retval;
627 }
628
629 if (data)
630 {
631 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
632 data);
633 }
634 if (oob)
635 {
636 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
637 oob);
638 }
639 }
640 return ERROR_OK;
641 }
642
643 static int test_iomux_settings (struct target * target, uint32_t address,
644 uint32_t mask, const char *text)
645 {
646 uint32_t register_content;
647 target_read_u32 (target, address, &register_content);
648 if ((register_content & mask) != (0x12121212 & mask))
649 {
650 LOG_ERROR ("IOMUX for {%s} is bad", text);
651 return ERROR_FAIL;
652 }
653 return ERROR_OK;
654 }
655
656 static int initialize_nf_controller (struct nand_device *nand)
657 {
658 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
659 struct target *target = mx3_nf_info->target;
660 /*
661 * resets NAND flash controller in zero time ? I dont know.
662 */
663 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
664 {
665 uint16_t work_mode;
666 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
667 if (target->endianness == TARGET_BIG_ENDIAN)
668 {
669 work_mode |= MX3_NF_BIT_BE_EN;
670 }
671 if (mx3_nf_info->flags.hw_ecc_enabled)
672 {
673 work_mode |= MX3_NF_BIT_ECC_EN;
674 }
675 target_write_u16 (target, MX3_NF_CFG1, work_mode);
676 }
677 /*
678 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
679 */
680 target_write_u16 (target, MX3_NF_BUFCFG, 2);
681 {
682 uint16_t temp;
683 target_read_u16 (target, MX3_NF_FWP, &temp);
684 if ((temp & 0x0007) == 1)
685 {
686 LOG_ERROR ("NAND flash is tight-locked, reset needed");
687 return ERROR_FAIL;
688 }
689
690 }
691 /*
692 * unlock NAND flash for write
693 */
694 target_write_u16 (target, MX3_NF_FWP, 4);
695 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
696 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
697 /*
698 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
699 */
700 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
701 /*
702 * address of SRAM buffer
703 */
704 in_sram_address = MX3_NF_MAIN_BUFFER0;
705 sign_of_sequental_byte_read = 0;
706 return ERROR_OK;
707 }
708
709 static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
710 {
711 static uint8_t even_byte = 0;
712 /*
713 * host-big_endian ??
714 */
715 if (sign_of_sequental_byte_read == 0)
716 {
717 even_byte = 0;
718 }
719 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
720 {
721 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
722 *value = 0;
723 sign_of_sequental_byte_read = 0;
724 even_byte = 0;
725 return ERROR_NAND_OPERATION_FAILED;
726 }
727 else
728 {
729 uint16_t temp;
730 target_read_u16 (target, in_sram_address, &temp);
731 if (even_byte)
732 {
733 *value = temp >> 8;
734 even_byte = 0;
735 in_sram_address += 2;
736 }
737 else
738 {
739 *value = temp & 0xff;
740 even_byte = 1;
741 }
742 }
743 sign_of_sequental_byte_read = 1;
744 return ERROR_OK;
745 }
746
747 static int get_next_halfword_from_sram_buffer (struct target * target,
748 uint16_t * value)
749 {
750 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
751 {
752 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
753 *value = 0;
754 return ERROR_NAND_OPERATION_FAILED;
755 }
756 else
757 {
758 target_read_u16 (target, in_sram_address, value);
759 in_sram_address += 2;
760 }
761 return ERROR_OK;
762 }
763
764 static int poll_for_complete_op (struct target * target, const char *text)
765 {
766 uint16_t poll_complete_status;
767 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
768 {
769 usleep (25);
770 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
771 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
772 {
773 break;
774 }
775 }
776 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
777 {
778 LOG_ERROR ("%s sending timeout", text);
779 return ERROR_NAND_OPERATION_FAILED;
780 }
781 return ERROR_OK;
782 }
783
784 static int validate_target_state (struct nand_device *nand)
785 {
786 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
787 struct target *target = mx3_nf_info->target;
788
789 if (target->state != TARGET_HALTED)
790 {
791 LOG_ERROR (target_not_halted_err_msg);
792 return ERROR_NAND_OPERATION_FAILED;
793 }
794
795 if (mx3_nf_info->flags.target_little_endian !=
796 (target->endianness == TARGET_LITTLE_ENDIAN))
797 {
798 /*
799 * endianness changed after NAND controller probed
800 */
801 return ERROR_NAND_OPERATION_FAILED;
802 }
803 return ERROR_OK;
804 }
805
806 static int do_data_output (struct nand_device *nand)
807 {
808 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
809 struct target *target = mx3_nf_info->target;
810 switch (mx3_nf_info->fin)
811 {
812 case MX3_NF_FIN_DATAOUT:
813 /*
814 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
815 */
816 target_write_u16 (target, MX3_NF_CFG2,
817 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
818 optype));
819 {
820 int poll_result;
821 poll_result = poll_for_complete_op (target, "data output");
822 if (poll_result != ERROR_OK)
823 {
824 return poll_result;
825 }
826 }
827 mx3_nf_info->fin = MX3_NF_FIN_NONE;
828 /*
829 * ECC stuff
830 */
831 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
832 && mx3_nf_info->flags.hw_ecc_enabled)
833 {
834 uint16_t ecc_status;
835 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
836 switch (ecc_status & 0x000c)
837 {
838 case 1 << 2:
839 LOG_DEBUG
840 ("main area readed with 1 (correctable) error");
841 break;
842 case 2 << 2:
843 LOG_DEBUG
844 ("main area readed with more than 1 (incorrectable) error");
845 return ERROR_NAND_OPERATION_FAILED;
846 break;
847 }
848 switch (ecc_status & 0x0003)
849 {
850 case 1:
851 LOG_DEBUG
852 ("spare area readed with 1 (correctable) error");
853 break;
854 case 2:
855 LOG_DEBUG
856 ("main area readed with more than 1 (incorrectable) error");
857 return ERROR_NAND_OPERATION_FAILED;
858 break;
859 }
860 }
861 break;
862 case MX3_NF_FIN_NONE:
863 break;
864 }
865 return ERROR_OK;
866 }
867
868 struct nand_flash_controller imx31_nand_flash_controller = {
869 .name = "imx31",
870 .nand_device_command = &imx31_nand_device_command,
871 .init = &imx31_init,
872 .reset = &imx31_reset,
873 .command = &imx31_command,
874 .address = &imx31_address,
875 .write_data = &imx31_write_data,
876 .read_data = &imx31_read_data,
877 .write_page = &imx31_write_page,
878 .read_page = &imx31_read_page,
879 .controller_ready = &imx31_controller_ready,
880 .nand_ready = &imx31_nand_ready,
881 };
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