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Nicolas Pitre nico at cam.org don't ignore bad options passed to the "nand write...
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32 #include <inttypes.h>
33
34 #include <errno.h>
35
36 #include "nand.h"
37 #include "flash.h"
38 #include "time_support.h"
39 #include "fileio.h"
40 #include "image.h"
41
42 int nand_register_commands(struct command_context_s *cmd_ctx);
43 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53
54 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
55 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
56 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
57
58 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
59 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
60
61 /* NAND flash controller
62 */
63 extern nand_flash_controller_t lpc3180_nand_controller;
64 extern nand_flash_controller_t s3c2410_nand_controller;
65 extern nand_flash_controller_t s3c2412_nand_controller;
66 extern nand_flash_controller_t s3c2440_nand_controller;
67 extern nand_flash_controller_t s3c2443_nand_controller;
68
69 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
70
71 nand_flash_controller_t *nand_flash_controllers[] =
72 {
73 &lpc3180_nand_controller,
74 &s3c2410_nand_controller,
75 &s3c2412_nand_controller,
76 &s3c2440_nand_controller,
77 &s3c2443_nand_controller,
78 /* &boundary_scan_nand_controller, */
79 NULL
80 };
81
82 /* configured NAND devices and NAND Flash command handler */
83 nand_device_t *nand_devices = NULL;
84 static command_t *nand_cmd;
85
86 /* Chip ID list
87 *
88 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
89 * options
90 *
91 * Pagesize; 0, 256, 512
92 * 0 get this information from the extended chip ID
93 * 256 256 Byte page size
94 * 512 512 Byte page size
95 */
96 nand_info_t nand_flash_ids[] =
97 {
98 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
99 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
100 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
101 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
102 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
103 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
104 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
105 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
106 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
107 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
108
109 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
110 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
111 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
112 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
113
114 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
115 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
116 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
118
119 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
120 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
121 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
122 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
123
124 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
125 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
126 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
128
129 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
130 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
131 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
132 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
133 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
134 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136
137 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
138
139 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
140 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
141 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
142 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
143
144 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
145 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
146 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
147 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
148
149 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
150 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
151 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
152 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
153
154 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
155 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
156 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
157 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
158
159 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
160 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
161 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
162 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
163
164 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
165 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
166 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
167 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
168
169 {NULL, 0,}
170 };
171
172 /* Manufacturer ID list
173 */
174 nand_manufacturer_t nand_manuf_ids[] =
175 {
176 {0x0, "unknown"},
177 {NAND_MFR_TOSHIBA, "Toshiba"},
178 {NAND_MFR_SAMSUNG, "Samsung"},
179 {NAND_MFR_FUJITSU, "Fujitsu"},
180 {NAND_MFR_NATIONAL, "National"},
181 {NAND_MFR_RENESAS, "Renesas"},
182 {NAND_MFR_STMICRO, "ST Micro"},
183 {NAND_MFR_HYNIX, "Hynix"},
184 {0x0, NULL},
185 };
186
187 /* nand device <nand_controller> [controller options]
188 */
189 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
190 {
191 int i;
192 int retval;
193
194 if (argc < 1)
195 {
196 LOG_WARNING("incomplete flash device nand configuration");
197 return ERROR_FLASH_BANK_INVALID;
198 }
199
200 for (i = 0; nand_flash_controllers[i]; i++)
201 {
202 nand_device_t *p, *c;
203
204 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
205 {
206 /* register flash specific commands */
207 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
208 {
209 LOG_ERROR("couldn't register '%s' commands", args[0]);
210 return retval;
211 }
212
213 c = malloc(sizeof(nand_device_t));
214
215 c->controller = nand_flash_controllers[i];
216 c->controller_priv = NULL;
217 c->manufacturer = NULL;
218 c->device = NULL;
219 c->bus_width = 0;
220 c->address_cycles = 0;
221 c->page_size = 0;
222 c->use_raw = 0;
223 c->next = NULL;
224
225 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
226 {
227 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
228 free(c);
229 return ERROR_OK;
230 }
231
232 /* put NAND device in linked list */
233 if (nand_devices)
234 {
235 /* find last flash device */
236 for (p = nand_devices; p && p->next; p = p->next);
237 if (p)
238 p->next = c;
239 }
240 else
241 {
242 nand_devices = c;
243 }
244
245 return ERROR_OK;
246 }
247 }
248
249 /* no valid NAND controller was found (i.e. the configuration option,
250 * didn't match one of the compiled-in controllers)
251 */
252 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
253 LOG_ERROR("compiled-in NAND flash controllers:");
254 for (i = 0; nand_flash_controllers[i]; i++)
255 {
256 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
257 }
258
259 return ERROR_OK;
260 }
261
262 int nand_register_commands(struct command_context_s *cmd_ctx)
263 {
264 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
265
266 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
267
268 return ERROR_OK;
269 }
270
271 int nand_init(struct command_context_s *cmd_ctx)
272 {
273 if (nand_devices)
274 {
275 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
276 "list configured NAND flash devices");
277 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
278 "print info about NAND flash device <num>");
279 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
280 "identify NAND flash device <num>");
281 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
282 "check NAND flash device <num> for bad blocks [<first> <last>]");
283 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
284 "erase blocks on NAND flash device <num> <first> <last>");
285 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
286 "copy from NAND flash device <num> <offset> <length> <ram-address>");
287 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
288 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
289 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
290 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only]");
291 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
292 "raw access to NAND flash device <num> ['enable'|'disable']");
293 }
294
295 return ERROR_OK;
296 }
297
298 nand_device_t *get_nand_device_by_num(int num)
299 {
300 nand_device_t *p;
301 int i = 0;
302
303 for (p = nand_devices; p; p = p->next)
304 {
305 if (i++ == num)
306 {
307 return p;
308 }
309 }
310
311 return NULL;
312 }
313
314 int nand_build_bbt(struct nand_device_s *device, int first, int last)
315 {
316 u32 page = 0x0;
317 int i;
318 u8 *oob;
319
320 oob = malloc(6);
321
322 if ((first < 0) || (first >= device->num_blocks))
323 first = 0;
324
325 if ((last >= device->num_blocks) || (last == -1))
326 last = device->num_blocks - 1;
327
328 for (i = first; i < last; i++)
329 {
330 nand_read_page(device, page, NULL, 0, oob, 6);
331
332 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
333 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
334 ((device->page_size == 2048) && (oob[0] != 0xff))))
335 {
336 LOG_WARNING("invalid block: %i", i);
337 device->blocks[i].is_bad = 1;
338 }
339 else
340 {
341 device->blocks[i].is_bad = 0;
342 }
343
344 page += (device->erase_size / device->page_size);
345 }
346
347 return ERROR_OK;
348 }
349
350 int nand_read_status(struct nand_device_s *device, u8 *status)
351 {
352 if (!device->device)
353 return ERROR_NAND_DEVICE_NOT_PROBED;
354
355 /* Send read status command */
356 device->controller->command(device, NAND_CMD_STATUS);
357
358 alive_sleep(1);
359
360 /* read status */
361 if (device->device->options & NAND_BUSWIDTH_16)
362 {
363 u16 data;
364 device->controller->read_data(device, &data);
365 *status = data & 0xff;
366 }
367 else
368 {
369 device->controller->read_data(device, status);
370 }
371
372 return ERROR_OK;
373 }
374
375 int nand_probe(struct nand_device_s *device)
376 {
377 u8 manufacturer_id, device_id;
378 u8 id_buff[6];
379 int retval;
380 int i;
381
382 /* clear device data */
383 device->device = NULL;
384 device->manufacturer = NULL;
385
386 /* clear device parameters */
387 device->bus_width = 0;
388 device->address_cycles = 0;
389 device->page_size = 0;
390 device->erase_size = 0;
391
392 /* initialize controller (device parameters are zero, use controller default) */
393 if ((retval = device->controller->init(device) != ERROR_OK))
394 {
395 switch (retval)
396 {
397 case ERROR_NAND_OPERATION_FAILED:
398 LOG_DEBUG("controller initialization failed");
399 return ERROR_NAND_OPERATION_FAILED;
400 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
401 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
402 return ERROR_NAND_OPERATION_FAILED;
403 default:
404 LOG_ERROR("BUG: unknown controller initialization failure");
405 return ERROR_NAND_OPERATION_FAILED;
406 }
407 }
408
409 device->controller->command(device, NAND_CMD_RESET);
410 device->controller->reset(device);
411
412 device->controller->command(device, NAND_CMD_READID);
413 device->controller->address(device, 0x0);
414
415 if (device->bus_width == 8)
416 {
417 device->controller->read_data(device, &manufacturer_id);
418 device->controller->read_data(device, &device_id);
419 }
420 else
421 {
422 u16 data_buf;
423 device->controller->read_data(device, &data_buf);
424 manufacturer_id = data_buf & 0xff;
425 device->controller->read_data(device, &data_buf);
426 device_id = data_buf & 0xff;
427 }
428
429 for (i = 0; nand_flash_ids[i].name; i++)
430 {
431 if (nand_flash_ids[i].id == device_id)
432 {
433 device->device = &nand_flash_ids[i];
434 break;
435 }
436 }
437
438 for (i = 0; nand_manuf_ids[i].name; i++)
439 {
440 if (nand_manuf_ids[i].id == manufacturer_id)
441 {
442 device->manufacturer = &nand_manuf_ids[i];
443 break;
444 }
445 }
446
447 if (!device->manufacturer)
448 {
449 device->manufacturer = &nand_manuf_ids[0];
450 device->manufacturer->id = manufacturer_id;
451 }
452
453 if (!device->device)
454 {
455 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
456 manufacturer_id, device_id);
457 return ERROR_NAND_OPERATION_FAILED;
458 }
459
460 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
461
462 /* initialize device parameters */
463
464 /* bus width */
465 if (device->device->options & NAND_BUSWIDTH_16)
466 device->bus_width = 16;
467 else
468 device->bus_width = 8;
469
470 /* Do we need extended device probe information? */
471 if (device->device->page_size == 0 ||
472 device->device->erase_size == 0)
473 {
474 if (device->bus_width == 8)
475 {
476 device->controller->read_data(device, id_buff+3);
477 device->controller->read_data(device, id_buff+4);
478 device->controller->read_data(device, id_buff+5);
479 }
480 else
481 {
482 u16 data_buf;
483
484 device->controller->read_data(device, &data_buf);
485 id_buff[3] = data_buf;
486
487 device->controller->read_data(device, &data_buf);
488 id_buff[4] = data_buf;
489
490 device->controller->read_data(device, &data_buf);
491 id_buff[5] = data_buf >> 8;
492 }
493 }
494
495 /* page size */
496 if (device->device->page_size == 0)
497 {
498 device->page_size = 1 << (10 + (id_buff[4] & 3));
499 }
500 else if (device->device->page_size == 256)
501 {
502 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
503 return ERROR_NAND_OPERATION_FAILED;
504 }
505 else
506 {
507 device->page_size = device->device->page_size;
508 }
509
510 /* number of address cycles */
511 if (device->page_size <= 512)
512 {
513 /* small page devices */
514 if (device->device->chip_size <= 32)
515 device->address_cycles = 3;
516 else if (device->device->chip_size <= 8*1024)
517 device->address_cycles = 4;
518 else
519 {
520 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
521 device->address_cycles = 5;
522 }
523 }
524 else
525 {
526 /* large page devices */
527 if (device->device->chip_size <= 128)
528 device->address_cycles = 4;
529 else if (device->device->chip_size <= 32*1024)
530 device->address_cycles = 5;
531 else
532 {
533 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
534 device->address_cycles = 6;
535 }
536 }
537
538 /* erase size */
539 if (device->device->erase_size == 0)
540 {
541 switch ((id_buff[4] >> 4) & 3) {
542 case 0:
543 device->erase_size = 64 << 10;
544 break;
545 case 1:
546 device->erase_size = 128 << 10;
547 break;
548 case 2:
549 device->erase_size = 256 << 10;
550 break;
551 case 3:
552 device->erase_size =512 << 10;
553 break;
554 }
555 }
556 else
557 {
558 device->erase_size = device->device->erase_size;
559 }
560
561 /* initialize controller, but leave parameters at the controllers default */
562 if ((retval = device->controller->init(device) != ERROR_OK))
563 {
564 switch (retval)
565 {
566 case ERROR_NAND_OPERATION_FAILED:
567 LOG_DEBUG("controller initialization failed");
568 return ERROR_NAND_OPERATION_FAILED;
569 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
570 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
571 device->bus_width, device->address_cycles, device->page_size);
572 return ERROR_NAND_OPERATION_FAILED;
573 default:
574 LOG_ERROR("BUG: unknown controller initialization failure");
575 return ERROR_NAND_OPERATION_FAILED;
576 }
577 }
578
579 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
580 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
581
582 for (i = 0; i < device->num_blocks; i++)
583 {
584 device->blocks[i].size = device->erase_size;
585 device->blocks[i].offset = i * device->erase_size;
586 device->blocks[i].is_erased = -1;
587 device->blocks[i].is_bad = -1;
588 }
589
590 return ERROR_OK;
591 }
592
593 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
594 {
595 int i;
596 u32 page;
597 u8 status;
598 int retval;
599
600 if (!device->device)
601 return ERROR_NAND_DEVICE_NOT_PROBED;
602
603 if ((first_block < 0) || (last_block > device->num_blocks))
604 return ERROR_INVALID_ARGUMENTS;
605
606 /* make sure we know if a block is bad before erasing it */
607 for (i = first_block; i <= last_block; i++)
608 {
609 if (device->blocks[i].is_bad == -1)
610 {
611 nand_build_bbt(device, i, last_block);
612 break;
613 }
614 }
615
616 for (i = first_block; i <= last_block; i++)
617 {
618 /* Send erase setup command */
619 device->controller->command(device, NAND_CMD_ERASE1);
620
621 page = i * (device->erase_size / device->page_size);
622
623 /* Send page address */
624 if (device->page_size <= 512)
625 {
626 /* row */
627 device->controller->address(device, page & 0xff);
628 device->controller->address(device, (page >> 8) & 0xff);
629
630 /* 3rd cycle only on devices with more than 32 MiB */
631 if (device->address_cycles >= 4)
632 device->controller->address(device, (page >> 16) & 0xff);
633
634 /* 4th cycle only on devices with more than 8 GiB */
635 if (device->address_cycles >= 5)
636 device->controller->address(device, (page >> 24) & 0xff);
637 }
638 else
639 {
640 /* row */
641 device->controller->address(device, page & 0xff);
642 device->controller->address(device, (page >> 8) & 0xff);
643
644 /* 3rd cycle only on devices with more than 128 MiB */
645 if (device->address_cycles >= 5)
646 device->controller->address(device, (page >> 16) & 0xff);
647 }
648
649 /* Send erase confirm command */
650 device->controller->command(device, NAND_CMD_ERASE2);
651
652 if (!device->controller->nand_ready(device, 1000))
653 {
654 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
655 return ERROR_NAND_OPERATION_TIMEOUT;
656 }
657
658 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
659 {
660 LOG_ERROR("couldn't read status");
661 return ERROR_NAND_OPERATION_FAILED;
662 }
663
664 if (status & 0x1)
665 {
666 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
667 return ERROR_NAND_OPERATION_FAILED;
668 }
669 }
670
671 return ERROR_OK;
672 }
673
674 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
675 {
676 u8 *page;
677
678 if (!device->device)
679 return ERROR_NAND_DEVICE_NOT_PROBED;
680
681 if (address % device->page_size)
682 {
683 LOG_ERROR("reads need to be page aligned");
684 return ERROR_NAND_OPERATION_FAILED;
685 }
686
687 page = malloc(device->page_size);
688
689 while (data_size > 0 )
690 {
691 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
692 u32 page_address;
693
694
695 page_address = address / device->page_size;
696
697 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
698
699 memcpy(data, page, thisrun_size);
700
701 address += thisrun_size;
702 data += thisrun_size;
703 data_size -= thisrun_size;
704 }
705
706 free(page);
707
708 return ERROR_OK;
709 }
710
711 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
712 {
713 u8 *page;
714
715 if (!device->device)
716 return ERROR_NAND_DEVICE_NOT_PROBED;
717
718 if (address % device->page_size)
719 {
720 LOG_ERROR("writes need to be page aligned");
721 return ERROR_NAND_OPERATION_FAILED;
722 }
723
724 page = malloc(device->page_size);
725
726 while (data_size > 0 )
727 {
728 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
729 u32 page_address;
730
731 memset(page, 0xff, device->page_size);
732 memcpy(page, data, thisrun_size);
733
734 page_address = address / device->page_size;
735
736 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
737
738 address += thisrun_size;
739 data += thisrun_size;
740 data_size -= thisrun_size;
741 }
742
743 free(page);
744
745 return ERROR_OK;
746 }
747
748 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
749 {
750 if (!device->device)
751 return ERROR_NAND_DEVICE_NOT_PROBED;
752
753 if (device->use_raw || device->controller->write_page == NULL)
754 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
755 else
756 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
757 }
758
759 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
760 {
761 if (!device->device)
762 return ERROR_NAND_DEVICE_NOT_PROBED;
763
764 if (device->use_raw || device->controller->read_page == NULL)
765 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
766 else
767 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
768 }
769
770 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
771 {
772 int i;
773
774 if (!device->device)
775 return ERROR_NAND_DEVICE_NOT_PROBED;
776
777 if (device->page_size <= 512)
778 {
779 /* small page device */
780 if (data)
781 device->controller->command(device, NAND_CMD_READ0);
782 else
783 device->controller->command(device, NAND_CMD_READOOB);
784
785 /* column (always 0, we start at the beginning of a page/OOB area) */
786 device->controller->address(device, 0x0);
787
788 /* row */
789 device->controller->address(device, page & 0xff);
790 device->controller->address(device, (page >> 8) & 0xff);
791
792 /* 4th cycle only on devices with more than 32 MiB */
793 if (device->address_cycles >= 4)
794 device->controller->address(device, (page >> 16) & 0xff);
795
796 /* 5th cycle only on devices with more than 8 GiB */
797 if (device->address_cycles >= 5)
798 device->controller->address(device, (page >> 24) & 0xff);
799 }
800 else
801 {
802 /* large page device */
803 device->controller->command(device, NAND_CMD_READ0);
804
805 /* column (0 when we start at the beginning of a page,
806 * or 2048 for the beginning of OOB area)
807 */
808 device->controller->address(device, 0x0);
809 if (data)
810 device->controller->address(device, 0x0);
811 else
812 device->controller->address(device, 0x8);
813
814 /* row */
815 device->controller->address(device, page & 0xff);
816 device->controller->address(device, (page >> 8) & 0xff);
817
818 /* 5th cycle only on devices with more than 128 MiB */
819 if (device->address_cycles >= 5)
820 device->controller->address(device, (page >> 16) & 0xff);
821
822 /* large page devices need a start command */
823 device->controller->command(device, NAND_CMD_READSTART);
824 }
825
826 if (!device->controller->nand_ready(device, 100))
827 return ERROR_NAND_OPERATION_TIMEOUT;
828
829 if (data)
830 {
831 if (device->controller->read_block_data != NULL)
832 (device->controller->read_block_data)(device, data, data_size);
833 else
834 {
835 for (i = 0; i < data_size;)
836 {
837 if (device->device->options & NAND_BUSWIDTH_16)
838 {
839 device->controller->read_data(device, data);
840 data += 2;
841 i += 2;
842 }
843 else
844 {
845 device->controller->read_data(device, data);
846 data += 1;
847 i += 1;
848 }
849 }
850 }
851 }
852
853 if (oob)
854 {
855 if (device->controller->read_block_data != NULL)
856 (device->controller->read_block_data)(device, oob, oob_size);
857 else
858 {
859 for (i = 0; i < oob_size;)
860 {
861 if (device->device->options & NAND_BUSWIDTH_16)
862 {
863 device->controller->read_data(device, oob);
864 oob += 2;
865 i += 2;
866 }
867 else
868 {
869 device->controller->read_data(device, oob);
870 oob += 1;
871 i += 1;
872 }
873 }
874 }
875 }
876
877 return ERROR_OK;
878 }
879
880 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
881 {
882 int i;
883 int retval;
884 u8 status;
885
886 if (!device->device)
887 return ERROR_NAND_DEVICE_NOT_PROBED;
888
889 device->controller->command(device, NAND_CMD_SEQIN);
890
891 if (device->page_size <= 512)
892 {
893 /* column (always 0, we start at the beginning of a page/OOB area) */
894 device->controller->address(device, 0x0);
895
896 /* row */
897 device->controller->address(device, page & 0xff);
898 device->controller->address(device, (page >> 8) & 0xff);
899
900 /* 4th cycle only on devices with more than 32 MiB */
901 if (device->address_cycles >= 4)
902 device->controller->address(device, (page >> 16) & 0xff);
903
904 /* 5th cycle only on devices with more than 8 GiB */
905 if (device->address_cycles >= 5)
906 device->controller->address(device, (page >> 24) & 0xff);
907 }
908 else
909 {
910 /* column (0 when we start at the beginning of a page,
911 * or 2048 for the beginning of OOB area)
912 */
913 device->controller->address(device, 0x0);
914 if (data)
915 device->controller->address(device, 0x0);
916 else
917 device->controller->address(device, 0x8);
918
919 /* row */
920 device->controller->address(device, page & 0xff);
921 device->controller->address(device, (page >> 8) & 0xff);
922
923 /* 5th cycle only on devices with more than 128 MiB */
924 if (device->address_cycles >= 5)
925 device->controller->address(device, (page >> 16) & 0xff);
926 }
927
928 if (data)
929 {
930 if (device->controller->write_block_data != NULL)
931 (device->controller->write_block_data)(device, data, data_size);
932 else
933 {
934 for (i = 0; i < data_size;)
935 {
936 if (device->device->options & NAND_BUSWIDTH_16)
937 {
938 u16 data_buf = le_to_h_u16(data);
939 device->controller->write_data(device, data_buf);
940 data += 2;
941 i += 2;
942 }
943 else
944 {
945 device->controller->write_data(device, *data);
946 data += 1;
947 i += 1;
948 }
949 }
950 }
951 }
952
953 if (oob)
954 {
955 if (device->controller->write_block_data != NULL)
956 (device->controller->write_block_data)(device, oob, oob_size);
957 else
958 {
959 for (i = 0; i < oob_size;)
960 {
961 if (device->device->options & NAND_BUSWIDTH_16)
962 {
963 u16 oob_buf = le_to_h_u16(data);
964 device->controller->write_data(device, oob_buf);
965 oob += 2;
966 i += 2;
967 }
968 else
969 {
970 device->controller->write_data(device, *oob);
971 oob += 1;
972 i += 1;
973 }
974 }
975 }
976 }
977
978 device->controller->command(device, NAND_CMD_PAGEPROG);
979
980 if (!device->controller->nand_ready(device, 100))
981 return ERROR_NAND_OPERATION_TIMEOUT;
982
983 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
984 {
985 LOG_ERROR("couldn't read status");
986 return ERROR_NAND_OPERATION_FAILED;
987 }
988
989 if (status & NAND_STATUS_FAIL)
990 {
991 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
992 return ERROR_NAND_OPERATION_FAILED;
993 }
994
995 return ERROR_OK;
996 }
997
998 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
999 {
1000 nand_device_t *p;
1001 int i = 0;
1002
1003 if (!nand_devices)
1004 {
1005 command_print(cmd_ctx, "no NAND flash devices configured");
1006 return ERROR_OK;
1007 }
1008
1009 for (p = nand_devices; p; p = p->next)
1010 {
1011 if (p->device)
1012 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1013 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1014 else
1015 command_print(cmd_ctx, "#%i: not probed");
1016 }
1017
1018 return ERROR_OK;
1019 }
1020
1021 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1022 {
1023 nand_device_t *p;
1024 int i = 0;
1025 int j = 0;
1026 int first = -1;
1027 int last = -1;
1028
1029 if ((argc < 1) || (argc > 3))
1030 {
1031 return ERROR_COMMAND_SYNTAX_ERROR;
1032
1033 }
1034
1035 if (argc == 2)
1036 {
1037 first = last = strtoul(args[1], NULL, 0);
1038 }
1039 else if (argc == 3)
1040 {
1041 first = strtoul(args[1], NULL, 0);
1042 last = strtoul(args[2], NULL, 0);
1043 }
1044
1045 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1046 if (p)
1047 {
1048 if (p->device)
1049 {
1050 if (first >= p->num_blocks)
1051 first = p->num_blocks - 1;
1052
1053 if (last >= p->num_blocks)
1054 last = p->num_blocks - 1;
1055
1056 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1057 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1058
1059 for (j = first; j <= last; j++)
1060 {
1061 char *erase_state, *bad_state;
1062
1063 if (p->blocks[j].is_erased == 0)
1064 erase_state = "not erased";
1065 else if (p->blocks[j].is_erased == 1)
1066 erase_state = "erased";
1067 else
1068 erase_state = "erase state unknown";
1069
1070 if (p->blocks[j].is_bad == 0)
1071 bad_state = "";
1072 else if (p->blocks[j].is_bad == 1)
1073 bad_state = " (marked bad)";
1074 else
1075 bad_state = " (block condition unknown)";
1076
1077 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1078 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1079 erase_state, bad_state);
1080 }
1081 }
1082 else
1083 {
1084 command_print(cmd_ctx, "#%i: not probed");
1085 }
1086 }
1087
1088 return ERROR_OK;
1089 }
1090
1091 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1092 {
1093 nand_device_t *p;
1094 int retval;
1095
1096 if (argc != 1)
1097 {
1098 return ERROR_COMMAND_SYNTAX_ERROR;
1099 }
1100
1101 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1102 if (p)
1103 {
1104 if ((retval = nand_probe(p)) == ERROR_OK)
1105 {
1106 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1107 }
1108 else if (retval == ERROR_NAND_OPERATION_FAILED)
1109 {
1110 command_print(cmd_ctx, "probing failed for NAND flash device");
1111 }
1112 else
1113 {
1114 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1115 }
1116 }
1117 else
1118 {
1119 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1120 }
1121
1122 return ERROR_OK;
1123 }
1124
1125 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1126 {
1127 nand_device_t *p;
1128 int retval;
1129
1130 if (argc != 3)
1131 {
1132 return ERROR_COMMAND_SYNTAX_ERROR;
1133
1134 }
1135
1136 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1137 if (p)
1138 {
1139 int first = strtoul(args[1], NULL, 0);
1140 int last = strtoul(args[2], NULL, 0);
1141
1142 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1143 {
1144 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1145 }
1146 else if (retval == ERROR_NAND_OPERATION_FAILED)
1147 {
1148 command_print(cmd_ctx, "erase failed");
1149 }
1150 else
1151 {
1152 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1153 }
1154 }
1155 else
1156 {
1157 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1158 }
1159
1160 return ERROR_OK;
1161 }
1162
1163 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1164 {
1165 nand_device_t *p;
1166 int retval;
1167 int first = -1;
1168 int last = -1;
1169
1170 if ((argc < 1) || (argc > 3) || (argc == 2))
1171 {
1172 return ERROR_COMMAND_SYNTAX_ERROR;
1173
1174 }
1175
1176 if (argc == 3)
1177 {
1178 first = strtoul(args[1], NULL, 0);
1179 last = strtoul(args[2], NULL, 0);
1180 }
1181
1182 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1183 if (p)
1184 {
1185 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1186 {
1187 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1188 }
1189 else if (retval == ERROR_NAND_OPERATION_FAILED)
1190 {
1191 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1192 }
1193 else
1194 {
1195 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1196 }
1197 }
1198 else
1199 {
1200 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1201 }
1202
1203 return ERROR_OK;
1204 }
1205
1206 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1207 {
1208 nand_device_t *p;
1209
1210 if (argc != 4)
1211 {
1212 return ERROR_COMMAND_SYNTAX_ERROR;
1213
1214 }
1215
1216 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1217 if (p)
1218 {
1219
1220 }
1221 else
1222 {
1223 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1224 }
1225
1226 return ERROR_OK;
1227 }
1228
1229 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1230 {
1231 u32 offset;
1232 u32 binary_size;
1233 u32 buf_cnt;
1234 enum oob_formats oob_format = NAND_OOB_NONE;
1235
1236 fileio_t fileio;
1237
1238 duration_t duration;
1239 char *duration_text;
1240
1241 nand_device_t *p;
1242
1243 if (argc < 3)
1244 {
1245 return ERROR_COMMAND_SYNTAX_ERROR;
1246
1247 }
1248
1249 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1250 if (p)
1251 {
1252 u8 *page = NULL;
1253 u32 page_size = 0;
1254 u8 *oob = NULL;
1255 u32 oob_size = 0;
1256
1257 offset = strtoul(args[2], NULL, 0);
1258
1259 if (argc > 3)
1260 {
1261 int i;
1262 for (i = 3; i < argc; i++)
1263 {
1264 if (!strcmp(args[i], "oob_raw"))
1265 oob_format |= NAND_OOB_RAW;
1266 else if (!strcmp(args[i], "oob_only"))
1267 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1268 else
1269 {
1270 command_print(cmd_ctx, "unknown option: %s", args[i]);
1271 return ERROR_COMMAND_SYNTAX_ERROR;
1272 }
1273 }
1274 }
1275
1276 duration_start_measure(&duration);
1277
1278 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1279 {
1280 return ERROR_OK;
1281 }
1282
1283 buf_cnt = binary_size = fileio.size;
1284
1285 if (!(oob_format & NAND_OOB_ONLY))
1286 {
1287 page_size = p->page_size;
1288 page = malloc(p->page_size);
1289 }
1290
1291 if (oob_format & NAND_OOB_RAW)
1292 {
1293 if (p->page_size == 512)
1294 oob_size = 16;
1295 else if (p->page_size == 2048)
1296 oob_size = 64;
1297 oob = malloc(oob_size);
1298 }
1299
1300 if (offset % p->page_size)
1301 {
1302 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1303 fileio_close(&fileio);
1304 free(oob);
1305 free(page);
1306 return ERROR_OK;
1307 }
1308
1309 while (buf_cnt > 0)
1310 {
1311 u32 size_read;
1312
1313 if (NULL != page)
1314 {
1315 fileio_read(&fileio, page_size, page, &size_read);
1316 buf_cnt -= size_read;
1317 if (size_read < page_size)
1318 {
1319 memset(page + size_read, 0xff, page_size - size_read);
1320 }
1321 }
1322
1323 if (NULL != oob)
1324 {
1325 fileio_read(&fileio, oob_size, oob, &size_read);
1326 buf_cnt -= size_read;
1327 if (size_read < oob_size)
1328 {
1329 memset(oob + size_read, 0xff, oob_size - size_read);
1330 }
1331 }
1332
1333 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1334 {
1335 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1336 args[1], args[0], offset);
1337
1338 fileio_close(&fileio);
1339 free(oob);
1340 free(page);
1341
1342 return ERROR_OK;
1343 }
1344 offset += page_size;
1345 }
1346
1347 fileio_close(&fileio);
1348 free(oob);
1349 free(page);
1350 oob = NULL;
1351 page = NULL;
1352 duration_stop_measure(&duration, &duration_text);
1353 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1354 args[1], args[0], offset, duration_text);
1355 free(duration_text);
1356 duration_text = NULL;
1357 }
1358 else
1359 {
1360 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1361 }
1362
1363 return ERROR_OK;
1364 }
1365
1366 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1367 {
1368 nand_device_t *p;
1369
1370 if (argc < 4)
1371 {
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1373 }
1374
1375 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1376 if (p)
1377 {
1378 if (p->device)
1379 {
1380 fileio_t fileio;
1381 duration_t duration;
1382 char *duration_text;
1383 int retval;
1384
1385 u8 *page = NULL;
1386 u32 page_size = 0;
1387 u8 *oob = NULL;
1388 u32 oob_size = 0;
1389 u32 address = strtoul(args[2], NULL, 0);
1390 u32 size = strtoul(args[3], NULL, 0);
1391 u32 bytes_done = 0;
1392 enum oob_formats oob_format = NAND_OOB_NONE;
1393
1394 if (argc > 4)
1395 {
1396 int i;
1397 for (i = 4; i < argc; i++)
1398 {
1399 if (!strcmp(args[i], "oob_raw"))
1400 oob_format |= NAND_OOB_RAW;
1401 else if (!strcmp(args[i], "oob_only"))
1402 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1403 else
1404 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1405 }
1406 }
1407
1408 if ((address % p->page_size) || (size % p->page_size))
1409 {
1410 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1411 return ERROR_OK;
1412 }
1413
1414 if (!(oob_format & NAND_OOB_ONLY))
1415 {
1416 page_size = p->page_size;
1417 page = malloc(p->page_size);
1418 }
1419
1420 if (oob_format & NAND_OOB_RAW)
1421 {
1422 if (p->page_size == 512)
1423 oob_size = 16;
1424 else if (p->page_size == 2048)
1425 oob_size = 64;
1426 oob = malloc(oob_size);
1427 }
1428
1429 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1430 {
1431 return ERROR_OK;
1432 }
1433
1434 duration_start_measure(&duration);
1435
1436 while (size > 0)
1437 {
1438 u32 size_written;
1439 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1440 {
1441 command_print(cmd_ctx, "reading NAND flash page failed");
1442 free(page);
1443 free(oob);
1444 fileio_close(&fileio);
1445 return ERROR_OK;
1446 }
1447
1448 if (NULL != page)
1449 {
1450 fileio_write(&fileio, page_size, page, &size_written);
1451 bytes_done += page_size;
1452 }
1453
1454 if (NULL != oob)
1455 {
1456 fileio_write(&fileio, oob_size, oob, &size_written);
1457 bytes_done += oob_size;
1458 }
1459
1460 size -= p->page_size;
1461 address += p->page_size;
1462 }
1463
1464 free(page);
1465 page = NULL;
1466 free(oob);
1467 oob = NULL;
1468 fileio_close(&fileio);
1469
1470 duration_stop_measure(&duration, &duration_text);
1471 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1472 free(duration_text);
1473 duration_text = NULL;
1474 }
1475 else
1476 {
1477 command_print(cmd_ctx, "#%i: not probed");
1478 }
1479 }
1480 else
1481 {
1482 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1483 }
1484
1485 return ERROR_OK;
1486 }
1487
1488 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1489 {
1490 nand_device_t *p;
1491
1492 if ((argc < 1) || (argc > 2))
1493 {
1494 return ERROR_COMMAND_SYNTAX_ERROR;
1495 }
1496
1497 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1498 if (p)
1499 {
1500 if (p->device)
1501 {
1502 if (argc == 2)
1503 {
1504 if (strcmp("enable", args[1]) == 0)
1505 {
1506 p->use_raw = 1;
1507 }
1508 else if (strcmp("disable", args[1]) == 0)
1509 {
1510 p->use_raw = 0;
1511 }
1512 else
1513 {
1514 return ERROR_COMMAND_SYNTAX_ERROR;
1515 }
1516 }
1517
1518 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1519 }
1520 else
1521 {
1522 command_print(cmd_ctx, "#%i: not probed");
1523 }
1524 }
1525 else
1526 {
1527 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1528 }
1529
1530 return ERROR_OK;
1531 }
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