Code Review / openocd.git / blob
? search:


8efed037c6073153fea0a4edf8ab0ee8340b8fbe
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 #include <inttypes.h>
32
33
34 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42
43 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
46 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
47
48 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
49
50 /* NAND flash controller
51 */
52 extern nand_flash_controller_t lpc3180_nand_controller;
53 extern nand_flash_controller_t orion_nand_controller;
54 extern nand_flash_controller_t s3c2410_nand_controller;
55 extern nand_flash_controller_t s3c2412_nand_controller;
56 extern nand_flash_controller_t s3c2440_nand_controller;
57 extern nand_flash_controller_t s3c2443_nand_controller;
58
59 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
60
61 static nand_flash_controller_t *nand_flash_controllers[] =
62 {
63 &lpc3180_nand_controller,
64 &orion_nand_controller,
65 &s3c2410_nand_controller,
66 &s3c2412_nand_controller,
67 &s3c2440_nand_controller,
68 &s3c2443_nand_controller,
69 /* &boundary_scan_nand_controller, */
70 NULL
71 };
72
73 /* configured NAND devices and NAND Flash command handler */
74 static nand_device_t *nand_devices = NULL;
75 static command_t *nand_cmd;
76
77 /* Chip ID list
78 *
79 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
80 * options
81 *
82 * Pagesize; 0, 256, 512
83 * 0 get this information from the extended chip ID
84 * 256 256 Byte page size
85 * 512 512 Byte page size
86 */
87 static nand_info_t nand_flash_ids[] =
88 {
89 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
90 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
91 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
92 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
94 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
95 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
98 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
99
100 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
101 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
103 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104
105 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
106 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
107 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
108 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
109
110 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
111 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
112 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
113 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
114
115 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
116 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
117 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
119
120 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
121 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
122 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
125 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127
128 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
129
130 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
131 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
132 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
133 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
134
135 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
136 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
137 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
138 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
139
140 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
141 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
142 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
143 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
144
145 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
146 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
147 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
148 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
149
150 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
151 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
152 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
153 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
154
155 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
156 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
157 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
158 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
159
160 {NULL, 0, 0, 0, 0, 0 }
161 };
162
163 /* Manufacturer ID list
164 */
165 static nand_manufacturer_t nand_manuf_ids[] =
166 {
167 {0x0, "unknown"},
168 {NAND_MFR_TOSHIBA, "Toshiba"},
169 {NAND_MFR_SAMSUNG, "Samsung"},
170 {NAND_MFR_FUJITSU, "Fujitsu"},
171 {NAND_MFR_NATIONAL, "National"},
172 {NAND_MFR_RENESAS, "Renesas"},
173 {NAND_MFR_STMICRO, "ST Micro"},
174 {NAND_MFR_HYNIX, "Hynix"},
175 {0x0, NULL},
176 };
177
178 /*
179 * Define default oob placement schemes for large and small page devices
180 */
181
182 #if 0
183 static nand_ecclayout_t nand_oob_8 = {
184 .eccbytes = 3,
185 .eccpos = {0, 1, 2},
186 .oobfree = {
187 {.offset = 3,
188 .length = 2},
189 {.offset = 6,
190 .length = 2}}
191 };
192 #endif
193
194 static nand_ecclayout_t nand_oob_16 = {
195 .eccbytes = 6,
196 .eccpos = {0, 1, 2, 3, 6, 7},
197 .oobfree = {
198 {.offset = 8,
199 . length = 8}}
200 };
201
202 static nand_ecclayout_t nand_oob_64 = {
203 .eccbytes = 24,
204 .eccpos = {
205 40, 41, 42, 43, 44, 45, 46, 47,
206 48, 49, 50, 51, 52, 53, 54, 55,
207 56, 57, 58, 59, 60, 61, 62, 63},
208 .oobfree = {
209 {.offset = 2,
210 .length = 38}}
211 };
212
213 /* nand device <nand_controller> [controller options]
214 */
215 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
216 {
217 int i;
218 int retval;
219
220 if (argc < 1)
221 {
222 LOG_WARNING("incomplete flash device nand configuration");
223 return ERROR_FLASH_BANK_INVALID;
224 }
225
226 for (i = 0; nand_flash_controllers[i]; i++)
227 {
228 nand_device_t *p, *c;
229
230 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
231 {
232 /* register flash specific commands */
233 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
234 {
235 LOG_ERROR("couldn't register '%s' commands", args[0]);
236 return retval;
237 }
238
239 c = malloc(sizeof(nand_device_t));
240
241 c->controller = nand_flash_controllers[i];
242 c->controller_priv = NULL;
243 c->manufacturer = NULL;
244 c->device = NULL;
245 c->bus_width = 0;
246 c->address_cycles = 0;
247 c->page_size = 0;
248 c->use_raw = 0;
249 c->next = NULL;
250
251 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
252 {
253 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
254 free(c);
255 return ERROR_OK;
256 }
257
258 /* put NAND device in linked list */
259 if (nand_devices)
260 {
261 /* find last flash device */
262 for (p = nand_devices; p && p->next; p = p->next);
263 if (p)
264 p->next = c;
265 }
266 else
267 {
268 nand_devices = c;
269 }
270
271 return ERROR_OK;
272 }
273 }
274
275 /* no valid NAND controller was found (i.e. the configuration option,
276 * didn't match one of the compiled-in controllers)
277 */
278 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
279 LOG_ERROR("compiled-in NAND flash controllers:");
280 for (i = 0; nand_flash_controllers[i]; i++)
281 {
282 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
283 }
284
285 return ERROR_OK;
286 }
287
288 int nand_register_commands(struct command_context_s *cmd_ctx)
289 {
290 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
291
292 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
293
294 return ERROR_OK;
295 }
296
297 int nand_init(struct command_context_s *cmd_ctx)
298 {
299 if (nand_devices)
300 {
301 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
302 "list configured NAND flash devices");
303 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
304 "print info about NAND flash device <num>");
305 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
306 "identify NAND flash device <num>");
307 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
308 "check NAND flash device <num> for bad blocks [<first> <last>]");
309 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
310 "erase blocks on NAND flash device <num> <first> <last>");
311 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
312 "copy from NAND flash device <num> <offset> <length> <ram-address>");
313 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
314 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
315 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
316 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc]");
317 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
318 "raw access to NAND flash device <num> ['enable'|'disable']");
319 }
320
321 return ERROR_OK;
322 }
323
324 nand_device_t *get_nand_device_by_num(int num)
325 {
326 nand_device_t *p;
327 int i = 0;
328
329 for (p = nand_devices; p; p = p->next)
330 {
331 if (i++ == num)
332 {
333 return p;
334 }
335 }
336
337 return NULL;
338 }
339
340 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
341 {
342 u32 page = 0x0;
343 int i;
344 u8 oob[6];
345
346 if ((first < 0) || (first >= device->num_blocks))
347 first = 0;
348
349 if ((last >= device->num_blocks) || (last == -1))
350 last = device->num_blocks - 1;
351
352 for (i = first; i < last; i++)
353 {
354 nand_read_page(device, page, NULL, 0, oob, 6);
355
356 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
357 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
358 ((device->page_size == 2048) && (oob[0] != 0xff))))
359 {
360 LOG_WARNING("invalid block: %i", i);
361 device->blocks[i].is_bad = 1;
362 }
363 else
364 {
365 device->blocks[i].is_bad = 0;
366 }
367
368 page += (device->erase_size / device->page_size);
369 }
370
371 return ERROR_OK;
372 }
373
374 int nand_read_status(struct nand_device_s *device, u8 *status)
375 {
376 if (!device->device)
377 return ERROR_NAND_DEVICE_NOT_PROBED;
378
379 /* Send read status command */
380 device->controller->command(device, NAND_CMD_STATUS);
381
382 alive_sleep(1);
383
384 /* read status */
385 if (device->device->options & NAND_BUSWIDTH_16)
386 {
387 u16 data;
388 device->controller->read_data(device, &data);
389 *status = data & 0xff;
390 }
391 else
392 {
393 device->controller->read_data(device, status);
394 }
395
396 return ERROR_OK;
397 }
398
399 static int nand_poll_ready(struct nand_device_s *device, int timeout)
400 {
401 u8 status;
402
403 device->controller->command(device, NAND_CMD_STATUS);
404 do {
405 if (device->device->options & NAND_BUSWIDTH_16) {
406 u16 data;
407 device->controller->read_data(device, &data);
408 status = data & 0xff;
409 } else {
410 device->controller->read_data(device, &status);
411 }
412 if (status & NAND_STATUS_READY)
413 break;
414 alive_sleep(1);
415 } while (timeout--);
416
417 return (status & NAND_STATUS_READY) != 0;
418 }
419
420 int nand_probe(struct nand_device_s *device)
421 {
422 u8 manufacturer_id, device_id;
423 u8 id_buff[6];
424 int retval;
425 int i;
426
427 /* clear device data */
428 device->device = NULL;
429 device->manufacturer = NULL;
430
431 /* clear device parameters */
432 device->bus_width = 0;
433 device->address_cycles = 0;
434 device->page_size = 0;
435 device->erase_size = 0;
436
437 /* initialize controller (device parameters are zero, use controller default) */
438 if ((retval = device->controller->init(device) != ERROR_OK))
439 {
440 switch (retval)
441 {
442 case ERROR_NAND_OPERATION_FAILED:
443 LOG_DEBUG("controller initialization failed");
444 return ERROR_NAND_OPERATION_FAILED;
445 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
446 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
447 return ERROR_NAND_OPERATION_FAILED;
448 default:
449 LOG_ERROR("BUG: unknown controller initialization failure");
450 return ERROR_NAND_OPERATION_FAILED;
451 }
452 }
453
454 device->controller->command(device, NAND_CMD_RESET);
455 device->controller->reset(device);
456
457 device->controller->command(device, NAND_CMD_READID);
458 device->controller->address(device, 0x0);
459
460 if (device->bus_width == 8)
461 {
462 device->controller->read_data(device, &manufacturer_id);
463 device->controller->read_data(device, &device_id);
464 }
465 else
466 {
467 u16 data_buf;
468 device->controller->read_data(device, &data_buf);
469 manufacturer_id = data_buf & 0xff;
470 device->controller->read_data(device, &data_buf);
471 device_id = data_buf & 0xff;
472 }
473
474 for (i = 0; nand_flash_ids[i].name; i++)
475 {
476 if (nand_flash_ids[i].id == device_id)
477 {
478 device->device = &nand_flash_ids[i];
479 break;
480 }
481 }
482
483 for (i = 0; nand_manuf_ids[i].name; i++)
484 {
485 if (nand_manuf_ids[i].id == manufacturer_id)
486 {
487 device->manufacturer = &nand_manuf_ids[i];
488 break;
489 }
490 }
491
492 if (!device->manufacturer)
493 {
494 device->manufacturer = &nand_manuf_ids[0];
495 device->manufacturer->id = manufacturer_id;
496 }
497
498 if (!device->device)
499 {
500 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
501 manufacturer_id, device_id);
502 return ERROR_NAND_OPERATION_FAILED;
503 }
504
505 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
506
507 /* initialize device parameters */
508
509 /* bus width */
510 if (device->device->options & NAND_BUSWIDTH_16)
511 device->bus_width = 16;
512 else
513 device->bus_width = 8;
514
515 /* Do we need extended device probe information? */
516 if (device->device->page_size == 0 ||
517 device->device->erase_size == 0)
518 {
519 if (device->bus_width == 8)
520 {
521 device->controller->read_data(device, id_buff+3);
522 device->controller->read_data(device, id_buff+4);
523 device->controller->read_data(device, id_buff+5);
524 }
525 else
526 {
527 u16 data_buf;
528
529 device->controller->read_data(device, &data_buf);
530 id_buff[3] = data_buf;
531
532 device->controller->read_data(device, &data_buf);
533 id_buff[4] = data_buf;
534
535 device->controller->read_data(device, &data_buf);
536 id_buff[5] = data_buf >> 8;
537 }
538 }
539
540 /* page size */
541 if (device->device->page_size == 0)
542 {
543 device->page_size = 1 << (10 + (id_buff[4] & 3));
544 }
545 else if (device->device->page_size == 256)
546 {
547 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
548 return ERROR_NAND_OPERATION_FAILED;
549 }
550 else
551 {
552 device->page_size = device->device->page_size;
553 }
554
555 /* number of address cycles */
556 if (device->page_size <= 512)
557 {
558 /* small page devices */
559 if (device->device->chip_size <= 32)
560 device->address_cycles = 3;
561 else if (device->device->chip_size <= 8*1024)
562 device->address_cycles = 4;
563 else
564 {
565 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
566 device->address_cycles = 5;
567 }
568 }
569 else
570 {
571 /* large page devices */
572 if (device->device->chip_size <= 128)
573 device->address_cycles = 4;
574 else if (device->device->chip_size <= 32*1024)
575 device->address_cycles = 5;
576 else
577 {
578 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
579 device->address_cycles = 6;
580 }
581 }
582
583 /* erase size */
584 if (device->device->erase_size == 0)
585 {
586 switch ((id_buff[4] >> 4) & 3) {
587 case 0:
588 device->erase_size = 64 << 10;
589 break;
590 case 1:
591 device->erase_size = 128 << 10;
592 break;
593 case 2:
594 device->erase_size = 256 << 10;
595 break;
596 case 3:
597 device->erase_size =512 << 10;
598 break;
599 }
600 }
601 else
602 {
603 device->erase_size = device->device->erase_size;
604 }
605
606 /* initialize controller, but leave parameters at the controllers default */
607 if ((retval = device->controller->init(device) != ERROR_OK))
608 {
609 switch (retval)
610 {
611 case ERROR_NAND_OPERATION_FAILED:
612 LOG_DEBUG("controller initialization failed");
613 return ERROR_NAND_OPERATION_FAILED;
614 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
615 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
616 device->bus_width, device->address_cycles, device->page_size);
617 return ERROR_NAND_OPERATION_FAILED;
618 default:
619 LOG_ERROR("BUG: unknown controller initialization failure");
620 return ERROR_NAND_OPERATION_FAILED;
621 }
622 }
623
624 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
625 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
626
627 for (i = 0; i < device->num_blocks; i++)
628 {
629 device->blocks[i].size = device->erase_size;
630 device->blocks[i].offset = i * device->erase_size;
631 device->blocks[i].is_erased = -1;
632 device->blocks[i].is_bad = -1;
633 }
634
635 return ERROR_OK;
636 }
637
638 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
639 {
640 int i;
641 u32 page;
642 u8 status;
643 int retval;
644
645 if (!device->device)
646 return ERROR_NAND_DEVICE_NOT_PROBED;
647
648 if ((first_block < 0) || (last_block > device->num_blocks))
649 return ERROR_INVALID_ARGUMENTS;
650
651 /* make sure we know if a block is bad before erasing it */
652 for (i = first_block; i <= last_block; i++)
653 {
654 if (device->blocks[i].is_bad == -1)
655 {
656 nand_build_bbt(device, i, last_block);
657 break;
658 }
659 }
660
661 for (i = first_block; i <= last_block; i++)
662 {
663 /* Send erase setup command */
664 device->controller->command(device, NAND_CMD_ERASE1);
665
666 page = i * (device->erase_size / device->page_size);
667
668 /* Send page address */
669 if (device->page_size <= 512)
670 {
671 /* row */
672 device->controller->address(device, page & 0xff);
673 device->controller->address(device, (page >> 8) & 0xff);
674
675 /* 3rd cycle only on devices with more than 32 MiB */
676 if (device->address_cycles >= 4)
677 device->controller->address(device, (page >> 16) & 0xff);
678
679 /* 4th cycle only on devices with more than 8 GiB */
680 if (device->address_cycles >= 5)
681 device->controller->address(device, (page >> 24) & 0xff);
682 }
683 else
684 {
685 /* row */
686 device->controller->address(device, page & 0xff);
687 device->controller->address(device, (page >> 8) & 0xff);
688
689 /* 3rd cycle only on devices with more than 128 MiB */
690 if (device->address_cycles >= 5)
691 device->controller->address(device, (page >> 16) & 0xff);
692 }
693
694 /* Send erase confirm command */
695 device->controller->command(device, NAND_CMD_ERASE2);
696
697 retval = device->controller->nand_ready ?
698 device->controller->nand_ready(device, 1000) :
699 nand_poll_ready(device, 1000);
700 if (!retval) {
701 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
702 return ERROR_NAND_OPERATION_TIMEOUT;
703 }
704
705 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
706 {
707 LOG_ERROR("couldn't read status");
708 return ERROR_NAND_OPERATION_FAILED;
709 }
710
711 if (status & 0x1)
712 {
713 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
714 return ERROR_NAND_OPERATION_FAILED;
715 }
716
717 device->blocks[i].is_erased = 1;
718 }
719
720 return ERROR_OK;
721 }
722
723 #if 0
724 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
725 {
726 u8 *page;
727
728 if (!device->device)
729 return ERROR_NAND_DEVICE_NOT_PROBED;
730
731 if (address % device->page_size)
732 {
733 LOG_ERROR("reads need to be page aligned");
734 return ERROR_NAND_OPERATION_FAILED;
735 }
736
737 page = malloc(device->page_size);
738
739 while (data_size > 0 )
740 {
741 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
742 u32 page_address;
743
744
745 page_address = address / device->page_size;
746
747 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
748
749 memcpy(data, page, thisrun_size);
750
751 address += thisrun_size;
752 data += thisrun_size;
753 data_size -= thisrun_size;
754 }
755
756 free(page);
757
758 return ERROR_OK;
759 }
760
761 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
762 {
763 u8 *page;
764
765 if (!device->device)
766 return ERROR_NAND_DEVICE_NOT_PROBED;
767
768 if (address % device->page_size)
769 {
770 LOG_ERROR("writes need to be page aligned");
771 return ERROR_NAND_OPERATION_FAILED;
772 }
773
774 page = malloc(device->page_size);
775
776 while (data_size > 0 )
777 {
778 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
779 u32 page_address;
780
781 memset(page, 0xff, device->page_size);
782 memcpy(page, data, thisrun_size);
783
784 page_address = address / device->page_size;
785
786 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
787
788 address += thisrun_size;
789 data += thisrun_size;
790 data_size -= thisrun_size;
791 }
792
793 free(page);
794
795 return ERROR_OK;
796 }
797 #endif
798
799 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
800 {
801 u32 block;
802
803 if (!device->device)
804 return ERROR_NAND_DEVICE_NOT_PROBED;
805
806 block = page / (device->erase_size / device->page_size);
807 if (device->blocks[block].is_erased == 1)
808 device->blocks[block].is_erased = 0;
809
810 if (device->use_raw || device->controller->write_page == NULL)
811 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
812 else
813 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
814 }
815
816 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
817 {
818 if (!device->device)
819 return ERROR_NAND_DEVICE_NOT_PROBED;
820
821 if (device->use_raw || device->controller->read_page == NULL)
822 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
823 else
824 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
825 }
826
827 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
828 {
829 u32 i;
830
831 if (!device->device)
832 return ERROR_NAND_DEVICE_NOT_PROBED;
833
834 if (device->page_size <= 512)
835 {
836 /* small page device */
837 if (data)
838 device->controller->command(device, NAND_CMD_READ0);
839 else
840 device->controller->command(device, NAND_CMD_READOOB);
841
842 /* column (always 0, we start at the beginning of a page/OOB area) */
843 device->controller->address(device, 0x0);
844
845 /* row */
846 device->controller->address(device, page & 0xff);
847 device->controller->address(device, (page >> 8) & 0xff);
848
849 /* 4th cycle only on devices with more than 32 MiB */
850 if (device->address_cycles >= 4)
851 device->controller->address(device, (page >> 16) & 0xff);
852
853 /* 5th cycle only on devices with more than 8 GiB */
854 if (device->address_cycles >= 5)
855 device->controller->address(device, (page >> 24) & 0xff);
856 }
857 else
858 {
859 /* large page device */
860 device->controller->command(device, NAND_CMD_READ0);
861
862 /* column (0 when we start at the beginning of a page,
863 * or 2048 for the beginning of OOB area)
864 */
865 device->controller->address(device, 0x0);
866 if (data)
867 device->controller->address(device, 0x0);
868 else
869 device->controller->address(device, 0x8);
870
871 /* row */
872 device->controller->address(device, page & 0xff);
873 device->controller->address(device, (page >> 8) & 0xff);
874
875 /* 5th cycle only on devices with more than 128 MiB */
876 if (device->address_cycles >= 5)
877 device->controller->address(device, (page >> 16) & 0xff);
878
879 /* large page devices need a start command */
880 device->controller->command(device, NAND_CMD_READSTART);
881 }
882
883 if (device->controller->nand_ready) {
884 if (!device->controller->nand_ready(device, 100))
885 return ERROR_NAND_OPERATION_TIMEOUT;
886 } else {
887 alive_sleep(1);
888 }
889
890 if (data)
891 {
892 if (device->controller->read_block_data != NULL)
893 (device->controller->read_block_data)(device, data, data_size);
894 else
895 {
896 for (i = 0; i < data_size;)
897 {
898 if (device->device->options & NAND_BUSWIDTH_16)
899 {
900 device->controller->read_data(device, data);
901 data += 2;
902 i += 2;
903 }
904 else
905 {
906 device->controller->read_data(device, data);
907 data += 1;
908 i += 1;
909 }
910 }
911 }
912 }
913
914 if (oob)
915 {
916 if (device->controller->read_block_data != NULL)
917 (device->controller->read_block_data)(device, oob, oob_size);
918 else
919 {
920 for (i = 0; i < oob_size;)
921 {
922 if (device->device->options & NAND_BUSWIDTH_16)
923 {
924 device->controller->read_data(device, oob);
925 oob += 2;
926 i += 2;
927 }
928 else
929 {
930 device->controller->read_data(device, oob);
931 oob += 1;
932 i += 1;
933 }
934 }
935 }
936 }
937
938 return ERROR_OK;
939 }
940
941 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
942 {
943 u32 i;
944 int retval;
945 u8 status;
946
947 if (!device->device)
948 return ERROR_NAND_DEVICE_NOT_PROBED;
949
950 device->controller->command(device, NAND_CMD_SEQIN);
951
952 if (device->page_size <= 512)
953 {
954 /* column (always 0, we start at the beginning of a page/OOB area) */
955 device->controller->address(device, 0x0);
956
957 /* row */
958 device->controller->address(device, page & 0xff);
959 device->controller->address(device, (page >> 8) & 0xff);
960
961 /* 4th cycle only on devices with more than 32 MiB */
962 if (device->address_cycles >= 4)
963 device->controller->address(device, (page >> 16) & 0xff);
964
965 /* 5th cycle only on devices with more than 8 GiB */
966 if (device->address_cycles >= 5)
967 device->controller->address(device, (page >> 24) & 0xff);
968 }
969 else
970 {
971 /* column (0 when we start at the beginning of a page,
972 * or 2048 for the beginning of OOB area)
973 */
974 device->controller->address(device, 0x0);
975 if (data)
976 device->controller->address(device, 0x0);
977 else
978 device->controller->address(device, 0x8);
979
980 /* row */
981 device->controller->address(device, page & 0xff);
982 device->controller->address(device, (page >> 8) & 0xff);
983
984 /* 5th cycle only on devices with more than 128 MiB */
985 if (device->address_cycles >= 5)
986 device->controller->address(device, (page >> 16) & 0xff);
987 }
988
989 if (data)
990 {
991 if (device->controller->write_block_data != NULL)
992 (device->controller->write_block_data)(device, data, data_size);
993 else
994 {
995 for (i = 0; i < data_size;)
996 {
997 if (device->device->options & NAND_BUSWIDTH_16)
998 {
999 u16 data_buf = le_to_h_u16(data);
1000 device->controller->write_data(device, data_buf);
1001 data += 2;
1002 i += 2;
1003 }
1004 else
1005 {
1006 device->controller->write_data(device, *data);
1007 data += 1;
1008 i += 1;
1009 }
1010 }
1011 }
1012 }
1013
1014 if (oob)
1015 {
1016 if (device->controller->write_block_data != NULL)
1017 (device->controller->write_block_data)(device, oob, oob_size);
1018 else
1019 {
1020 for (i = 0; i < oob_size;)
1021 {
1022 if (device->device->options & NAND_BUSWIDTH_16)
1023 {
1024 u16 oob_buf = le_to_h_u16(data);
1025 device->controller->write_data(device, oob_buf);
1026 oob += 2;
1027 i += 2;
1028 }
1029 else
1030 {
1031 device->controller->write_data(device, *oob);
1032 oob += 1;
1033 i += 1;
1034 }
1035 }
1036 }
1037 }
1038
1039 device->controller->command(device, NAND_CMD_PAGEPROG);
1040
1041 retval = device->controller->nand_ready ?
1042 device->controller->nand_ready(device, 100) :
1043 nand_poll_ready(device, 100);
1044 if (!retval)
1045 return ERROR_NAND_OPERATION_TIMEOUT;
1046
1047 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1048 {
1049 LOG_ERROR("couldn't read status");
1050 return ERROR_NAND_OPERATION_FAILED;
1051 }
1052
1053 if (status & NAND_STATUS_FAIL)
1054 {
1055 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1056 return ERROR_NAND_OPERATION_FAILED;
1057 }
1058
1059 return ERROR_OK;
1060 }
1061
1062 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1063 {
1064 nand_device_t *p;
1065 int i = 0;
1066
1067 if (!nand_devices)
1068 {
1069 command_print(cmd_ctx, "no NAND flash devices configured");
1070 return ERROR_OK;
1071 }
1072
1073 for (p = nand_devices; p; p = p->next)
1074 {
1075 if (p->device)
1076 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1077 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1078 else
1079 command_print(cmd_ctx, "#%i: not probed");
1080 }
1081
1082 return ERROR_OK;
1083 }
1084
1085 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1086 {
1087 nand_device_t *p;
1088 int i = 0;
1089 int j = 0;
1090 int first = -1;
1091 int last = -1;
1092
1093 if ((argc < 1) || (argc > 3))
1094 {
1095 return ERROR_COMMAND_SYNTAX_ERROR;
1096
1097 }
1098
1099 if (argc == 2)
1100 {
1101 first = last = strtoul(args[1], NULL, 0);
1102 }
1103 else if (argc == 3)
1104 {
1105 first = strtoul(args[1], NULL, 0);
1106 last = strtoul(args[2], NULL, 0);
1107 }
1108
1109 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1110 if (p)
1111 {
1112 if (p->device)
1113 {
1114 if (first >= p->num_blocks)
1115 first = p->num_blocks - 1;
1116
1117 if (last >= p->num_blocks)
1118 last = p->num_blocks - 1;
1119
1120 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1121 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1122
1123 for (j = first; j <= last; j++)
1124 {
1125 char *erase_state, *bad_state;
1126
1127 if (p->blocks[j].is_erased == 0)
1128 erase_state = "not erased";
1129 else if (p->blocks[j].is_erased == 1)
1130 erase_state = "erased";
1131 else
1132 erase_state = "erase state unknown";
1133
1134 if (p->blocks[j].is_bad == 0)
1135 bad_state = "";
1136 else if (p->blocks[j].is_bad == 1)
1137 bad_state = " (marked bad)";
1138 else
1139 bad_state = " (block condition unknown)";
1140
1141 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1142 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1143 erase_state, bad_state);
1144 }
1145 }
1146 else
1147 {
1148 command_print(cmd_ctx, "#%i: not probed");
1149 }
1150 }
1151
1152 return ERROR_OK;
1153 }
1154
1155 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1156 {
1157 nand_device_t *p;
1158 int retval;
1159
1160 if (argc != 1)
1161 {
1162 return ERROR_COMMAND_SYNTAX_ERROR;
1163 }
1164
1165 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1166 if (p)
1167 {
1168 if ((retval = nand_probe(p)) == ERROR_OK)
1169 {
1170 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1171 }
1172 else if (retval == ERROR_NAND_OPERATION_FAILED)
1173 {
1174 command_print(cmd_ctx, "probing failed for NAND flash device");
1175 }
1176 else
1177 {
1178 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1179 }
1180 }
1181 else
1182 {
1183 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1184 }
1185
1186 return ERROR_OK;
1187 }
1188
1189 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1190 {
1191 nand_device_t *p;
1192 int retval;
1193
1194 if (argc != 3)
1195 {
1196 return ERROR_COMMAND_SYNTAX_ERROR;
1197
1198 }
1199
1200 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1201 if (p)
1202 {
1203 int first = strtoul(args[1], NULL, 0);
1204 int last = strtoul(args[2], NULL, 0);
1205
1206 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1207 {
1208 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1209 }
1210 else if (retval == ERROR_NAND_OPERATION_FAILED)
1211 {
1212 command_print(cmd_ctx, "erase failed");
1213 }
1214 else
1215 {
1216 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1217 }
1218 }
1219 else
1220 {
1221 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1222 }
1223
1224 return ERROR_OK;
1225 }
1226
1227 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1228 {
1229 nand_device_t *p;
1230 int retval;
1231 int first = -1;
1232 int last = -1;
1233
1234 if ((argc < 1) || (argc > 3) || (argc == 2))
1235 {
1236 return ERROR_COMMAND_SYNTAX_ERROR;
1237
1238 }
1239
1240 if (argc == 3)
1241 {
1242 first = strtoul(args[1], NULL, 0);
1243 last = strtoul(args[2], NULL, 0);
1244 }
1245
1246 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1247 if (p)
1248 {
1249 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1250 {
1251 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1252 }
1253 else if (retval == ERROR_NAND_OPERATION_FAILED)
1254 {
1255 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1256 }
1257 else
1258 {
1259 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1260 }
1261 }
1262 else
1263 {
1264 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1265 }
1266
1267 return ERROR_OK;
1268 }
1269
1270 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1271 {
1272 nand_device_t *p;
1273
1274 if (argc != 4)
1275 {
1276 return ERROR_COMMAND_SYNTAX_ERROR;
1277
1278 }
1279
1280 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1281 if (p)
1282 {
1283
1284 }
1285 else
1286 {
1287 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1288 }
1289
1290 return ERROR_OK;
1291 }
1292
1293 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1294 {
1295 u32 offset;
1296 u32 binary_size;
1297 u32 buf_cnt;
1298 enum oob_formats oob_format = NAND_OOB_NONE;
1299
1300 fileio_t fileio;
1301
1302 duration_t duration;
1303 char *duration_text;
1304
1305 nand_device_t *p;
1306
1307 if (argc < 3)
1308 {
1309 return ERROR_COMMAND_SYNTAX_ERROR;
1310
1311 }
1312
1313 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1314 if (p)
1315 {
1316 u8 *page = NULL;
1317 u32 page_size = 0;
1318 u8 *oob = NULL;
1319 u32 oob_size = 0;
1320 const int *eccpos = NULL;
1321
1322 offset = strtoul(args[2], NULL, 0);
1323
1324 if (argc > 3)
1325 {
1326 int i;
1327 for (i = 3; i < argc; i++)
1328 {
1329 if (!strcmp(args[i], "oob_raw"))
1330 oob_format |= NAND_OOB_RAW;
1331 else if (!strcmp(args[i], "oob_only"))
1332 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1333 else if (!strcmp(args[i], "oob_softecc"))
1334 oob_format |= NAND_OOB_SW_ECC;
1335 else
1336 {
1337 command_print(cmd_ctx, "unknown option: %s", args[i]);
1338 return ERROR_COMMAND_SYNTAX_ERROR;
1339 }
1340 }
1341 }
1342
1343 duration_start_measure(&duration);
1344
1345 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1346 {
1347 return ERROR_OK;
1348 }
1349
1350 buf_cnt = binary_size = fileio.size;
1351
1352 if (!(oob_format & NAND_OOB_ONLY))
1353 {
1354 page_size = p->page_size;
1355 page = malloc(p->page_size);
1356 }
1357
1358 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
1359 {
1360 if (p->page_size == 512) {
1361 oob_size = 16;
1362 eccpos = nand_oob_16.eccpos;
1363 } else if (p->page_size == 2048) {
1364 oob_size = 64;
1365 eccpos = nand_oob_64.eccpos;
1366 }
1367 oob = malloc(oob_size);
1368 }
1369
1370 if (offset % p->page_size)
1371 {
1372 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1373 fileio_close(&fileio);
1374 free(oob);
1375 free(page);
1376 return ERROR_OK;
1377 }
1378
1379 while (buf_cnt > 0)
1380 {
1381 u32 size_read;
1382
1383 if (NULL != page)
1384 {
1385 fileio_read(&fileio, page_size, page, &size_read);
1386 buf_cnt -= size_read;
1387 if (size_read < page_size)
1388 {
1389 memset(page + size_read, 0xff, page_size - size_read);
1390 }
1391 }
1392
1393 if (oob_format & NAND_OOB_SW_ECC)
1394 {
1395 u32 i, j;
1396 u8 ecc[3];
1397 memset(oob, 0xff, oob_size);
1398 for (i = 0, j = 0; i < page_size; i += 256) {
1399 nand_calculate_ecc(p, page+i, ecc);
1400 oob[eccpos[j++]] = ecc[0];
1401 oob[eccpos[j++]] = ecc[1];
1402 oob[eccpos[j++]] = ecc[2];
1403 }
1404 }
1405 else if (NULL != oob)
1406 {
1407 fileio_read(&fileio, oob_size, oob, &size_read);
1408 buf_cnt -= size_read;
1409 if (size_read < oob_size)
1410 {
1411 memset(oob + size_read, 0xff, oob_size - size_read);
1412 }
1413 }
1414
1415 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1416 {
1417 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1418 args[1], args[0], offset);
1419
1420 fileio_close(&fileio);
1421 free(oob);
1422 free(page);
1423
1424 return ERROR_OK;
1425 }
1426 offset += page_size;
1427 }
1428
1429 fileio_close(&fileio);
1430 free(oob);
1431 free(page);
1432 oob = NULL;
1433 page = NULL;
1434 duration_stop_measure(&duration, &duration_text);
1435 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1436 args[1], args[0], offset, duration_text);
1437 free(duration_text);
1438 duration_text = NULL;
1439 }
1440 else
1441 {
1442 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1443 }
1444
1445 return ERROR_OK;
1446 }
1447
1448 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1449 {
1450 nand_device_t *p;
1451
1452 if (argc < 4)
1453 {
1454 return ERROR_COMMAND_SYNTAX_ERROR;
1455 }
1456
1457 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1458 if (p)
1459 {
1460 if (p->device)
1461 {
1462 fileio_t fileio;
1463 duration_t duration;
1464 char *duration_text;
1465 int retval;
1466
1467 u8 *page = NULL;
1468 u32 page_size = 0;
1469 u8 *oob = NULL;
1470 u32 oob_size = 0;
1471 u32 address = strtoul(args[2], NULL, 0);
1472 u32 size = strtoul(args[3], NULL, 0);
1473 u32 bytes_done = 0;
1474 enum oob_formats oob_format = NAND_OOB_NONE;
1475
1476 if (argc > 4)
1477 {
1478 int i;
1479 for (i = 4; i < argc; i++)
1480 {
1481 if (!strcmp(args[i], "oob_raw"))
1482 oob_format |= NAND_OOB_RAW;
1483 else if (!strcmp(args[i], "oob_only"))
1484 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1485 else
1486 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1487 }
1488 }
1489
1490 if ((address % p->page_size) || (size % p->page_size))
1491 {
1492 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1493 return ERROR_OK;
1494 }
1495
1496 if (!(oob_format & NAND_OOB_ONLY))
1497 {
1498 page_size = p->page_size;
1499 page = malloc(p->page_size);
1500 }
1501
1502 if (oob_format & NAND_OOB_RAW)
1503 {
1504 if (p->page_size == 512)
1505 oob_size = 16;
1506 else if (p->page_size == 2048)
1507 oob_size = 64;
1508 oob = malloc(oob_size);
1509 }
1510
1511 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1512 {
1513 return ERROR_OK;
1514 }
1515
1516 duration_start_measure(&duration);
1517
1518 while (size > 0)
1519 {
1520 u32 size_written;
1521 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1522 {
1523 command_print(cmd_ctx, "reading NAND flash page failed");
1524 free(page);
1525 free(oob);
1526 fileio_close(&fileio);
1527 return ERROR_OK;
1528 }
1529
1530 if (NULL != page)
1531 {
1532 fileio_write(&fileio, page_size, page, &size_written);
1533 bytes_done += page_size;
1534 }
1535
1536 if (NULL != oob)
1537 {
1538 fileio_write(&fileio, oob_size, oob, &size_written);
1539 bytes_done += oob_size;
1540 }
1541
1542 size -= p->page_size;
1543 address += p->page_size;
1544 }
1545
1546 free(page);
1547 page = NULL;
1548 free(oob);
1549 oob = NULL;
1550 fileio_close(&fileio);
1551
1552 duration_stop_measure(&duration, &duration_text);
1553 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1554 free(duration_text);
1555 duration_text = NULL;
1556 }
1557 else
1558 {
1559 command_print(cmd_ctx, "#%i: not probed");
1560 }
1561 }
1562 else
1563 {
1564 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1565 }
1566
1567 return ERROR_OK;
1568 }
1569
1570 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1571 {
1572 nand_device_t *p;
1573
1574 if ((argc < 1) || (argc > 2))
1575 {
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1577 }
1578
1579 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1580 if (p)
1581 {
1582 if (p->device)
1583 {
1584 if (argc == 2)
1585 {
1586 if (strcmp("enable", args[1]) == 0)
1587 {
1588 p->use_raw = 1;
1589 }
1590 else if (strcmp("disable", args[1]) == 0)
1591 {
1592 p->use_raw = 0;
1593 }
1594 else
1595 {
1596 return ERROR_COMMAND_SYNTAX_ERROR;
1597 }
1598 }
1599
1600 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1601 }
1602 else
1603 {
1604 command_print(cmd_ctx, "#%i: not probed");
1605 }
1606 }
1607 else
1608 {
1609 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1610 }
1611
1612 return ERROR_OK;
1613 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)