2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 static const char target_not_halted_err_msg
[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg
[] =
43 "minimal granularity is one half-word, %" PRId32
" is incorrect";
44 static const char sram_buffer_bounds_err_msg
[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
46 static const char get_status_register_err_msg
[] = "can't get NAND status";
47 static uint32_t in_sram_address
;
48 unsigned char sign_of_sequental_byte_read
;
50 static int test_iomux_settings (target_t
* target
, uint32_t value
,
51 uint32_t mask
, const char *text
);
52 static int initialize_nf_controller (struct nand_device_s
*device
);
53 static int get_next_byte_from_sram_buffer (target_t
* target
, uint8_t * value
);
54 static int get_next_halfword_from_sram_buffer (target_t
* target
,
56 static int poll_for_complete_op (target_t
* target
, const char *text
);
57 static int validate_target_state (struct nand_device_s
*device
);
58 static int do_data_output (struct nand_device_s
*device
);
60 static int imx31_nand_device_command (struct command_context_s
*cmd_ctx
,
61 char *cmd
, char **args
, int argc
,
62 struct nand_device_s
*device
);
63 static int imx31_init (struct nand_device_s
*device
);
64 static int imx31_read_data (struct nand_device_s
*device
, void *data
);
65 static int imx31_write_data (struct nand_device_s
*device
, uint16_t data
);
66 static int imx31_nand_ready (struct nand_device_s
*device
, int timeout
);
67 static int imx31_register_commands (struct command_context_s
*cmd_ctx
);
68 static int imx31_reset (struct nand_device_s
*device
);
69 static int imx31_command (struct nand_device_s
*device
, uint8_t command
);
70 static int imx31_address (struct nand_device_s
*device
, uint8_t address
);
71 static int imx31_controller_ready (struct nand_device_s
*device
, int tout
);
72 static int imx31_write_page (struct nand_device_s
*device
, uint32_t page
,
73 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
75 static int imx31_read_page (struct nand_device_s
*device
, uint32_t page
,
76 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
79 nand_flash_controller_t imx31_nand_flash_controller
= {
81 .nand_device_command
= imx31_nand_device_command
,
82 .register_commands
= imx31_register_commands
,
85 .command
= imx31_command
,
86 .address
= imx31_address
,
87 .write_data
= imx31_write_data
,
88 .read_data
= imx31_read_data
,
89 .write_page
= imx31_write_page
,
90 .read_page
= imx31_read_page
,
91 .controller_ready
= imx31_controller_ready
,
92 .nand_ready
= imx31_nand_ready
,
95 static int imx31_nand_device_command (struct command_context_s
*cmd_ctx
,
96 char *cmd
, char **args
, int argc
,
97 struct nand_device_s
*device
)
99 mx3_nf_controller_t
*mx3_nf_info
;
100 mx3_nf_info
= malloc (sizeof (mx3_nf_controller_t
));
101 if (mx3_nf_info
== NULL
)
103 LOG_ERROR ("no memory for nand controller");
107 device
->controller_priv
= mx3_nf_info
;
109 mx3_nf_info
->target
= get_target (args
[1]);
110 if (mx3_nf_info
->target
== NULL
)
112 LOG_ERROR ("target '%s' not defined", args
[1]);
117 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
121 * check hwecc requirements
125 hwecc_needed
= strcmp (args
[2], "hwecc");
126 if (hwecc_needed
== 0)
128 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
132 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
136 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
137 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
138 mx3_nf_info
->flags
.target_little_endian
=
139 (mx3_nf_info
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
141 * testing host endianess
145 if (*(char *) &x
== 1)
147 mx3_nf_info
->flags
.host_little_endian
= 1;
151 mx3_nf_info
->flags
.host_little_endian
= 0;
157 static int imx31_init (struct nand_device_s
*device
)
159 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
160 target_t
*target
= mx3_nf_info
->target
;
164 * validate target state
166 int validate_target_result
;
167 validate_target_result
= validate_target_state (device
);
168 if (validate_target_result
!= ERROR_OK
)
170 return validate_target_result
;
175 uint16_t buffsize_register_content
;
176 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
177 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
181 uint32_t pcsr_register_content
;
182 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
183 if (!device
->bus_width
)
186 (pcsr_register_content
& 0x80000000) ? 16 : 8;
190 pcsr_register_content
|=
191 ((device
->bus_width
== 16) ? 0x80000000 : 0x00000000);
192 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
195 if (!device
->page_size
)
198 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
202 pcsr_register_content
|=
203 ((device
->page_size
== 2048) ? 0x40000000 : 0x00000000);
204 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
206 if (mx3_nf_info
->flags
.one_kb_sram
&& (device
->page_size
== 2048))
209 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
214 uint32_t cgr_register_content
;
215 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
216 if (!(cgr_register_content
& 0x00000300))
218 LOG_ERROR ("clock gating to EMI disabled");
224 uint32_t gpr_register_content
;
225 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
226 if (gpr_register_content
& 0x00000060)
228 LOG_ERROR ("pins mode overrided by GPR");
235 * testing IOMUX settings; must be in "functional-mode output and
236 * functional-mode input" mode
239 test_iomux
= ERROR_OK
;
241 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
243 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
245 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
246 if (device
->bus_width
== 16)
249 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
252 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
255 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
258 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
261 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
262 "nfwe,nfre,nfale,nfcle");
263 if (test_iomux
!= ERROR_OK
)
269 initialize_nf_controller (device
);
273 uint16_t nand_status_content
;
275 retval
|= imx31_command (device
, NAND_CMD_STATUS
);
276 retval
|= imx31_address (device
, 0x00);
277 retval
|= do_data_output (device
);
278 if (retval
!= ERROR_OK
)
280 LOG_ERROR (get_status_register_err_msg
);
283 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
284 if (!(nand_status_content
& 0x0080))
287 * is host-big-endian correctly ??
289 LOG_INFO ("NAND read-only");
290 mx3_nf_info
->flags
.nand_readonly
= 1;
294 mx3_nf_info
->flags
.nand_readonly
= 0;
300 static int imx31_read_data (struct nand_device_s
*device
, void *data
)
302 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
303 target_t
*target
= mx3_nf_info
->target
;
306 * validate target state
308 int validate_target_result
;
309 validate_target_result
= validate_target_state (device
);
310 if (validate_target_result
!= ERROR_OK
)
312 return validate_target_result
;
318 * get data from nand chip
320 int try_data_output_from_nand_chip
;
321 try_data_output_from_nand_chip
= do_data_output (device
);
322 if (try_data_output_from_nand_chip
!= ERROR_OK
)
324 return try_data_output_from_nand_chip
;
328 if (device
->bus_width
== 16)
330 get_next_halfword_from_sram_buffer (target
, data
);
334 get_next_byte_from_sram_buffer (target
, data
);
340 static int imx31_write_data (struct nand_device_s
*device
, uint16_t data
)
342 LOG_ERROR ("write_data() not implemented");
343 return ERROR_NAND_OPERATION_FAILED
;
346 static int imx31_nand_ready (struct nand_device_s
*device
, int timeout
)
348 return imx31_controller_ready (device
, timeout
);
351 static int imx31_register_commands (struct command_context_s
*cmd_ctx
)
356 static int imx31_reset (struct nand_device_s
*device
)
359 * validate target state
361 int validate_target_result
;
362 validate_target_result
= validate_target_state (device
);
363 if (validate_target_result
!= ERROR_OK
)
365 return validate_target_result
;
367 initialize_nf_controller (device
);
371 static int imx31_command (struct nand_device_s
*device
, uint8_t command
)
373 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
374 target_t
*target
= mx3_nf_info
->target
;
377 * validate target state
379 int validate_target_result
;
380 validate_target_result
= validate_target_state (device
);
381 if (validate_target_result
!= ERROR_OK
)
383 return validate_target_result
;
389 case NAND_CMD_READOOB
:
390 command
= NAND_CMD_READ0
;
391 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
393 * read_block_data() to
398 command
= NAND_CMD_READ0
;
400 * offset == one half of page size
403 MX3_NF_MAIN_BUFFER0
+ (device
->page_size
>> 1);
405 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
408 target_write_u16 (target
, MX3_NF_FCMD
, command
);
410 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
412 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
415 poll_result
= poll_for_complete_op (target
, "command");
416 if (poll_result
!= ERROR_OK
)
422 * reset cursor to begin of the buffer
424 sign_of_sequental_byte_read
= 0;
427 case NAND_CMD_READID
:
428 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
429 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
431 case NAND_CMD_STATUS
:
432 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
433 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
436 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
437 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
440 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
445 static int imx31_address (struct nand_device_s
*device
, uint8_t address
)
447 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
448 target_t
*target
= mx3_nf_info
->target
;
451 * validate target state
453 int validate_target_result
;
454 validate_target_result
= validate_target_state (device
);
455 if (validate_target_result
!= ERROR_OK
)
457 return validate_target_result
;
461 target_write_u16 (target
, MX3_NF_FADDR
, address
);
463 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
465 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
468 poll_result
= poll_for_complete_op (target
, "address");
469 if (poll_result
!= ERROR_OK
)
477 static int imx31_controller_ready (struct nand_device_s
*device
, int tout
)
479 uint16_t poll_complete_status
;
480 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
481 target_t
*target
= mx3_nf_info
->target
;
485 * validate target state
487 int validate_target_result
;
488 validate_target_result
= validate_target_state (device
);
489 if (validate_target_result
!= ERROR_OK
)
491 return validate_target_result
;
497 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
498 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
508 static int imx31_write_page (struct nand_device_s
*device
, uint32_t page
,
509 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
512 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
513 target_t
*target
= mx3_nf_info
->target
;
517 LOG_ERROR (data_block_size_err_msg
, data_size
);
518 return ERROR_NAND_OPERATION_FAILED
;
522 LOG_ERROR (data_block_size_err_msg
, oob_size
);
523 return ERROR_NAND_OPERATION_FAILED
;
527 LOG_ERROR ("nothing to program");
528 return ERROR_NAND_OPERATION_FAILED
;
532 * validate target state
535 retval
= validate_target_state (device
);
536 if (retval
!= ERROR_OK
)
542 int retval
= ERROR_OK
;
543 retval
|= imx31_command (device
, NAND_CMD_SEQIN
);
544 retval
|= imx31_address (device
, 0x00);
545 retval
|= imx31_address (device
, page
& 0xff);
546 retval
|= imx31_address (device
, (page
>> 8) & 0xff);
547 if (device
->address_cycles
>= 4)
549 retval
|= imx31_address (device
, (page
>> 16) & 0xff);
550 if (device
->address_cycles
>= 5)
552 retval
|= imx31_address (device
, (page
>> 24) & 0xff);
555 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
558 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
561 * part of spare block will be overrided by hardware
565 ("part of spare block will be overrided by hardware ECC generator");
567 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
571 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
573 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
576 poll_result
= poll_for_complete_op (target
, "data input");
577 if (poll_result
!= ERROR_OK
)
582 retval
|= imx31_command (device
, NAND_CMD_PAGEPROG
);
583 if (retval
!= ERROR_OK
)
589 * check status register
592 uint16_t nand_status_content
;
594 retval
|= imx31_command (device
, NAND_CMD_STATUS
);
595 retval
|= imx31_address (device
, 0x00);
596 retval
|= do_data_output (device
);
597 if (retval
!= ERROR_OK
)
599 LOG_ERROR (get_status_register_err_msg
);
602 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
603 if (nand_status_content
& 0x0001)
606 * is host-big-endian correctly ??
608 return ERROR_NAND_OPERATION_FAILED
;
615 static int imx31_read_page (struct nand_device_s
*device
, uint32_t page
,
616 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
619 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
620 target_t
*target
= mx3_nf_info
->target
;
624 LOG_ERROR (data_block_size_err_msg
, data_size
);
625 return ERROR_NAND_OPERATION_FAILED
;
629 LOG_ERROR (data_block_size_err_msg
, oob_size
);
630 return ERROR_NAND_OPERATION_FAILED
;
635 * validate target state
638 retval
= validate_target_state (device
);
639 if (retval
!= ERROR_OK
)
645 int retval
= ERROR_OK
;
646 retval
|= imx31_command (device
, NAND_CMD_READ0
);
647 retval
|= imx31_address (device
, 0x00);
648 retval
|= imx31_address (device
, page
& 0xff);
649 retval
|= imx31_address (device
, (page
>> 8) & 0xff);
650 if (device
->address_cycles
>= 4)
652 retval
|= imx31_address (device
, (page
>> 16) & 0xff);
653 if (device
->address_cycles
>= 5)
655 retval
|= imx31_address (device
, (page
>> 24) & 0xff);
656 retval
|= imx31_command (device
, NAND_CMD_READSTART
);
659 retval
|= do_data_output (device
);
660 if (retval
!= ERROR_OK
)
667 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
672 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
679 static int test_iomux_settings (target_t
* target
, uint32_t address
,
680 uint32_t mask
, const char *text
)
682 uint32_t register_content
;
683 target_read_u32 (target
, address
, ®ister_content
);
684 if ((register_content
& mask
) != (0x12121212 & mask
))
686 LOG_ERROR ("IOMUX for {%s} is bad", text
);
692 static int initialize_nf_controller (struct nand_device_s
*device
)
694 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
695 target_t
*target
= mx3_nf_info
->target
;
697 * resets NAND flash controller in zero time ? I dont know.
699 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
702 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
703 if (target
->endianness
== TARGET_BIG_ENDIAN
)
705 work_mode
|= MX3_NF_BIT_BE_EN
;
707 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
709 work_mode
|= MX3_NF_BIT_ECC_EN
;
711 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
714 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
716 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
719 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
720 if ((temp
& 0x0007) == 1)
722 LOG_ERROR ("NAND flash is tight-locked, reset needed");
728 * unlock NAND flash for write
730 target_write_u16 (target
, MX3_NF_FWP
, 4);
731 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
732 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
734 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
736 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
738 * address of SRAM buffer
740 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
741 sign_of_sequental_byte_read
= 0;
745 static int get_next_byte_from_sram_buffer (target_t
* target
, uint8_t * value
)
747 static uint8_t even_byte
= 0;
751 if (sign_of_sequental_byte_read
== 0)
755 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
757 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
759 sign_of_sequental_byte_read
= 0;
761 return ERROR_NAND_OPERATION_FAILED
;
766 target_read_u16 (target
, in_sram_address
, &temp
);
771 in_sram_address
+= 2;
775 *value
= temp
& 0xff;
779 sign_of_sequental_byte_read
= 1;
783 static int get_next_halfword_from_sram_buffer (target_t
* target
,
786 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
788 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
790 return ERROR_NAND_OPERATION_FAILED
;
794 target_read_u16 (target
, in_sram_address
, value
);
795 in_sram_address
+= 2;
800 static int poll_for_complete_op (target_t
* target
, const char *text
)
802 uint16_t poll_complete_status
;
803 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
806 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
807 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
812 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
814 LOG_ERROR ("%s sending timeout", text
);
815 return ERROR_NAND_OPERATION_FAILED
;
820 static int validate_target_state (struct nand_device_s
*device
)
822 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
823 target_t
*target
= mx3_nf_info
->target
;
825 if (target
->state
!= TARGET_HALTED
)
827 LOG_ERROR (target_not_halted_err_msg
);
828 return ERROR_NAND_OPERATION_FAILED
;
831 if (mx3_nf_info
->flags
.target_little_endian
!=
832 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
835 * endianness changed after NAND controller probed
837 return ERROR_NAND_OPERATION_FAILED
;
842 static int do_data_output (struct nand_device_s
*device
)
844 mx3_nf_controller_t
*mx3_nf_info
= device
->controller_priv
;
845 target_t
*target
= mx3_nf_info
->target
;
846 switch (mx3_nf_info
->fin
)
848 case MX3_NF_FIN_DATAOUT
:
850 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
852 target_write_u16 (target
, MX3_NF_CFG2
,
853 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
857 poll_result
= poll_for_complete_op (target
, "data output");
858 if (poll_result
!= ERROR_OK
)
863 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
867 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
868 && mx3_nf_info
->flags
.hw_ecc_enabled
)
871 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
872 switch (ecc_status
& 0x000c)
876 ("main area readed with 1 (correctable) error");
880 ("main area readed with more than 1 (incorrectable) error");
881 return ERROR_NAND_OPERATION_FAILED
;
884 switch (ecc_status
& 0x0003)
888 ("spare area readed with 1 (correctable) error");
892 ("main area readed with more than 1 (incorrectable) error");
893 return ERROR_NAND_OPERATION_FAILED
;
898 case MX3_NF_FIN_NONE
:
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