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David Brownell <david-b@pacbell.net>:
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28 #include "armv4_5.h"
29 #include "binarybuffer.h"
30
31
32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
36 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
37 static int cfi_probe(struct flash_bank_s *bank);
38 static int cfi_auto_probe(struct flash_bank_s *bank);
39 static int cfi_protect_check(struct flash_bank_s *bank);
40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
41
42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 #define CFI_MAX_BUS_WIDTH 4
45 #define CFI_MAX_CHIP_WIDTH 4
46
47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
48 #define CFI_MAX_INTEL_CODESIZE 256
49
50 flash_driver_t cfi_flash =
51 {
52 .name = "cfi",
53 .register_commands = cfi_register_commands,
54 .flash_bank_command = cfi_flash_bank_command,
55 .erase = cfi_erase,
56 .protect = cfi_protect,
57 .write = cfi_write,
58 .probe = cfi_probe,
59 .auto_probe = cfi_auto_probe,
60 .erase_check = default_flash_blank_check,
61 .protect_check = cfi_protect_check,
62 .info = cfi_info
63 };
64
65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
66 {
67 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
68 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
69 };
70
71 /* CFI fixups foward declarations */
72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
75
76 /* fixup after reading cmdset 0002 primary query table */
77 static cfi_fixup_t cfi_0002_fixups[] = {
78 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
79 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
80 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
81 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
82 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
83 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
84 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
85 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
86 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
87 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
88 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
89 {0, 0, NULL, NULL}
90 };
91
92 /* fixup after reading cmdset 0001 primary query table */
93 static cfi_fixup_t cfi_0001_fixups[] = {
94 {0, 0, NULL, NULL}
95 };
96
97 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
98 {
99 cfi_flash_bank_t *cfi_info = bank->driver_priv;
100 cfi_fixup_t *f;
101
102 for (f = fixups; f->fixup; f++)
103 {
104 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
105 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
106 {
107 f->fixup(bank, f->param);
108 }
109 }
110 }
111
112 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
113 static __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
114 {
115 cfi_flash_bank_t *cfi_info = bank->driver_priv;
116
117 /* while the sector list isn't built, only accesses to sector 0 work */
118 if (sector == 0)
119 return bank->base + (offset * bank->bus_width << cfi_info->x16_as_x8 );
120 else
121 {
122 if (!bank->sectors)
123 {
124 LOG_ERROR("BUG: sector list not yet built");
125 exit(-1);
126 }
127 return bank->base + bank->sectors[sector].offset + (offset * bank->bus_width << cfi_info->x16_as_x8 );
128 }
129
130 }
131
132 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
133 {
134 int i;
135
136 /* clear whole buffer, to ensure bits that exceed the bus_width
137 * are set to zero
138 */
139 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
140 cmd_buf[i] = 0;
141
142 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
143 {
144 for (i = bank->bus_width; i > 0; i--)
145 {
146 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
147 }
148 }
149 else
150 {
151 for (i = 1; i <= bank->bus_width; i++)
152 {
153 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
154 }
155 }
156 }
157
158 /* read unsigned 8-bit value from the bank
159 * flash banks are expected to be made of similar chips
160 * the query result should be the same for all
161 */
162 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
163 {
164 target_t *target = bank->target;
165 u8 data[CFI_MAX_BUS_WIDTH];
166
167 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
168
169 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
170 return data[0];
171 else
172 return data[bank->bus_width - 1];
173 }
174
175 /* read unsigned 8-bit value from the bank
176 * in case of a bank made of multiple chips,
177 * the individual values are ORed
178 */
179 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
180 {
181 target_t *target = bank->target;
182 u8 data[CFI_MAX_BUS_WIDTH];
183 int i;
184
185 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
186
187 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
188 {
189 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
190 data[0] |= data[i];
191
192 return data[0];
193 }
194 else
195 {
196 u8 value = 0;
197 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
198 value |= data[bank->bus_width - 1 - i];
199
200 return value;
201 }
202 }
203
204 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
205 {
206 target_t *target = bank->target;
207 cfi_flash_bank_t *cfi_info = bank->driver_priv;
208 u8 data[CFI_MAX_BUS_WIDTH * 2];
209
210 if(cfi_info->x16_as_x8)
211 {
212 u8 i;
213 for(i=0;i<2;i++)
214 target->type->read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
215 &data[i*bank->bus_width] );
216 }
217 else
218 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
219
220 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
221 return data[0] | data[bank->bus_width] << 8;
222 else
223 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
224 }
225
226 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
227 {
228 target_t *target = bank->target;
229 cfi_flash_bank_t *cfi_info = bank->driver_priv;
230 u8 data[CFI_MAX_BUS_WIDTH * 4];
231
232 if(cfi_info->x16_as_x8)
233 {
234 u8 i;
235 for(i=0;i<4;i++)
236 target->type->read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
237 &data[i*bank->bus_width] );
238 }
239 else
240 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
241
242 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
243 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
244 else
245 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
246 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
247 }
248
249 static void cfi_intel_clear_status_register(flash_bank_t *bank)
250 {
251 target_t *target = bank->target;
252 u8 command[8];
253
254 if (target->state != TARGET_HALTED)
255 {
256 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
257 exit(-1);
258 }
259
260 cfi_command(bank, 0x50, command);
261 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
262 }
263
264 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
265 {
266 u8 status;
267
268 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
269 {
270 LOG_DEBUG("status: 0x%x", status);
271 alive_sleep(1);
272 }
273
274 /* mask out bit 0 (reserved) */
275 status = status & 0xfe;
276
277 LOG_DEBUG("status: 0x%x", status);
278
279 if ((status & 0x80) != 0x80)
280 {
281 LOG_ERROR("timeout while waiting for WSM to become ready");
282 }
283 else if (status != 0x80)
284 {
285 LOG_ERROR("status register: 0x%x", status);
286 if (status & 0x2)
287 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
288 if (status & 0x4)
289 LOG_ERROR("Program suspended");
290 if (status & 0x8)
291 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
292 if (status & 0x10)
293 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
294 if (status & 0x20)
295 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
296 if (status & 0x40)
297 LOG_ERROR("Block Erase Suspended");
298
299 cfi_intel_clear_status_register(bank);
300 }
301
302 return status;
303 }
304
305 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
306 {
307 u8 status, oldstatus;
308 cfi_flash_bank_t *cfi_info = bank->driver_priv;
309
310 oldstatus = cfi_get_u8(bank, 0, 0x0);
311
312 do {
313 status = cfi_get_u8(bank, 0, 0x0);
314 if ((status ^ oldstatus) & 0x40) {
315 if (status & cfi_info->status_poll_mask & 0x20) {
316 oldstatus = cfi_get_u8(bank, 0, 0x0);
317 status = cfi_get_u8(bank, 0, 0x0);
318 if ((status ^ oldstatus) & 0x40) {
319 LOG_ERROR("dq5 timeout, status: 0x%x", status);
320 return(ERROR_FLASH_OPERATION_FAILED);
321 } else {
322 LOG_DEBUG("status: 0x%x", status);
323 return(ERROR_OK);
324 }
325 }
326 } else { /* no toggle: finished, OK */
327 LOG_DEBUG("status: 0x%x", status);
328 return(ERROR_OK);
329 }
330
331 oldstatus = status;
332 alive_sleep(1);
333 } while (timeout-- > 0);
334
335 LOG_ERROR("timeout, status: 0x%x", status);
336
337 return(ERROR_FLASH_BUSY);
338 }
339
340 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
341 {
342 int retval;
343 cfi_flash_bank_t *cfi_info = bank->driver_priv;
344 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
345 target_t *target = bank->target;
346 u8 command[8];
347
348 cfi_info->pri_ext = pri_ext;
349
350 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
351 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
352 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
353
354 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
355 {
356 cfi_command(bank, 0xf0, command);
357 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
358 {
359 return retval;
360 }
361 cfi_command(bank, 0xff, command);
362 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
363 {
364 return retval;
365 }
366 LOG_ERROR("Could not read bank flash bank information");
367 return ERROR_FLASH_BANK_INVALID;
368 }
369
370 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
371 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
372
373 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
374
375 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
376 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
377 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
378
379 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
380
381 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
382 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
383
384 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
385 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
386 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
387
388 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
389 if (pri_ext->num_protection_fields != 1)
390 {
391 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
392 }
393
394 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
395 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
396 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
397
398 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
399
400 return ERROR_OK;
401 }
402
403 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
404 {
405 int retval;
406 cfi_flash_bank_t *cfi_info = bank->driver_priv;
407 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
408 target_t *target = bank->target;
409 u8 command[8];
410
411 cfi_info->pri_ext = pri_ext;
412
413 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
414 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
415 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
416
417 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
418 {
419 cfi_command(bank, 0xf0, command);
420 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
421 {
422 return retval;
423 }
424 LOG_ERROR("Could not read spansion bank information");
425 return ERROR_FLASH_BANK_INVALID;
426 }
427
428 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
429 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
430
431 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
432
433 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
434 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
435 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
436 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
437 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
438 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
439 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
440 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
441 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
442 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
443 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
444
445 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
446 pri_ext->EraseSuspend, pri_ext->BlkProt);
447
448 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
449 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
450
451 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
452
453
454 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
455 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
456 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
457
458 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
459
460 /* default values for implementation specific workarounds */
461 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
462 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
463 pri_ext->_reversed_geometry = 0;
464
465 return ERROR_OK;
466 }
467
468 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
469 {
470 int retval;
471 cfi_atmel_pri_ext_t atmel_pri_ext;
472 cfi_flash_bank_t *cfi_info = bank->driver_priv;
473 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
474 target_t *target = bank->target;
475 u8 command[8];
476
477 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
478 * but a different primary extended query table.
479 * We read the atmel table, and prepare a valid AMD/Spansion query table.
480 */
481
482 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
483
484 cfi_info->pri_ext = pri_ext;
485
486 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
487 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
488 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
489
490 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
491 {
492 cfi_command(bank, 0xf0, command);
493 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
494 {
495 return retval;
496 }
497 LOG_ERROR("Could not read atmel bank information");
498 return ERROR_FLASH_BANK_INVALID;
499 }
500
501 pri_ext->pri[0] = atmel_pri_ext.pri[0];
502 pri_ext->pri[1] = atmel_pri_ext.pri[1];
503 pri_ext->pri[2] = atmel_pri_ext.pri[2];
504
505 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
506 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
507
508 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
509
510 pri_ext->major_version = atmel_pri_ext.major_version;
511 pri_ext->minor_version = atmel_pri_ext.minor_version;
512
513 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
514 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
515 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
516 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
517
518 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
519 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
520
521 if (atmel_pri_ext.features & 0x02)
522 pri_ext->EraseSuspend = 2;
523
524 if (atmel_pri_ext.bottom_boot)
525 pri_ext->TopBottom = 2;
526 else
527 pri_ext->TopBottom = 3;
528
529 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
530 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
531
532 return ERROR_OK;
533 }
534
535 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
536 {
537 cfi_flash_bank_t *cfi_info = bank->driver_priv;
538
539 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
540 {
541 return cfi_read_atmel_pri_ext(bank);
542 }
543 else
544 {
545 return cfi_read_spansion_pri_ext(bank);
546 }
547 }
548
549 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
550 {
551 int printed;
552 cfi_flash_bank_t *cfi_info = bank->driver_priv;
553 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
554
555 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
556 buf += printed;
557 buf_size -= printed;
558
559 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
560 pri_ext->pri[1], pri_ext->pri[2],
561 pri_ext->major_version, pri_ext->minor_version);
562 buf += printed;
563 buf_size -= printed;
564
565 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
566 (pri_ext->SiliconRevision) >> 2,
567 (pri_ext->SiliconRevision) & 0x03);
568 buf += printed;
569 buf_size -= printed;
570
571 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
572 pri_ext->EraseSuspend,
573 pri_ext->BlkProt);
574 buf += printed;
575 buf_size -= printed;
576
577 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
578 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
579 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
580
581 return ERROR_OK;
582 }
583
584 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
585 {
586 int printed;
587 cfi_flash_bank_t *cfi_info = bank->driver_priv;
588 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
589
590 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
591 buf += printed;
592 buf_size -= printed;
593
594 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
595 buf += printed;
596 buf_size -= printed;
597
598 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
599 buf += printed;
600 buf_size -= printed;
601
602 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
603 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
604 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
605 buf += printed;
606 buf_size -= printed;
607
608 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
609
610 return ERROR_OK;
611 }
612
613 static int cfi_register_commands(struct command_context_s *cmd_ctx)
614 {
615 /*command_t *cfi_cmd = */
616 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
617 /*
618 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
619 "print part id of cfi flash bank <num>");
620 */
621 return ERROR_OK;
622 }
623
624 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
625 */
626 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
627 {
628 cfi_flash_bank_t *cfi_info;
629 int i;
630 (void) cmd_ctx;
631 (void) cmd;
632
633 if (argc < 6)
634 {
635 LOG_WARNING("incomplete flash_bank cfi configuration");
636 return ERROR_FLASH_BANK_INVALID;
637 }
638
639 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
640 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
641 {
642 LOG_ERROR("chip and bus width have to specified in bytes");
643 return ERROR_FLASH_BANK_INVALID;
644 }
645
646 cfi_info = malloc(sizeof(cfi_flash_bank_t));
647 cfi_info->probed = 0;
648 bank->driver_priv = cfi_info;
649
650 cfi_info->write_algorithm = NULL;
651
652 cfi_info->x16_as_x8 = 0;
653 cfi_info->jedec_probe = 0;
654 cfi_info->not_cfi = 0;
655
656 for (i = 6; i < argc; i++)
657 {
658 if (strcmp(args[i], "x16_as_x8") == 0)
659 {
660 cfi_info->x16_as_x8 = 1;
661 }
662 else if (strcmp(args[i], "jedec_probe") == 0)
663 {
664 cfi_info->jedec_probe = 1;
665 }
666 }
667
668 cfi_info->write_algorithm = NULL;
669
670 /* bank wasn't probed yet */
671 cfi_info->qry[0] = -1;
672
673 return ERROR_OK;
674 }
675
676 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
677 {
678 int retval;
679 cfi_flash_bank_t *cfi_info = bank->driver_priv;
680 target_t *target = bank->target;
681 u8 command[8];
682 int i;
683
684 cfi_intel_clear_status_register(bank);
685
686 for (i = first; i <= last; i++)
687 {
688 cfi_command(bank, 0x20, command);
689 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
690 {
691 return retval;
692 }
693
694 cfi_command(bank, 0xd0, command);
695 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
696 {
697 return retval;
698 }
699
700 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
701 bank->sectors[i].is_erased = 1;
702 else
703 {
704 cfi_command(bank, 0xff, command);
705 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
706 {
707 return retval;
708 }
709
710 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
711 return ERROR_FLASH_OPERATION_FAILED;
712 }
713 }
714
715 cfi_command(bank, 0xff, command);
716 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
717
718 }
719
720 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
721 {
722 int retval;
723 cfi_flash_bank_t *cfi_info = bank->driver_priv;
724 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
725 target_t *target = bank->target;
726 u8 command[8];
727 int i;
728
729 for (i = first; i <= last; i++)
730 {
731 cfi_command(bank, 0xaa, command);
732 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
733 {
734 return retval;
735 }
736
737 cfi_command(bank, 0x55, command);
738 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
739 {
740 return retval;
741 }
742
743 cfi_command(bank, 0x80, command);
744 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
745 {
746 return retval;
747 }
748
749 cfi_command(bank, 0xaa, command);
750 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
751 {
752 return retval;
753 }
754
755 cfi_command(bank, 0x55, command);
756 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
757 {
758 return retval;
759 }
760
761 cfi_command(bank, 0x30, command);
762 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
763 {
764 return retval;
765 }
766
767 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
768 bank->sectors[i].is_erased = 1;
769 else
770 {
771 cfi_command(bank, 0xf0, command);
772 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
773 {
774 return retval;
775 }
776
777 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
778 return ERROR_FLASH_OPERATION_FAILED;
779 }
780 }
781
782 cfi_command(bank, 0xf0, command);
783 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
784 }
785
786 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
787 {
788 cfi_flash_bank_t *cfi_info = bank->driver_priv;
789
790 if (bank->target->state != TARGET_HALTED)
791 {
792 LOG_ERROR("Target not halted");
793 return ERROR_TARGET_NOT_HALTED;
794 }
795
796 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
797 {
798 return ERROR_FLASH_SECTOR_INVALID;
799 }
800
801 if (cfi_info->qry[0] != 'Q')
802 return ERROR_FLASH_BANK_NOT_PROBED;
803
804 switch(cfi_info->pri_id)
805 {
806 case 1:
807 case 3:
808 return cfi_intel_erase(bank, first, last);
809 break;
810 case 2:
811 return cfi_spansion_erase(bank, first, last);
812 break;
813 default:
814 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
815 break;
816 }
817
818 return ERROR_OK;
819 }
820
821 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
822 {
823 int retval;
824 cfi_flash_bank_t *cfi_info = bank->driver_priv;
825 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
826 target_t *target = bank->target;
827 u8 command[8];
828 int retry = 0;
829 int i;
830
831 /* if the device supports neither legacy lock/unlock (bit 3) nor
832 * instant individual block locking (bit 5).
833 */
834 if (!(pri_ext->feature_support & 0x28))
835 return ERROR_FLASH_OPERATION_FAILED;
836
837 cfi_intel_clear_status_register(bank);
838
839 for (i = first; i <= last; i++)
840 {
841 cfi_command(bank, 0x60, command);
842 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
843 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
844 {
845 return retval;
846 }
847 if (set)
848 {
849 cfi_command(bank, 0x01, command);
850 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
851 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
852 {
853 return retval;
854 }
855 bank->sectors[i].is_protected = 1;
856 }
857 else
858 {
859 cfi_command(bank, 0xd0, command);
860 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
861 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
862 {
863 return retval;
864 }
865 bank->sectors[i].is_protected = 0;
866 }
867
868 /* instant individual block locking doesn't require reading of the status register */
869 if (!(pri_ext->feature_support & 0x20))
870 {
871 /* Clear lock bits operation may take up to 1.4s */
872 cfi_intel_wait_status_busy(bank, 1400);
873 }
874 else
875 {
876 u8 block_status;
877 /* read block lock bit, to verify status */
878 cfi_command(bank, 0x90, command);
879 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
880 {
881 return retval;
882 }
883 block_status = cfi_get_u8(bank, i, 0x2);
884
885 if ((block_status & 0x1) != set)
886 {
887 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
888 cfi_command(bank, 0x70, command);
889 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
890 {
891 return retval;
892 }
893 cfi_intel_wait_status_busy(bank, 10);
894
895 if (retry > 10)
896 return ERROR_FLASH_OPERATION_FAILED;
897 else
898 {
899 i--;
900 retry++;
901 }
902 }
903 }
904 }
905
906 /* if the device doesn't support individual block lock bits set/clear,
907 * all blocks have been unlocked in parallel, so we set those that should be protected
908 */
909 if ((!set) && (!(pri_ext->feature_support & 0x20)))
910 {
911 for (i = 0; i < bank->num_sectors; i++)
912 {
913 if (bank->sectors[i].is_protected == 1)
914 {
915 cfi_intel_clear_status_register(bank);
916
917 cfi_command(bank, 0x60, command);
918 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
919 {
920 return retval;
921 }
922
923 cfi_command(bank, 0x01, command);
924 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
925 {
926 return retval;
927 }
928
929 cfi_intel_wait_status_busy(bank, 100);
930 }
931 }
932 }
933
934 cfi_command(bank, 0xff, command);
935 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
936 }
937
938 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
939 {
940 cfi_flash_bank_t *cfi_info = bank->driver_priv;
941
942 if (bank->target->state != TARGET_HALTED)
943 {
944 LOG_ERROR("Target not halted");
945 return ERROR_TARGET_NOT_HALTED;
946 }
947
948 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
949 {
950 return ERROR_FLASH_SECTOR_INVALID;
951 }
952
953 if (cfi_info->qry[0] != 'Q')
954 return ERROR_FLASH_BANK_NOT_PROBED;
955
956 switch(cfi_info->pri_id)
957 {
958 case 1:
959 case 3:
960 cfi_intel_protect(bank, set, first, last);
961 break;
962 default:
963 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
964 break;
965 }
966
967 return ERROR_OK;
968 }
969
970 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
971 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
972 {
973 /* target_t *target = bank->target; */
974
975 int i;
976
977 /* NOTE:
978 * The data to flash must not be changed in endian! We write a bytestrem in
979 * target byte order already. Only the control and status byte lane of the flash
980 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
981 * word (data seems to be in the upper or lower byte lane for u16 accesses).
982 */
983
984 #if 0
985 if (target->endianness == TARGET_LITTLE_ENDIAN)
986 {
987 #endif
988 /* shift bytes */
989 for (i = 0; i < bank->bus_width - 1; i++)
990 word[i] = word[i + 1];
991 word[bank->bus_width - 1] = byte;
992 #if 0
993 }
994 else
995 {
996 /* shift bytes */
997 for (i = bank->bus_width - 1; i > 0; i--)
998 word[i] = word[i - 1];
999 word[0] = byte;
1000 }
1001 #endif
1002 }
1003
1004 /* Convert code image to target endian */
1005 /* FIXME create general block conversion fcts in target.c?) */
1006 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
1007 {
1008 u32 i;
1009 for (i=0; i< count; i++)
1010 {
1011 target_buffer_set_u32(target, dest, *src);
1012 dest+=4;
1013 src++;
1014 }
1015 }
1016
1017 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1018 {
1019 target_t *target = bank->target;
1020
1021 u8 buf[CFI_MAX_BUS_WIDTH];
1022 cfi_command(bank, cmd, buf);
1023 switch (bank->bus_width)
1024 {
1025 case 1 :
1026 return buf[0];
1027 break;
1028 case 2 :
1029 return target_buffer_get_u16(target, buf);
1030 break;
1031 case 4 :
1032 return target_buffer_get_u32(target, buf);
1033 break;
1034 default :
1035 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1036 return 0;
1037 }
1038 }
1039
1040 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1041 {
1042 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1043 target_t *target = bank->target;
1044 reg_param_t reg_params[7];
1045 armv4_5_algorithm_t armv4_5_info;
1046 working_area_t *source;
1047 u32 buffer_size = 32768;
1048 u32 write_command_val, busy_pattern_val, error_pattern_val;
1049
1050 /* algorithm register usage:
1051 * r0: source address (in RAM)
1052 * r1: target address (in Flash)
1053 * r2: count
1054 * r3: flash write command
1055 * r4: status byte (returned to host)
1056 * r5: busy test pattern
1057 * r6: error test pattern
1058 */
1059
1060 static const u32 word_32_code[] = {
1061 0xe4904004, /* loop: ldr r4, [r0], #4 */
1062 0xe5813000, /* str r3, [r1] */
1063 0xe5814000, /* str r4, [r1] */
1064 0xe5914000, /* busy: ldr r4, [r1] */
1065 0xe0047005, /* and r7, r4, r5 */
1066 0xe1570005, /* cmp r7, r5 */
1067 0x1afffffb, /* bne busy */
1068 0xe1140006, /* tst r4, r6 */
1069 0x1a000003, /* bne done */
1070 0xe2522001, /* subs r2, r2, #1 */
1071 0x0a000001, /* beq done */
1072 0xe2811004, /* add r1, r1 #4 */
1073 0xeafffff2, /* b loop */
1074 0xeafffffe /* done: b -2 */
1075 };
1076
1077 static const u32 word_16_code[] = {
1078 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1079 0xe1c130b0, /* strh r3, [r1] */
1080 0xe1c140b0, /* strh r4, [r1] */
1081 0xe1d140b0, /* busy ldrh r4, [r1] */
1082 0xe0047005, /* and r7, r4, r5 */
1083 0xe1570005, /* cmp r7, r5 */
1084 0x1afffffb, /* bne busy */
1085 0xe1140006, /* tst r4, r6 */
1086 0x1a000003, /* bne done */
1087 0xe2522001, /* subs r2, r2, #1 */
1088 0x0a000001, /* beq done */
1089 0xe2811002, /* add r1, r1 #2 */
1090 0xeafffff2, /* b loop */
1091 0xeafffffe /* done: b -2 */
1092 };
1093
1094 static const u32 word_8_code[] = {
1095 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1096 0xe5c13000, /* strb r3, [r1] */
1097 0xe5c14000, /* strb r4, [r1] */
1098 0xe5d14000, /* busy ldrb r4, [r1] */
1099 0xe0047005, /* and r7, r4, r5 */
1100 0xe1570005, /* cmp r7, r5 */
1101 0x1afffffb, /* bne busy */
1102 0xe1140006, /* tst r4, r6 */
1103 0x1a000003, /* bne done */
1104 0xe2522001, /* subs r2, r2, #1 */
1105 0x0a000001, /* beq done */
1106 0xe2811001, /* add r1, r1 #1 */
1107 0xeafffff2, /* b loop */
1108 0xeafffffe /* done: b -2 */
1109 };
1110 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1111 const u32 *target_code_src;
1112 u32 target_code_size;
1113 int retval = ERROR_OK;
1114
1115
1116 cfi_intel_clear_status_register(bank);
1117
1118 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1119 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1120 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1121
1122 /* If we are setting up the write_algorith, we need target_code_src */
1123 /* if not we only need target_code_size. */
1124 /* */
1125 /* However, we don't want to create multiple code paths, so we */
1126 /* do the unecessary evaluation of target_code_src, which the */
1127 /* compiler will probably nicely optimize away if not needed */
1128
1129 /* prepare algorithm code for target endian */
1130 switch (bank->bus_width)
1131 {
1132 case 1 :
1133 target_code_src = word_8_code;
1134 target_code_size = sizeof(word_8_code);
1135 break;
1136 case 2 :
1137 target_code_src = word_16_code;
1138 target_code_size = sizeof(word_16_code);
1139 break;
1140 case 4 :
1141 target_code_src = word_32_code;
1142 target_code_size = sizeof(word_32_code);
1143 break;
1144 default:
1145 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1146 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1147 }
1148
1149 /* flash write code */
1150 if (!cfi_info->write_algorithm)
1151 {
1152 if ( target_code_size > sizeof(target_code) )
1153 {
1154 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1155 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1156 }
1157 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1158
1159 /* Get memory for block write handler */
1160 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1161 if (retval != ERROR_OK)
1162 {
1163 LOG_WARNING("No working area available, can't do block memory writes");
1164 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1165 };
1166
1167 /* write algorithm code to working area */
1168 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1169 if (retval != ERROR_OK)
1170 {
1171 LOG_ERROR("Unable to write block write code to target");
1172 goto cleanup;
1173 }
1174 }
1175
1176 /* Get a workspace buffer for the data to flash starting with 32k size.
1177 Half size until buffer would be smaller 256 Bytem then fail back */
1178 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1179 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1180 {
1181 buffer_size /= 2;
1182 if (buffer_size <= 256)
1183 {
1184 LOG_WARNING("no large enough working area available, can't do block memory writes");
1185 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1186 goto cleanup;
1187 }
1188 };
1189
1190 /* setup algo registers */
1191 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1192 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1193 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1194 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1195 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1196 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1197 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1198
1199 /* prepare command and status register patterns */
1200 write_command_val = cfi_command_val(bank, 0x40);
1201 busy_pattern_val = cfi_command_val(bank, 0x80);
1202 error_pattern_val = cfi_command_val(bank, 0x7e);
1203
1204 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1205
1206 /* Programming main loop */
1207 while (count > 0)
1208 {
1209 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1210 u32 wsm_error;
1211
1212 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1213 {
1214 goto cleanup;
1215 }
1216
1217 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1218 buf_set_u32(reg_params[1].value, 0, 32, address);
1219 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1220
1221 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1222 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1223 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1224
1225 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1226
1227 /* Execute algorithm, assume breakpoint for last instruction */
1228 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1229 cfi_info->write_algorithm->address,
1230 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1231 10000, /* 10s should be enough for max. 32k of data */
1232 &armv4_5_info);
1233
1234 /* On failure try a fall back to direct word writes */
1235 if (retval != ERROR_OK)
1236 {
1237 cfi_intel_clear_status_register(bank);
1238 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1239 retval = ERROR_FLASH_OPERATION_FAILED;
1240 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1241 /* FIXME To allow fall back or recovery, we must save the actual status
1242 somewhere, so that a higher level code can start recovery. */
1243 goto cleanup;
1244 }
1245
1246 /* Check return value from algo code */
1247 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1248 if (wsm_error)
1249 {
1250 /* read status register (outputs debug inforation) */
1251 cfi_intel_wait_status_busy(bank, 100);
1252 cfi_intel_clear_status_register(bank);
1253 retval = ERROR_FLASH_OPERATION_FAILED;
1254 goto cleanup;
1255 }
1256
1257 buffer += thisrun_count;
1258 address += thisrun_count;
1259 count -= thisrun_count;
1260 }
1261
1262 /* free up resources */
1263 cleanup:
1264 if (source)
1265 target_free_working_area(target, source);
1266
1267 if (cfi_info->write_algorithm)
1268 {
1269 target_free_working_area(target, cfi_info->write_algorithm);
1270 cfi_info->write_algorithm = NULL;
1271 }
1272
1273 destroy_reg_param(&reg_params[0]);
1274 destroy_reg_param(&reg_params[1]);
1275 destroy_reg_param(&reg_params[2]);
1276 destroy_reg_param(&reg_params[3]);
1277 destroy_reg_param(&reg_params[4]);
1278 destroy_reg_param(&reg_params[5]);
1279 destroy_reg_param(&reg_params[6]);
1280
1281 return retval;
1282 }
1283
1284 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1285 {
1286 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1287 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1288 target_t *target = bank->target;
1289 reg_param_t reg_params[10];
1290 armv4_5_algorithm_t armv4_5_info;
1291 working_area_t *source;
1292 u32 buffer_size = 32768;
1293 u32 status;
1294 int retval, retvaltemp;
1295 int exit_code = ERROR_OK;
1296
1297 /* input parameters - */
1298 /* R0 = source address */
1299 /* R1 = destination address */
1300 /* R2 = number of writes */
1301 /* R3 = flash write command */
1302 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1303 /* output parameters - */
1304 /* R5 = 0x80 ok 0x00 bad */
1305 /* temp registers - */
1306 /* R6 = value read from flash to test status */
1307 /* R7 = holding register */
1308 /* unlock registers - */
1309 /* R8 = unlock1_addr */
1310 /* R9 = unlock1_cmd */
1311 /* R10 = unlock2_addr */
1312 /* R11 = unlock2_cmd */
1313
1314 static const u32 word_32_code[] = {
1315 /* 00008100 <sp_32_code>: */
1316 0xe4905004, /* ldr r5, [r0], #4 */
1317 0xe5889000, /* str r9, [r8] */
1318 0xe58ab000, /* str r11, [r10] */
1319 0xe5883000, /* str r3, [r8] */
1320 0xe5815000, /* str r5, [r1] */
1321 0xe1a00000, /* nop */
1322 /* */
1323 /* 00008110 <sp_32_busy>: */
1324 0xe5916000, /* ldr r6, [r1] */
1325 0xe0257006, /* eor r7, r5, r6 */
1326 0xe0147007, /* ands r7, r4, r7 */
1327 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1328 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1329 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1330 0xe5916000, /* ldr r6, [r1] */
1331 0xe0257006, /* eor r7, r5, r6 */
1332 0xe0147007, /* ands r7, r4, r7 */
1333 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1334 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1335 0x1a000004, /* bne 8154 <sp_32_done> */
1336 /* */
1337 /* 00008140 <sp_32_cont>: */
1338 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1339 0x03a05080, /* moveq r5, #128 ; 0x80 */
1340 0x0a000001, /* beq 8154 <sp_32_done> */
1341 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1342 0xeaffffe8, /* b 8100 <sp_32_code> */
1343 /* */
1344 /* 00008154 <sp_32_done>: */
1345 0xeafffffe /* b 8154 <sp_32_done> */
1346 };
1347
1348 static const u32 word_16_code[] = {
1349 /* 00008158 <sp_16_code>: */
1350 0xe0d050b2, /* ldrh r5, [r0], #2 */
1351 0xe1c890b0, /* strh r9, [r8] */
1352 0xe1cab0b0, /* strh r11, [r10] */
1353 0xe1c830b0, /* strh r3, [r8] */
1354 0xe1c150b0, /* strh r5, [r1] */
1355 0xe1a00000, /* nop (mov r0,r0) */
1356 /* */
1357 /* 00008168 <sp_16_busy>: */
1358 0xe1d160b0, /* ldrh r6, [r1] */
1359 0xe0257006, /* eor r7, r5, r6 */
1360 0xe0147007, /* ands r7, r4, r7 */
1361 0x0a000007, /* beq 8198 <sp_16_cont> */
1362 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1363 0x0afffff9, /* beq 8168 <sp_16_busy> */
1364 0xe1d160b0, /* ldrh r6, [r1] */
1365 0xe0257006, /* eor r7, r5, r6 */
1366 0xe0147007, /* ands r7, r4, r7 */
1367 0x0a000001, /* beq 8198 <sp_16_cont> */
1368 0xe3a05000, /* mov r5, #0 ; 0x0 */
1369 0x1a000004, /* bne 81ac <sp_16_done> */
1370 /* */
1371 /* 00008198 <sp_16_cont>: */
1372 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1373 0x03a05080, /* moveq r5, #128 ; 0x80 */
1374 0x0a000001, /* beq 81ac <sp_16_done> */
1375 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1376 0xeaffffe8, /* b 8158 <sp_16_code> */
1377 /* */
1378 /* 000081ac <sp_16_done>: */
1379 0xeafffffe /* b 81ac <sp_16_done> */
1380 };
1381
1382 static const u32 word_8_code[] = {
1383 /* 000081b0 <sp_16_code_end>: */
1384 0xe4d05001, /* ldrb r5, [r0], #1 */
1385 0xe5c89000, /* strb r9, [r8] */
1386 0xe5cab000, /* strb r11, [r10] */
1387 0xe5c83000, /* strb r3, [r8] */
1388 0xe5c15000, /* strb r5, [r1] */
1389 0xe1a00000, /* nop (mov r0,r0) */
1390 /* */
1391 /* 000081c0 <sp_8_busy>: */
1392 0xe5d16000, /* ldrb r6, [r1] */
1393 0xe0257006, /* eor r7, r5, r6 */
1394 0xe0147007, /* ands r7, r4, r7 */
1395 0x0a000007, /* beq 81f0 <sp_8_cont> */
1396 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1397 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1398 0xe5d16000, /* ldrb r6, [r1] */
1399 0xe0257006, /* eor r7, r5, r6 */
1400 0xe0147007, /* ands r7, r4, r7 */
1401 0x0a000001, /* beq 81f0 <sp_8_cont> */
1402 0xe3a05000, /* mov r5, #0 ; 0x0 */
1403 0x1a000004, /* bne 8204 <sp_8_done> */
1404 /* */
1405 /* 000081f0 <sp_8_cont>: */
1406 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1407 0x03a05080, /* moveq r5, #128 ; 0x80 */
1408 0x0a000001, /* beq 8204 <sp_8_done> */
1409 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1410 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1411 /* */
1412 /* 00008204 <sp_8_done>: */
1413 0xeafffffe /* b 8204 <sp_8_done> */
1414 };
1415
1416 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1417 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1418 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1419
1420 /* flash write code */
1421 if (!cfi_info->write_algorithm)
1422 {
1423 u8 *target_code;
1424 int target_code_size;
1425 const u32 *src;
1426
1427 /* convert bus-width dependent algorithm code to correct endiannes */
1428 switch (bank->bus_width)
1429 {
1430 case 1:
1431 src = word_8_code;
1432 target_code_size = sizeof(word_8_code);
1433 break;
1434 case 2:
1435 src = word_16_code;
1436 target_code_size = sizeof(word_16_code);
1437 break;
1438 case 4:
1439 src = word_32_code;
1440 target_code_size = sizeof(word_32_code);
1441 break;
1442 default:
1443 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1444 return ERROR_FLASH_OPERATION_FAILED;
1445 }
1446 target_code = malloc(target_code_size);
1447 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1448
1449 /* allocate working area */
1450 retval=target_alloc_working_area(target, target_code_size,
1451 &cfi_info->write_algorithm);
1452 if (retval != ERROR_OK)
1453 {
1454 free(target_code);
1455 return retval;
1456 }
1457
1458 /* write algorithm code to working area */
1459 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1460 target_code_size, target_code)) != ERROR_OK)
1461 {
1462 free(target_code);
1463 return retval;
1464 }
1465
1466 free(target_code);
1467 }
1468 /* the following code still assumes target code is fixed 24*4 bytes */
1469
1470 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1471 {
1472 buffer_size /= 2;
1473 if (buffer_size <= 256)
1474 {
1475 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1476 if (cfi_info->write_algorithm)
1477 target_free_working_area(target, cfi_info->write_algorithm);
1478
1479 LOG_WARNING("not enough working area available, can't do block memory writes");
1480 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1481 }
1482 };
1483
1484 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1485 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1486 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1487 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1488 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1489 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1490 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1491 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1492 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1493 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1494
1495 while (count > 0)
1496 {
1497 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1498
1499 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1500
1501 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1502 buf_set_u32(reg_params[1].value, 0, 32, address);
1503 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1504 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1505 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1506 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1507 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1508 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1509 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1510
1511 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1512 cfi_info->write_algorithm->address,
1513 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1514 10000, &armv4_5_info);
1515
1516 status = buf_get_u32(reg_params[5].value, 0, 32);
1517
1518 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1519 {
1520 LOG_DEBUG("status: 0x%x", status);
1521 exit_code = ERROR_FLASH_OPERATION_FAILED;
1522 break;
1523 }
1524
1525 buffer += thisrun_count;
1526 address += thisrun_count;
1527 count -= thisrun_count;
1528 }
1529
1530 target_free_working_area(target, source);
1531
1532 destroy_reg_param(&reg_params[0]);
1533 destroy_reg_param(&reg_params[1]);
1534 destroy_reg_param(&reg_params[2]);
1535 destroy_reg_param(&reg_params[3]);
1536 destroy_reg_param(&reg_params[4]);
1537 destroy_reg_param(&reg_params[5]);
1538 destroy_reg_param(&reg_params[6]);
1539 destroy_reg_param(&reg_params[7]);
1540 destroy_reg_param(&reg_params[8]);
1541 destroy_reg_param(&reg_params[9]);
1542
1543 return exit_code;
1544 }
1545
1546 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1547 {
1548 int retval;
1549 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1550 target_t *target = bank->target;
1551 u8 command[8];
1552
1553 cfi_intel_clear_status_register(bank);
1554 cfi_command(bank, 0x40, command);
1555 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1556 {
1557 return retval;
1558 }
1559
1560 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1561 {
1562 return retval;
1563 }
1564
1565 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1566 {
1567 cfi_command(bank, 0xff, command);
1568 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1569 {
1570 return retval;
1571 }
1572
1573 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1574 return ERROR_FLASH_OPERATION_FAILED;
1575 }
1576
1577 return ERROR_OK;
1578 }
1579
1580 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1581 {
1582 int retval;
1583 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1584 target_t *target = bank->target;
1585 u8 command[8];
1586
1587 /* Calculate buffer size and boundary mask */
1588 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1589 u32 buffermask = buffersize-1;
1590 u32 bufferwsize;
1591
1592 /* Check for valid range */
1593 if (address & buffermask)
1594 {
1595 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1596 return ERROR_FLASH_OPERATION_FAILED;
1597 }
1598 switch(bank->chip_width)
1599 {
1600 case 4 : bufferwsize = buffersize / 4; break;
1601 case 2 : bufferwsize = buffersize / 2; break;
1602 case 1 : bufferwsize = buffersize; break;
1603 default:
1604 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1605 return ERROR_FLASH_OPERATION_FAILED;
1606 }
1607
1608 bufferwsize/=(bank->bus_width / bank->chip_width);
1609
1610
1611 /* Check for valid size */
1612 if (wordcount > bufferwsize)
1613 {
1614 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1615 return ERROR_FLASH_OPERATION_FAILED;
1616 }
1617
1618 /* Write to flash buffer */
1619 cfi_intel_clear_status_register(bank);
1620
1621 /* Initiate buffer operation _*/
1622 cfi_command(bank, 0xE8, command);
1623 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1624 {
1625 return retval;
1626 }
1627 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1628 {
1629 cfi_command(bank, 0xff, command);
1630 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1631 {
1632 return retval;
1633 }
1634
1635 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1636 return ERROR_FLASH_OPERATION_FAILED;
1637 }
1638
1639 /* Write buffer wordcount-1 and data words */
1640 cfi_command(bank, bufferwsize-1, command);
1641 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1642 {
1643 return retval;
1644 }
1645
1646 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1647 {
1648 return retval;
1649 }
1650
1651 /* Commit write operation */
1652 cfi_command(bank, 0xd0, command);
1653 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1654 {
1655 return retval;
1656 }
1657 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1658 {
1659 cfi_command(bank, 0xff, command);
1660 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1661 {
1662 return retval;
1663 }
1664
1665 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1666 return ERROR_FLASH_OPERATION_FAILED;
1667 }
1668
1669 return ERROR_OK;
1670 }
1671
1672 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1673 {
1674 int retval;
1675 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1676 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1677 target_t *target = bank->target;
1678 u8 command[8];
1679
1680 cfi_command(bank, 0xaa, command);
1681 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1682 {
1683 return retval;
1684 }
1685
1686 cfi_command(bank, 0x55, command);
1687 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1688 {
1689 return retval;
1690 }
1691
1692 cfi_command(bank, 0xa0, command);
1693 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1694 {
1695 return retval;
1696 }
1697
1698 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1699 {
1700 return retval;
1701 }
1702
1703 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1704 {
1705 cfi_command(bank, 0xf0, command);
1706 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1707 {
1708 return retval;
1709 }
1710
1711 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1712 return ERROR_FLASH_OPERATION_FAILED;
1713 }
1714
1715 return ERROR_OK;
1716 }
1717
1718 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1719 {
1720 int retval;
1721 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1722 target_t *target = bank->target;
1723 u8 command[8];
1724 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1725
1726 /* Calculate buffer size and boundary mask */
1727 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1728 u32 buffermask = buffersize-1;
1729 u32 bufferwsize;
1730
1731 /* Check for valid range */
1732 if (address & buffermask)
1733 {
1734 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1735 return ERROR_FLASH_OPERATION_FAILED;
1736 }
1737 switch(bank->chip_width)
1738 {
1739 case 4 : bufferwsize = buffersize / 4; break;
1740 case 2 : bufferwsize = buffersize / 2; break;
1741 case 1 : bufferwsize = buffersize; break;
1742 default:
1743 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1744 return ERROR_FLASH_OPERATION_FAILED;
1745 }
1746
1747 bufferwsize/=(bank->bus_width / bank->chip_width);
1748
1749 /* Check for valid size */
1750 if (wordcount > bufferwsize)
1751 {
1752 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1753 return ERROR_FLASH_OPERATION_FAILED;
1754 }
1755
1756 // Unlock
1757 cfi_command(bank, 0xaa, command);
1758 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1759 {
1760 return retval;
1761 }
1762
1763 cfi_command(bank, 0x55, command);
1764 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1765 {
1766 return retval;
1767 }
1768
1769 // Buffer load command
1770 cfi_command(bank, 0x25, command);
1771 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1772 {
1773 return retval;
1774 }
1775
1776 /* Write buffer wordcount-1 and data words */
1777 cfi_command(bank, bufferwsize-1, command);
1778 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1779 {
1780 return retval;
1781 }
1782
1783 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1784 {
1785 return retval;
1786 }
1787
1788 /* Commit write operation */
1789 cfi_command(bank, 0x29, command);
1790 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1791 {
1792 return retval;
1793 }
1794
1795 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1796 {
1797 cfi_command(bank, 0xf0, command);
1798 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1799 {
1800 return retval;
1801 }
1802
1803 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1804 return ERROR_FLASH_OPERATION_FAILED;
1805 }
1806
1807 return ERROR_OK;
1808 }
1809
1810 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1811 {
1812 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1813
1814 switch(cfi_info->pri_id)
1815 {
1816 case 1:
1817 case 3:
1818 return cfi_intel_write_word(bank, word, address);
1819 break;
1820 case 2:
1821 return cfi_spansion_write_word(bank, word, address);
1822 break;
1823 default:
1824 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1825 break;
1826 }
1827
1828 return ERROR_FLASH_OPERATION_FAILED;
1829 }
1830
1831 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1832 {
1833 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1834
1835 switch(cfi_info->pri_id)
1836 {
1837 case 1:
1838 case 3:
1839 return cfi_intel_write_words(bank, word, wordcount, address);
1840 break;
1841 case 2:
1842 return cfi_spansion_write_words(bank, word, wordcount, address);
1843 break;
1844 default:
1845 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1846 break;
1847 }
1848
1849 return ERROR_FLASH_OPERATION_FAILED;
1850 }
1851
1852 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1853 {
1854 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1855 target_t *target = bank->target;
1856 u32 address = bank->base + offset; /* address of first byte to be programmed */
1857 u32 write_p, copy_p;
1858 int align; /* number of unaligned bytes */
1859 int blk_count; /* number of bus_width bytes for block copy */
1860 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1861 int i;
1862 int retval;
1863
1864 if (bank->target->state != TARGET_HALTED)
1865 {
1866 LOG_ERROR("Target not halted");
1867 return ERROR_TARGET_NOT_HALTED;
1868 }
1869
1870 if (offset + count > bank->size)
1871 return ERROR_FLASH_DST_OUT_OF_BANK;
1872
1873 if (cfi_info->qry[0] != 'Q')
1874 return ERROR_FLASH_BANK_NOT_PROBED;
1875
1876 /* start at the first byte of the first word (bus_width size) */
1877 write_p = address & ~(bank->bus_width - 1);
1878 if ((align = address - write_p) != 0)
1879 {
1880 LOG_INFO("Fixup %d unaligned head bytes", align );
1881
1882 for (i = 0; i < bank->bus_width; i++)
1883 current_word[i] = 0;
1884 copy_p = write_p;
1885
1886 /* copy bytes before the first write address */
1887 for (i = 0; i < align; ++i, ++copy_p)
1888 {
1889 u8 byte;
1890 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1891 {
1892 return retval;
1893 }
1894 cfi_add_byte(bank, current_word, byte);
1895 }
1896
1897 /* add bytes from the buffer */
1898 for (; (i < bank->bus_width) && (count > 0); i++)
1899 {
1900 cfi_add_byte(bank, current_word, *buffer++);
1901 count--;
1902 copy_p++;
1903 }
1904
1905 /* if the buffer is already finished, copy bytes after the last write address */
1906 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1907 {
1908 u8 byte;
1909 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1910 {
1911 return retval;
1912 }
1913 cfi_add_byte(bank, current_word, byte);
1914 }
1915
1916 retval = cfi_write_word(bank, current_word, write_p);
1917 if (retval != ERROR_OK)
1918 return retval;
1919 write_p = copy_p;
1920 }
1921
1922 /* handle blocks of bus_size aligned bytes */
1923 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1924 switch(cfi_info->pri_id)
1925 {
1926 /* try block writes (fails without working area) */
1927 case 1:
1928 case 3:
1929 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1930 break;
1931 case 2:
1932 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1933 break;
1934 default:
1935 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1936 retval = ERROR_FLASH_OPERATION_FAILED;
1937 break;
1938 }
1939 if (retval == ERROR_OK)
1940 {
1941 /* Increment pointers and decrease count on succesful block write */
1942 buffer += blk_count;
1943 write_p += blk_count;
1944 count -= blk_count;
1945 }
1946 else
1947 {
1948 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1949 {
1950 //adjust buffersize for chip width
1951 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1952 u32 buffermask = buffersize-1;
1953 u32 bufferwsize;
1954
1955 switch(bank->chip_width)
1956 {
1957 case 4 : bufferwsize = buffersize / 4; break;
1958 case 2 : bufferwsize = buffersize / 2; break;
1959 case 1 : bufferwsize = buffersize; break;
1960 default:
1961 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1962 return ERROR_FLASH_OPERATION_FAILED;
1963 }
1964
1965 bufferwsize/=(bank->bus_width / bank->chip_width);
1966
1967 /* fall back to memory writes */
1968 while (count >= (u32)bank->bus_width)
1969 {
1970 int fallback;
1971 if ((write_p & 0xff) == 0)
1972 {
1973 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1974 }
1975 fallback = 1;
1976 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1977 {
1978 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1979 if (retval == ERROR_OK)
1980 {
1981 buffer += buffersize;
1982 write_p += buffersize;
1983 count -= buffersize;
1984 fallback=0;
1985 }
1986 }
1987 /* try the slow way? */
1988 if (fallback)
1989 {
1990 for (i = 0; i < bank->bus_width; i++)
1991 current_word[i] = 0;
1992
1993 for (i = 0; i < bank->bus_width; i++)
1994 {
1995 cfi_add_byte(bank, current_word, *buffer++);
1996 }
1997
1998 retval = cfi_write_word(bank, current_word, write_p);
1999 if (retval != ERROR_OK)
2000 return retval;
2001
2002 write_p += bank->bus_width;
2003 count -= bank->bus_width;
2004 }
2005 }
2006 }
2007 else
2008 return retval;
2009 }
2010
2011 /* return to read array mode, so we can read from flash again for padding */
2012 cfi_command(bank, 0xf0, current_word);
2013 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2014 {
2015 return retval;
2016 }
2017 cfi_command(bank, 0xff, current_word);
2018 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2019 {
2020 return retval;
2021 }
2022
2023 /* handle unaligned tail bytes */
2024 if (count > 0)
2025 {
2026 LOG_INFO("Fixup %d unaligned tail bytes", count );
2027
2028 copy_p = write_p;
2029 for (i = 0; i < bank->bus_width; i++)
2030 current_word[i] = 0;
2031
2032 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2033 {
2034 cfi_add_byte(bank, current_word, *buffer++);
2035 count--;
2036 }
2037 for (; i < bank->bus_width; ++i, ++copy_p)
2038 {
2039 u8 byte;
2040 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2041 {
2042 return retval;
2043 }
2044 cfi_add_byte(bank, current_word, byte);
2045 }
2046 retval = cfi_write_word(bank, current_word, write_p);
2047 if (retval != ERROR_OK)
2048 return retval;
2049 }
2050
2051 /* return to read array mode */
2052 cfi_command(bank, 0xf0, current_word);
2053 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2054 {
2055 return retval;
2056 }
2057 cfi_command(bank, 0xff, current_word);
2058 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2059 }
2060
2061 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2062 {
2063 (void) param;
2064 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2065 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2066
2067 pri_ext->_reversed_geometry = 1;
2068 }
2069
2070 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2071 {
2072 int i;
2073 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2074 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2075 (void) param;
2076
2077 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2078 {
2079 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2080
2081 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2082 {
2083 int j = (cfi_info->num_erase_regions - 1) - i;
2084 u32 swap;
2085
2086 swap = cfi_info->erase_region_info[i];
2087 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2088 cfi_info->erase_region_info[j] = swap;
2089 }
2090 }
2091 }
2092
2093 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2094 {
2095 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2096 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2097 cfi_unlock_addresses_t *unlock_addresses = param;
2098
2099 pri_ext->_unlock1 = unlock_addresses->unlock1;
2100 pri_ext->_unlock2 = unlock_addresses->unlock2;
2101 }
2102
2103 static int cfi_probe(struct flash_bank_s *bank)
2104 {
2105 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2106 target_t *target = bank->target;
2107 u8 command[8];
2108 int num_sectors = 0;
2109 int i;
2110 int sector = 0;
2111 u32 unlock1 = 0x555;
2112 u32 unlock2 = 0x2aa;
2113 int retval;
2114
2115 if (bank->target->state != TARGET_HALTED)
2116 {
2117 LOG_ERROR("Target not halted");
2118 return ERROR_TARGET_NOT_HALTED;
2119 }
2120
2121 cfi_info->probed = 0;
2122
2123 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2124 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2125 */
2126 if (cfi_info->jedec_probe)
2127 {
2128 unlock1 = 0x5555;
2129 unlock2 = 0x2aaa;
2130 }
2131
2132 /* switch to read identifier codes mode ("AUTOSELECT") */
2133 cfi_command(bank, 0xaa, command);
2134 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2135 {
2136 return retval;
2137 }
2138 cfi_command(bank, 0x55, command);
2139 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2140 {
2141 return retval;
2142 }
2143 cfi_command(bank, 0x90, command);
2144 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2145 {
2146 return retval;
2147 }
2148
2149 if (bank->chip_width == 1)
2150 {
2151 u8 manufacturer, device_id;
2152 if((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2153 {
2154 return retval;
2155 }
2156 if((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2157 {
2158 return retval;
2159 }
2160 cfi_info->manufacturer = manufacturer;
2161 cfi_info->device_id = device_id;
2162 }
2163 else if (bank->chip_width == 2)
2164 {
2165 if((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2166 {
2167 return retval;
2168 }
2169 if((retval = target_read_u16(target, flash_address(bank, 0, 0x02), &cfi_info->device_id)) != ERROR_OK)
2170 {
2171 return retval;
2172 }
2173 }
2174
2175 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2176 /* switch back to read array mode */
2177 cfi_command(bank, 0xf0, command);
2178 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2179 {
2180 return retval;
2181 }
2182 cfi_command(bank, 0xff, command);
2183 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2184 {
2185 return retval;
2186 }
2187
2188 /* check device/manufacturer ID for known non-CFI flashes. */
2189 cfi_fixup_non_cfi(bank);
2190
2191 /* query only if this is a CFI compatible flash,
2192 * otherwise the relevant info has already been filled in
2193 */
2194 if (cfi_info->not_cfi == 0)
2195 {
2196 /* enter CFI query mode
2197 * according to JEDEC Standard No. 68.01,
2198 * a single bus sequence with address = 0x55, data = 0x98 should put
2199 * the device into CFI query mode.
2200 *
2201 * SST flashes clearly violate this, and we will consider them incompatbile for now
2202 */
2203 cfi_command(bank, 0x98, command);
2204 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2205 {
2206 return retval;
2207 }
2208
2209 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2210 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2211 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2212
2213 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2214
2215 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2216 {
2217 cfi_command(bank, 0xf0, command);
2218 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2219 {
2220 return retval;
2221 }
2222 cfi_command(bank, 0xff, command);
2223 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2224 {
2225 return retval;
2226 }
2227 LOG_ERROR("Could not probe bank: no QRY");
2228 return ERROR_FLASH_BANK_INVALID;
2229 }
2230
2231 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2232 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2233 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2234 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2235
2236 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2237
2238 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2239 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2240 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2241 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2242 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2243 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2244 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2245 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2246 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2247 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2248 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2249 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2250
2251 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2252 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2253 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2254 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2255 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2256 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2257 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2258 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2259 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2260 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2261 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2262
2263 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2264 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2265 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2266 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2267
2268 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2269
2270 if (cfi_info->num_erase_regions)
2271 {
2272 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2273 for (i = 0; i < cfi_info->num_erase_regions; i++)
2274 {
2275 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2276 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2277 }
2278 }
2279 else
2280 {
2281 cfi_info->erase_region_info = NULL;
2282 }
2283
2284 /* We need to read the primary algorithm extended query table before calculating
2285 * the sector layout to be able to apply fixups
2286 */
2287 switch(cfi_info->pri_id)
2288 {
2289 /* Intel command set (standard and extended) */
2290 case 0x0001:
2291 case 0x0003:
2292 cfi_read_intel_pri_ext(bank);
2293 break;
2294 /* AMD/Spansion, Atmel, ... command set */
2295 case 0x0002:
2296 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2297 cfi_read_0002_pri_ext(bank);
2298 break;
2299 default:
2300 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2301 break;
2302 }
2303
2304 /* return to read array mode
2305 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2306 */
2307 cfi_command(bank, 0xf0, command);
2308 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2309 {
2310 return retval;
2311 }
2312 cfi_command(bank, 0xff, command);
2313 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2314 {
2315 return retval;
2316 }
2317 } /* end CFI case */
2318
2319 /* apply fixups depending on the primary command set */
2320 switch(cfi_info->pri_id)
2321 {
2322 /* Intel command set (standard and extended) */
2323 case 0x0001:
2324 case 0x0003:
2325 cfi_fixup(bank, cfi_0001_fixups);
2326 break;
2327 /* AMD/Spansion, Atmel, ... command set */
2328 case 0x0002:
2329 cfi_fixup(bank, cfi_0002_fixups);
2330 break;
2331 default:
2332 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2333 break;
2334 }
2335
2336 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2337 {
2338 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2339 }
2340
2341 if (cfi_info->num_erase_regions == 0)
2342 {
2343 /* a device might have only one erase block, spanning the whole device */
2344 bank->num_sectors = 1;
2345 bank->sectors = malloc(sizeof(flash_sector_t));
2346
2347 bank->sectors[sector].offset = 0x0;
2348 bank->sectors[sector].size = bank->size;
2349 bank->sectors[sector].is_erased = -1;
2350 bank->sectors[sector].is_protected = -1;
2351 }
2352 else
2353 {
2354 u32 offset = 0;
2355
2356 for (i = 0; i < cfi_info->num_erase_regions; i++)
2357 {
2358 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2359 }
2360
2361 bank->num_sectors = num_sectors;
2362 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2363
2364 for (i = 0; i < cfi_info->num_erase_regions; i++)
2365 {
2366 u32 j;
2367 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2368 {
2369 bank->sectors[sector].offset = offset;
2370 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2371 offset += bank->sectors[sector].size;
2372 bank->sectors[sector].is_erased = -1;
2373 bank->sectors[sector].is_protected = -1;
2374 sector++;
2375 }
2376 }
2377 if (offset != cfi_info->dev_size)
2378 {
2379 LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2380 }
2381 }
2382
2383 cfi_info->probed = 1;
2384
2385 return ERROR_OK;
2386 }
2387
2388 static int cfi_auto_probe(struct flash_bank_s *bank)
2389 {
2390 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2391 if (cfi_info->probed)
2392 return ERROR_OK;
2393 return cfi_probe(bank);
2394 }
2395
2396
2397 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2398 {
2399 int retval;
2400 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2401 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2402 target_t *target = bank->target;
2403 u8 command[CFI_MAX_BUS_WIDTH];
2404 int i;
2405
2406 /* check if block lock bits are supported on this device */
2407 if (!(pri_ext->blk_status_reg_mask & 0x1))
2408 return ERROR_FLASH_OPERATION_FAILED;
2409
2410 cfi_command(bank, 0x90, command);
2411 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2412 {
2413 return retval;
2414 }
2415
2416 for (i = 0; i < bank->num_sectors; i++)
2417 {
2418 u8 block_status = cfi_get_u8(bank, i, 0x2);
2419
2420 if (block_status & 1)
2421 bank->sectors[i].is_protected = 1;
2422 else
2423 bank->sectors[i].is_protected = 0;
2424 }
2425
2426 cfi_command(bank, 0xff, command);
2427 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2428 }
2429
2430 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2431 {
2432 int retval;
2433 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2434 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2435 target_t *target = bank->target;
2436 u8 command[8];
2437 int i;
2438
2439 cfi_command(bank, 0xaa, command);
2440 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2441 {
2442 return retval;
2443 }
2444
2445 cfi_command(bank, 0x55, command);
2446 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2447 {
2448 return retval;
2449 }
2450
2451 cfi_command(bank, 0x90, command);
2452 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2453 {
2454 return retval;
2455 }
2456
2457 for (i = 0; i < bank->num_sectors; i++)
2458 {
2459 u8 block_status = cfi_get_u8(bank, i, 0x2);
2460
2461 if (block_status & 1)
2462 bank->sectors[i].is_protected = 1;
2463 else
2464 bank->sectors[i].is_protected = 0;
2465 }
2466
2467 cfi_command(bank, 0xf0, command);
2468 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2469 }
2470
2471 static int cfi_protect_check(struct flash_bank_s *bank)
2472 {
2473 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2474
2475 if (bank->target->state != TARGET_HALTED)
2476 {
2477 LOG_ERROR("Target not halted");
2478 return ERROR_TARGET_NOT_HALTED;
2479 }
2480
2481 if (cfi_info->qry[0] != 'Q')
2482 return ERROR_FLASH_BANK_NOT_PROBED;
2483
2484 switch(cfi_info->pri_id)
2485 {
2486 case 1:
2487 case 3:
2488 return cfi_intel_protect_check(bank);
2489 break;
2490 case 2:
2491 return cfi_spansion_protect_check(bank);
2492 break;
2493 default:
2494 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2495 break;
2496 }
2497
2498 return ERROR_OK;
2499 }
2500
2501 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2502 {
2503 int printed;
2504 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2505
2506 if (cfi_info->qry[0] == (char)-1)
2507 {
2508 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2509 return ERROR_OK;
2510 }
2511
2512 if (cfi_info->not_cfi == 0)
2513 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2514 else
2515 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2516 buf += printed;
2517 buf_size -= printed;
2518
2519 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2520 cfi_info->manufacturer, cfi_info->device_id);
2521 buf += printed;
2522 buf_size -= printed;
2523
2524 if (cfi_info->not_cfi == 0)
2525 {
2526 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2527 buf += printed;
2528 buf_size -= printed;
2529
2530 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2531 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2532 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2533 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2534 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2535 buf += printed;
2536 buf_size -= printed;
2537
2538 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2539 1 << cfi_info->word_write_timeout_typ,
2540 1 << cfi_info->buf_write_timeout_typ,
2541 1 << cfi_info->block_erase_timeout_typ,
2542 1 << cfi_info->chip_erase_timeout_typ);
2543 buf += printed;
2544 buf_size -= printed;
2545
2546 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2547 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2548 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2549 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2550 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2551 buf += printed;
2552 buf_size -= printed;
2553
2554 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2555 cfi_info->dev_size,
2556 cfi_info->interface_desc,
2557 1 << cfi_info->max_buf_write_size);
2558 buf += printed;
2559 buf_size -= printed;
2560
2561 switch(cfi_info->pri_id)
2562 {
2563 case 1:
2564 case 3:
2565 cfi_intel_info(bank, buf, buf_size);
2566 break;
2567 case 2:
2568 cfi_spansion_info(bank, buf, buf_size);
2569 break;
2570 default:
2571 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2572 break;
2573 }
2574 }
2575
2576 return ERROR_OK;
2577 }
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