Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Audit and eliminate redundant #include directives in src/flash sources.
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28 #include "armv4_5.h"
29 #include "binarybuffer.h"
30
31
32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
36 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
37 static int cfi_probe(struct flash_bank_s *bank);
38 static int cfi_auto_probe(struct flash_bank_s *bank);
39 static int cfi_protect_check(struct flash_bank_s *bank);
40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
41
42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 #define CFI_MAX_BUS_WIDTH 4
45 #define CFI_MAX_CHIP_WIDTH 4
46
47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
48 #define CFI_MAX_INTEL_CODESIZE 256
49
50 flash_driver_t cfi_flash =
51 {
52 .name = "cfi",
53 .register_commands = cfi_register_commands,
54 .flash_bank_command = cfi_flash_bank_command,
55 .erase = cfi_erase,
56 .protect = cfi_protect,
57 .write = cfi_write,
58 .probe = cfi_probe,
59 .auto_probe = cfi_auto_probe,
60 .erase_check = default_flash_blank_check,
61 .protect_check = cfi_protect_check,
62 .info = cfi_info
63 };
64
65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
66 {
67 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
68 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
69 };
70
71 /* CFI fixups foward declarations */
72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
75
76 /* fixup after reading cmdset 0002 primary query table */
77 static cfi_fixup_t cfi_0002_fixups[] = {
78 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
79 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
80 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
81 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
82 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
83 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
84 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
85 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
86 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
87 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
88 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
89 {0, 0, NULL, NULL}
90 };
91
92 /* fixup after reading cmdset 0001 primary query table */
93 static cfi_fixup_t cfi_0001_fixups[] = {
94 {0, 0, NULL, NULL}
95 };
96
97 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
98 {
99 cfi_flash_bank_t *cfi_info = bank->driver_priv;
100 cfi_fixup_t *f;
101
102 for (f = fixups; f->fixup; f++)
103 {
104 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
105 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
106 {
107 f->fixup(bank, f->param);
108 }
109 }
110 }
111
112 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
113 static __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
114 {
115 /* while the sector list isn't built, only accesses to sector 0 work */
116 if (sector == 0)
117 return bank->base + offset * bank->bus_width;
118 else
119 {
120 if (!bank->sectors)
121 {
122 LOG_ERROR("BUG: sector list not yet built");
123 exit(-1);
124 }
125 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
126 }
127
128 }
129
130 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
131 {
132 int i;
133
134 /* clear whole buffer, to ensure bits that exceed the bus_width
135 * are set to zero
136 */
137 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
138 cmd_buf[i] = 0;
139
140 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
141 {
142 for (i = bank->bus_width; i > 0; i--)
143 {
144 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
145 }
146 }
147 else
148 {
149 for (i = 1; i <= bank->bus_width; i++)
150 {
151 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
152 }
153 }
154 }
155
156 /* read unsigned 8-bit value from the bank
157 * flash banks are expected to be made of similar chips
158 * the query result should be the same for all
159 */
160 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
161 {
162 target_t *target = bank->target;
163 u8 data[CFI_MAX_BUS_WIDTH];
164
165 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
166
167 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
168 return data[0];
169 else
170 return data[bank->bus_width - 1];
171 }
172
173 /* read unsigned 8-bit value from the bank
174 * in case of a bank made of multiple chips,
175 * the individual values are ORed
176 */
177 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
178 {
179 target_t *target = bank->target;
180 u8 data[CFI_MAX_BUS_WIDTH];
181 int i;
182
183 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
184
185 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
186 {
187 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
188 data[0] |= data[i];
189
190 return data[0];
191 }
192 else
193 {
194 u8 value = 0;
195 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
196 value |= data[bank->bus_width - 1 - i];
197
198 return value;
199 }
200 }
201
202 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
203 {
204 target_t *target = bank->target;
205 u8 data[CFI_MAX_BUS_WIDTH * 2];
206
207 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
208
209 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
210 return data[0] | data[bank->bus_width] << 8;
211 else
212 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
213 }
214
215 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
216 {
217 target_t *target = bank->target;
218 u8 data[CFI_MAX_BUS_WIDTH * 4];
219
220 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
221
222 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
223 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
224 else
225 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
226 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
227 }
228
229 static void cfi_intel_clear_status_register(flash_bank_t *bank)
230 {
231 target_t *target = bank->target;
232 u8 command[8];
233
234 if (target->state != TARGET_HALTED)
235 {
236 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
237 exit(-1);
238 }
239
240 cfi_command(bank, 0x50, command);
241 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
242 }
243
244 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
245 {
246 u8 status;
247
248 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
249 {
250 LOG_DEBUG("status: 0x%x", status);
251 alive_sleep(1);
252 }
253
254 /* mask out bit 0 (reserved) */
255 status = status & 0xfe;
256
257 LOG_DEBUG("status: 0x%x", status);
258
259 if ((status & 0x80) != 0x80)
260 {
261 LOG_ERROR("timeout while waiting for WSM to become ready");
262 }
263 else if (status != 0x80)
264 {
265 LOG_ERROR("status register: 0x%x", status);
266 if (status & 0x2)
267 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
268 if (status & 0x4)
269 LOG_ERROR("Program suspended");
270 if (status & 0x8)
271 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
272 if (status & 0x10)
273 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
274 if (status & 0x20)
275 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
276 if (status & 0x40)
277 LOG_ERROR("Block Erase Suspended");
278
279 cfi_intel_clear_status_register(bank);
280 }
281
282 return status;
283 }
284
285 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
286 {
287 u8 status, oldstatus;
288 cfi_flash_bank_t *cfi_info = bank->driver_priv;
289
290 oldstatus = cfi_get_u8(bank, 0, 0x0);
291
292 do {
293 status = cfi_get_u8(bank, 0, 0x0);
294 if ((status ^ oldstatus) & 0x40) {
295 if (status & cfi_info->status_poll_mask & 0x20) {
296 oldstatus = cfi_get_u8(bank, 0, 0x0);
297 status = cfi_get_u8(bank, 0, 0x0);
298 if ((status ^ oldstatus) & 0x40) {
299 LOG_ERROR("dq5 timeout, status: 0x%x", status);
300 return(ERROR_FLASH_OPERATION_FAILED);
301 } else {
302 LOG_DEBUG("status: 0x%x", status);
303 return(ERROR_OK);
304 }
305 }
306 } else { /* no toggle: finished, OK */
307 LOG_DEBUG("status: 0x%x", status);
308 return(ERROR_OK);
309 }
310
311 oldstatus = status;
312 alive_sleep(1);
313 } while (timeout-- > 0);
314
315 LOG_ERROR("timeout, status: 0x%x", status);
316
317 return(ERROR_FLASH_BUSY);
318 }
319
320 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
321 {
322 int retval;
323 cfi_flash_bank_t *cfi_info = bank->driver_priv;
324 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
325 target_t *target = bank->target;
326 u8 command[8];
327
328 cfi_info->pri_ext = pri_ext;
329
330 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
331 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
332 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
333
334 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
335 {
336 cfi_command(bank, 0xf0, command);
337 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
338 {
339 return retval;
340 }
341 cfi_command(bank, 0xff, command);
342 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
343 {
344 return retval;
345 }
346 LOG_ERROR("Could not read bank flash bank information");
347 return ERROR_FLASH_BANK_INVALID;
348 }
349
350 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
351 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
352
353 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
354
355 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
356 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
357 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
358
359 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
360
361 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
362 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
363
364 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
365 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
366 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
367
368 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
369 if (pri_ext->num_protection_fields != 1)
370 {
371 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
372 }
373
374 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
375 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
376 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
377
378 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
379
380 return ERROR_OK;
381 }
382
383 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
384 {
385 int retval;
386 cfi_flash_bank_t *cfi_info = bank->driver_priv;
387 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
388 target_t *target = bank->target;
389 u8 command[8];
390
391 cfi_info->pri_ext = pri_ext;
392
393 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
394 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
395 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
396
397 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
398 {
399 cfi_command(bank, 0xf0, command);
400 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
401 {
402 return retval;
403 }
404 LOG_ERROR("Could not read spansion bank information");
405 return ERROR_FLASH_BANK_INVALID;
406 }
407
408 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
409 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
410
411 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
412
413 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
414 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
415 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
416 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
417 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
418 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
419 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
420 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
421 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
422 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
423 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
424
425 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
426 pri_ext->EraseSuspend, pri_ext->BlkProt);
427
428 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
429 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
430
431 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
432
433
434 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
435 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
436 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
437
438 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
439
440 /* default values for implementation specific workarounds */
441 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
442 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
443 pri_ext->_reversed_geometry = 0;
444
445 return ERROR_OK;
446 }
447
448 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
449 {
450 int retval;
451 cfi_atmel_pri_ext_t atmel_pri_ext;
452 cfi_flash_bank_t *cfi_info = bank->driver_priv;
453 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
454 target_t *target = bank->target;
455 u8 command[8];
456
457 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
458 * but a different primary extended query table.
459 * We read the atmel table, and prepare a valid AMD/Spansion query table.
460 */
461
462 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
463
464 cfi_info->pri_ext = pri_ext;
465
466 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
467 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
468 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
469
470 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
471 {
472 cfi_command(bank, 0xf0, command);
473 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
474 {
475 return retval;
476 }
477 LOG_ERROR("Could not read atmel bank information");
478 return ERROR_FLASH_BANK_INVALID;
479 }
480
481 pri_ext->pri[0] = atmel_pri_ext.pri[0];
482 pri_ext->pri[1] = atmel_pri_ext.pri[1];
483 pri_ext->pri[2] = atmel_pri_ext.pri[2];
484
485 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
486 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
487
488 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
489
490 pri_ext->major_version = atmel_pri_ext.major_version;
491 pri_ext->minor_version = atmel_pri_ext.minor_version;
492
493 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
494 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
495 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
496 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
497
498 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
499 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
500
501 if (atmel_pri_ext.features & 0x02)
502 pri_ext->EraseSuspend = 2;
503
504 if (atmel_pri_ext.bottom_boot)
505 pri_ext->TopBottom = 2;
506 else
507 pri_ext->TopBottom = 3;
508
509 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
510 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
511
512 return ERROR_OK;
513 }
514
515 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
516 {
517 cfi_flash_bank_t *cfi_info = bank->driver_priv;
518
519 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
520 {
521 return cfi_read_atmel_pri_ext(bank);
522 }
523 else
524 {
525 return cfi_read_spansion_pri_ext(bank);
526 }
527 }
528
529 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
530 {
531 int printed;
532 cfi_flash_bank_t *cfi_info = bank->driver_priv;
533 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
534
535 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
536 buf += printed;
537 buf_size -= printed;
538
539 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
540 pri_ext->pri[1], pri_ext->pri[2],
541 pri_ext->major_version, pri_ext->minor_version);
542 buf += printed;
543 buf_size -= printed;
544
545 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
546 (pri_ext->SiliconRevision) >> 2,
547 (pri_ext->SiliconRevision) & 0x03);
548 buf += printed;
549 buf_size -= printed;
550
551 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
552 pri_ext->EraseSuspend,
553 pri_ext->BlkProt);
554 buf += printed;
555 buf_size -= printed;
556
557 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
558 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
559 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
560
561 return ERROR_OK;
562 }
563
564 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
565 {
566 int printed;
567 cfi_flash_bank_t *cfi_info = bank->driver_priv;
568 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
569
570 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
571 buf += printed;
572 buf_size -= printed;
573
574 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
575 buf += printed;
576 buf_size -= printed;
577
578 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
579 buf += printed;
580 buf_size -= printed;
581
582 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
583 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
584 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
585 buf += printed;
586 buf_size -= printed;
587
588 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
589
590 return ERROR_OK;
591 }
592
593 static int cfi_register_commands(struct command_context_s *cmd_ctx)
594 {
595 /*command_t *cfi_cmd = */
596 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
597 /*
598 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
599 "print part id of cfi flash bank <num>");
600 */
601 return ERROR_OK;
602 }
603
604 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
605 */
606 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
607 {
608 cfi_flash_bank_t *cfi_info;
609 int i;
610 (void) cmd_ctx;
611 (void) cmd;
612
613 if (argc < 6)
614 {
615 LOG_WARNING("incomplete flash_bank cfi configuration");
616 return ERROR_FLASH_BANK_INVALID;
617 }
618
619 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
620 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
621 {
622 LOG_ERROR("chip and bus width have to specified in bytes");
623 return ERROR_FLASH_BANK_INVALID;
624 }
625
626 cfi_info = malloc(sizeof(cfi_flash_bank_t));
627 cfi_info->probed = 0;
628 bank->driver_priv = cfi_info;
629
630 cfi_info->write_algorithm = NULL;
631
632 cfi_info->x16_as_x8 = 0;
633 cfi_info->jedec_probe = 0;
634 cfi_info->not_cfi = 0;
635
636 for (i = 6; i < argc; i++)
637 {
638 if (strcmp(args[i], "x16_as_x8") == 0)
639 {
640 cfi_info->x16_as_x8 = 1;
641 }
642 else if (strcmp(args[i], "jedec_probe") == 0)
643 {
644 cfi_info->jedec_probe = 1;
645 }
646 }
647
648 cfi_info->write_algorithm = NULL;
649
650 /* bank wasn't probed yet */
651 cfi_info->qry[0] = -1;
652
653 return ERROR_OK;
654 }
655
656 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
657 {
658 int retval;
659 cfi_flash_bank_t *cfi_info = bank->driver_priv;
660 target_t *target = bank->target;
661 u8 command[8];
662 int i;
663
664 cfi_intel_clear_status_register(bank);
665
666 for (i = first; i <= last; i++)
667 {
668 cfi_command(bank, 0x20, command);
669 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
670 {
671 return retval;
672 }
673
674 cfi_command(bank, 0xd0, command);
675 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
676 {
677 return retval;
678 }
679
680 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
681 bank->sectors[i].is_erased = 1;
682 else
683 {
684 cfi_command(bank, 0xff, command);
685 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
686 {
687 return retval;
688 }
689
690 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
691 return ERROR_FLASH_OPERATION_FAILED;
692 }
693 }
694
695 cfi_command(bank, 0xff, command);
696 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
697
698 }
699
700 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
701 {
702 int retval;
703 cfi_flash_bank_t *cfi_info = bank->driver_priv;
704 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
705 target_t *target = bank->target;
706 u8 command[8];
707 int i;
708
709 for (i = first; i <= last; i++)
710 {
711 cfi_command(bank, 0xaa, command);
712 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
713 {
714 return retval;
715 }
716
717 cfi_command(bank, 0x55, command);
718 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
719 {
720 return retval;
721 }
722
723 cfi_command(bank, 0x80, command);
724 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
725 {
726 return retval;
727 }
728
729 cfi_command(bank, 0xaa, command);
730 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
731 {
732 return retval;
733 }
734
735 cfi_command(bank, 0x55, command);
736 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
737 {
738 return retval;
739 }
740
741 cfi_command(bank, 0x30, command);
742 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
743 {
744 return retval;
745 }
746
747 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
748 bank->sectors[i].is_erased = 1;
749 else
750 {
751 cfi_command(bank, 0xf0, command);
752 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
753 {
754 return retval;
755 }
756
757 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
758 return ERROR_FLASH_OPERATION_FAILED;
759 }
760 }
761
762 cfi_command(bank, 0xf0, command);
763 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
764 }
765
766 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
767 {
768 cfi_flash_bank_t *cfi_info = bank->driver_priv;
769
770 if (bank->target->state != TARGET_HALTED)
771 {
772 LOG_ERROR("Target not halted");
773 return ERROR_TARGET_NOT_HALTED;
774 }
775
776 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
777 {
778 return ERROR_FLASH_SECTOR_INVALID;
779 }
780
781 if (cfi_info->qry[0] != 'Q')
782 return ERROR_FLASH_BANK_NOT_PROBED;
783
784 switch(cfi_info->pri_id)
785 {
786 case 1:
787 case 3:
788 return cfi_intel_erase(bank, first, last);
789 break;
790 case 2:
791 return cfi_spansion_erase(bank, first, last);
792 break;
793 default:
794 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
795 break;
796 }
797
798 return ERROR_OK;
799 }
800
801 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
802 {
803 int retval;
804 cfi_flash_bank_t *cfi_info = bank->driver_priv;
805 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
806 target_t *target = bank->target;
807 u8 command[8];
808 int retry = 0;
809 int i;
810
811 /* if the device supports neither legacy lock/unlock (bit 3) nor
812 * instant individual block locking (bit 5).
813 */
814 if (!(pri_ext->feature_support & 0x28))
815 return ERROR_FLASH_OPERATION_FAILED;
816
817 cfi_intel_clear_status_register(bank);
818
819 for (i = first; i <= last; i++)
820 {
821 cfi_command(bank, 0x60, command);
822 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
823 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
824 {
825 return retval;
826 }
827 if (set)
828 {
829 cfi_command(bank, 0x01, command);
830 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
831 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
832 {
833 return retval;
834 }
835 bank->sectors[i].is_protected = 1;
836 }
837 else
838 {
839 cfi_command(bank, 0xd0, command);
840 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
841 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
842 {
843 return retval;
844 }
845 bank->sectors[i].is_protected = 0;
846 }
847
848 /* instant individual block locking doesn't require reading of the status register */
849 if (!(pri_ext->feature_support & 0x20))
850 {
851 /* Clear lock bits operation may take up to 1.4s */
852 cfi_intel_wait_status_busy(bank, 1400);
853 }
854 else
855 {
856 u8 block_status;
857 /* read block lock bit, to verify status */
858 cfi_command(bank, 0x90, command);
859 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
860 {
861 return retval;
862 }
863 block_status = cfi_get_u8(bank, i, 0x2);
864
865 if ((block_status & 0x1) != set)
866 {
867 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
868 cfi_command(bank, 0x70, command);
869 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
870 {
871 return retval;
872 }
873 cfi_intel_wait_status_busy(bank, 10);
874
875 if (retry > 10)
876 return ERROR_FLASH_OPERATION_FAILED;
877 else
878 {
879 i--;
880 retry++;
881 }
882 }
883 }
884 }
885
886 /* if the device doesn't support individual block lock bits set/clear,
887 * all blocks have been unlocked in parallel, so we set those that should be protected
888 */
889 if ((!set) && (!(pri_ext->feature_support & 0x20)))
890 {
891 for (i = 0; i < bank->num_sectors; i++)
892 {
893 if (bank->sectors[i].is_protected == 1)
894 {
895 cfi_intel_clear_status_register(bank);
896
897 cfi_command(bank, 0x60, command);
898 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
899 {
900 return retval;
901 }
902
903 cfi_command(bank, 0x01, command);
904 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
905 {
906 return retval;
907 }
908
909 cfi_intel_wait_status_busy(bank, 100);
910 }
911 }
912 }
913
914 cfi_command(bank, 0xff, command);
915 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
916 }
917
918 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
919 {
920 cfi_flash_bank_t *cfi_info = bank->driver_priv;
921
922 if (bank->target->state != TARGET_HALTED)
923 {
924 LOG_ERROR("Target not halted");
925 return ERROR_TARGET_NOT_HALTED;
926 }
927
928 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
929 {
930 return ERROR_FLASH_SECTOR_INVALID;
931 }
932
933 if (cfi_info->qry[0] != 'Q')
934 return ERROR_FLASH_BANK_NOT_PROBED;
935
936 switch(cfi_info->pri_id)
937 {
938 case 1:
939 case 3:
940 cfi_intel_protect(bank, set, first, last);
941 break;
942 default:
943 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
944 break;
945 }
946
947 return ERROR_OK;
948 }
949
950 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
951 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
952 {
953 /* target_t *target = bank->target; */
954
955 int i;
956
957 /* NOTE:
958 * The data to flash must not be changed in endian! We write a bytestrem in
959 * target byte order already. Only the control and status byte lane of the flash
960 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
961 * word (data seems to be in the upper or lower byte lane for u16 accesses).
962 */
963
964 #if 0
965 if (target->endianness == TARGET_LITTLE_ENDIAN)
966 {
967 #endif
968 /* shift bytes */
969 for (i = 0; i < bank->bus_width - 1; i++)
970 word[i] = word[i + 1];
971 word[bank->bus_width - 1] = byte;
972 #if 0
973 }
974 else
975 {
976 /* shift bytes */
977 for (i = bank->bus_width - 1; i > 0; i--)
978 word[i] = word[i - 1];
979 word[0] = byte;
980 }
981 #endif
982 }
983
984 /* Convert code image to target endian */
985 /* FIXME create general block conversion fcts in target.c?) */
986 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
987 {
988 u32 i;
989 for (i=0; i< count; i++)
990 {
991 target_buffer_set_u32(target, dest, *src);
992 dest+=4;
993 src++;
994 }
995 }
996
997 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
998 {
999 target_t *target = bank->target;
1000
1001 u8 buf[CFI_MAX_BUS_WIDTH];
1002 cfi_command(bank, cmd, buf);
1003 switch (bank->bus_width)
1004 {
1005 case 1 :
1006 return buf[0];
1007 break;
1008 case 2 :
1009 return target_buffer_get_u16(target, buf);
1010 break;
1011 case 4 :
1012 return target_buffer_get_u32(target, buf);
1013 break;
1014 default :
1015 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1016 return 0;
1017 }
1018 }
1019
1020 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1021 {
1022 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1023 target_t *target = bank->target;
1024 reg_param_t reg_params[7];
1025 armv4_5_algorithm_t armv4_5_info;
1026 working_area_t *source;
1027 u32 buffer_size = 32768;
1028 u32 write_command_val, busy_pattern_val, error_pattern_val;
1029
1030 /* algorithm register usage:
1031 * r0: source address (in RAM)
1032 * r1: target address (in Flash)
1033 * r2: count
1034 * r3: flash write command
1035 * r4: status byte (returned to host)
1036 * r5: busy test pattern
1037 * r6: error test pattern
1038 */
1039
1040 static const u32 word_32_code[] = {
1041 0xe4904004, /* loop: ldr r4, [r0], #4 */
1042 0xe5813000, /* str r3, [r1] */
1043 0xe5814000, /* str r4, [r1] */
1044 0xe5914000, /* busy: ldr r4, [r1] */
1045 0xe0047005, /* and r7, r4, r5 */
1046 0xe1570005, /* cmp r7, r5 */
1047 0x1afffffb, /* bne busy */
1048 0xe1140006, /* tst r4, r6 */
1049 0x1a000003, /* bne done */
1050 0xe2522001, /* subs r2, r2, #1 */
1051 0x0a000001, /* beq done */
1052 0xe2811004, /* add r1, r1 #4 */
1053 0xeafffff2, /* b loop */
1054 0xeafffffe /* done: b -2 */
1055 };
1056
1057 static const u32 word_16_code[] = {
1058 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1059 0xe1c130b0, /* strh r3, [r1] */
1060 0xe1c140b0, /* strh r4, [r1] */
1061 0xe1d140b0, /* busy ldrh r4, [r1] */
1062 0xe0047005, /* and r7, r4, r5 */
1063 0xe1570005, /* cmp r7, r5 */
1064 0x1afffffb, /* bne busy */
1065 0xe1140006, /* tst r4, r6 */
1066 0x1a000003, /* bne done */
1067 0xe2522001, /* subs r2, r2, #1 */
1068 0x0a000001, /* beq done */
1069 0xe2811002, /* add r1, r1 #2 */
1070 0xeafffff2, /* b loop */
1071 0xeafffffe /* done: b -2 */
1072 };
1073
1074 static const u32 word_8_code[] = {
1075 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1076 0xe5c13000, /* strb r3, [r1] */
1077 0xe5c14000, /* strb r4, [r1] */
1078 0xe5d14000, /* busy ldrb r4, [r1] */
1079 0xe0047005, /* and r7, r4, r5 */
1080 0xe1570005, /* cmp r7, r5 */
1081 0x1afffffb, /* bne busy */
1082 0xe1140006, /* tst r4, r6 */
1083 0x1a000003, /* bne done */
1084 0xe2522001, /* subs r2, r2, #1 */
1085 0x0a000001, /* beq done */
1086 0xe2811001, /* add r1, r1 #1 */
1087 0xeafffff2, /* b loop */
1088 0xeafffffe /* done: b -2 */
1089 };
1090 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1091 const u32 *target_code_src;
1092 u32 target_code_size;
1093 int retval = ERROR_OK;
1094
1095
1096 cfi_intel_clear_status_register(bank);
1097
1098 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1099 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1100 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1101
1102 /* If we are setting up the write_algorith, we need target_code_src */
1103 /* if not we only need target_code_size. */
1104 /* */
1105 /* However, we don't want to create multiple code paths, so we */
1106 /* do the unecessary evaluation of target_code_src, which the */
1107 /* compiler will probably nicely optimize away if not needed */
1108
1109 /* prepare algorithm code for target endian */
1110 switch (bank->bus_width)
1111 {
1112 case 1 :
1113 target_code_src = word_8_code;
1114 target_code_size = sizeof(word_8_code);
1115 break;
1116 case 2 :
1117 target_code_src = word_16_code;
1118 target_code_size = sizeof(word_16_code);
1119 break;
1120 case 4 :
1121 target_code_src = word_32_code;
1122 target_code_size = sizeof(word_32_code);
1123 break;
1124 default:
1125 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1126 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1127 }
1128
1129 /* flash write code */
1130 if (!cfi_info->write_algorithm)
1131 {
1132 if ( target_code_size > sizeof(target_code) )
1133 {
1134 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1135 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1136 }
1137 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1138
1139 /* Get memory for block write handler */
1140 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1141 if (retval != ERROR_OK)
1142 {
1143 LOG_WARNING("No working area available, can't do block memory writes");
1144 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1145 };
1146
1147 /* write algorithm code to working area */
1148 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1149 if (retval != ERROR_OK)
1150 {
1151 LOG_ERROR("Unable to write block write code to target");
1152 goto cleanup;
1153 }
1154 }
1155
1156 /* Get a workspace buffer for the data to flash starting with 32k size.
1157 Half size until buffer would be smaller 256 Bytem then fail back */
1158 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1159 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1160 {
1161 buffer_size /= 2;
1162 if (buffer_size <= 256)
1163 {
1164 LOG_WARNING("no large enough working area available, can't do block memory writes");
1165 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1166 goto cleanup;
1167 }
1168 };
1169
1170 /* setup algo registers */
1171 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1172 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1173 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1174 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1175 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1176 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1177 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1178
1179 /* prepare command and status register patterns */
1180 write_command_val = cfi_command_val(bank, 0x40);
1181 busy_pattern_val = cfi_command_val(bank, 0x80);
1182 error_pattern_val = cfi_command_val(bank, 0x7e);
1183
1184 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1185
1186 /* Programming main loop */
1187 while (count > 0)
1188 {
1189 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1190 u32 wsm_error;
1191
1192 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1193 {
1194 goto cleanup;
1195 }
1196
1197 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1198 buf_set_u32(reg_params[1].value, 0, 32, address);
1199 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1200
1201 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1202 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1203 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1204
1205 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1206
1207 /* Execute algorithm, assume breakpoint for last instruction */
1208 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1209 cfi_info->write_algorithm->address,
1210 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1211 10000, /* 10s should be enough for max. 32k of data */
1212 &armv4_5_info);
1213
1214 /* On failure try a fall back to direct word writes */
1215 if (retval != ERROR_OK)
1216 {
1217 cfi_intel_clear_status_register(bank);
1218 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1219 retval = ERROR_FLASH_OPERATION_FAILED;
1220 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1221 /* FIXME To allow fall back or recovery, we must save the actual status
1222 somewhere, so that a higher level code can start recovery. */
1223 goto cleanup;
1224 }
1225
1226 /* Check return value from algo code */
1227 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1228 if (wsm_error)
1229 {
1230 /* read status register (outputs debug inforation) */
1231 cfi_intel_wait_status_busy(bank, 100);
1232 cfi_intel_clear_status_register(bank);
1233 retval = ERROR_FLASH_OPERATION_FAILED;
1234 goto cleanup;
1235 }
1236
1237 buffer += thisrun_count;
1238 address += thisrun_count;
1239 count -= thisrun_count;
1240 }
1241
1242 /* free up resources */
1243 cleanup:
1244 if (source)
1245 target_free_working_area(target, source);
1246
1247 if (cfi_info->write_algorithm)
1248 {
1249 target_free_working_area(target, cfi_info->write_algorithm);
1250 cfi_info->write_algorithm = NULL;
1251 }
1252
1253 destroy_reg_param(&reg_params[0]);
1254 destroy_reg_param(&reg_params[1]);
1255 destroy_reg_param(&reg_params[2]);
1256 destroy_reg_param(&reg_params[3]);
1257 destroy_reg_param(&reg_params[4]);
1258 destroy_reg_param(&reg_params[5]);
1259 destroy_reg_param(&reg_params[6]);
1260
1261 return retval;
1262 }
1263
1264 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1265 {
1266 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1267 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1268 target_t *target = bank->target;
1269 reg_param_t reg_params[10];
1270 armv4_5_algorithm_t armv4_5_info;
1271 working_area_t *source;
1272 u32 buffer_size = 32768;
1273 u32 status;
1274 int retval, retvaltemp;
1275 int exit_code = ERROR_OK;
1276
1277 /* input parameters - */
1278 /* R0 = source address */
1279 /* R1 = destination address */
1280 /* R2 = number of writes */
1281 /* R3 = flash write command */
1282 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1283 /* output parameters - */
1284 /* R5 = 0x80 ok 0x00 bad */
1285 /* temp registers - */
1286 /* R6 = value read from flash to test status */
1287 /* R7 = holding register */
1288 /* unlock registers - */
1289 /* R8 = unlock1_addr */
1290 /* R9 = unlock1_cmd */
1291 /* R10 = unlock2_addr */
1292 /* R11 = unlock2_cmd */
1293
1294 static const u32 word_32_code[] = {
1295 /* 00008100 <sp_32_code>: */
1296 0xe4905004, /* ldr r5, [r0], #4 */
1297 0xe5889000, /* str r9, [r8] */
1298 0xe58ab000, /* str r11, [r10] */
1299 0xe5883000, /* str r3, [r8] */
1300 0xe5815000, /* str r5, [r1] */
1301 0xe1a00000, /* nop */
1302 /* */
1303 /* 00008110 <sp_32_busy>: */
1304 0xe5916000, /* ldr r6, [r1] */
1305 0xe0257006, /* eor r7, r5, r6 */
1306 0xe0147007, /* ands r7, r4, r7 */
1307 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1308 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1309 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1310 0xe5916000, /* ldr r6, [r1] */
1311 0xe0257006, /* eor r7, r5, r6 */
1312 0xe0147007, /* ands r7, r4, r7 */
1313 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1314 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1315 0x1a000004, /* bne 8154 <sp_32_done> */
1316 /* */
1317 /* 00008140 <sp_32_cont>: */
1318 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1319 0x03a05080, /* moveq r5, #128 ; 0x80 */
1320 0x0a000001, /* beq 8154 <sp_32_done> */
1321 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1322 0xeaffffe8, /* b 8100 <sp_32_code> */
1323 /* */
1324 /* 00008154 <sp_32_done>: */
1325 0xeafffffe /* b 8154 <sp_32_done> */
1326 };
1327
1328 static const u32 word_16_code[] = {
1329 /* 00008158 <sp_16_code>: */
1330 0xe0d050b2, /* ldrh r5, [r0], #2 */
1331 0xe1c890b0, /* strh r9, [r8] */
1332 0xe1cab0b0, /* strh r11, [r10] */
1333 0xe1c830b0, /* strh r3, [r8] */
1334 0xe1c150b0, /* strh r5, [r1] */
1335 0xe1a00000, /* nop (mov r0,r0) */
1336 /* */
1337 /* 00008168 <sp_16_busy>: */
1338 0xe1d160b0, /* ldrh r6, [r1] */
1339 0xe0257006, /* eor r7, r5, r6 */
1340 0xe0147007, /* ands r7, r4, r7 */
1341 0x0a000007, /* beq 8198 <sp_16_cont> */
1342 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1343 0x0afffff9, /* beq 8168 <sp_16_busy> */
1344 0xe1d160b0, /* ldrh r6, [r1] */
1345 0xe0257006, /* eor r7, r5, r6 */
1346 0xe0147007, /* ands r7, r4, r7 */
1347 0x0a000001, /* beq 8198 <sp_16_cont> */
1348 0xe3a05000, /* mov r5, #0 ; 0x0 */
1349 0x1a000004, /* bne 81ac <sp_16_done> */
1350 /* */
1351 /* 00008198 <sp_16_cont>: */
1352 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1353 0x03a05080, /* moveq r5, #128 ; 0x80 */
1354 0x0a000001, /* beq 81ac <sp_16_done> */
1355 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1356 0xeaffffe8, /* b 8158 <sp_16_code> */
1357 /* */
1358 /* 000081ac <sp_16_done>: */
1359 0xeafffffe /* b 81ac <sp_16_done> */
1360 };
1361
1362 static const u32 word_8_code[] = {
1363 /* 000081b0 <sp_16_code_end>: */
1364 0xe4d05001, /* ldrb r5, [r0], #1 */
1365 0xe5c89000, /* strb r9, [r8] */
1366 0xe5cab000, /* strb r11, [r10] */
1367 0xe5c83000, /* strb r3, [r8] */
1368 0xe5c15000, /* strb r5, [r1] */
1369 0xe1a00000, /* nop (mov r0,r0) */
1370 /* */
1371 /* 000081c0 <sp_8_busy>: */
1372 0xe5d16000, /* ldrb r6, [r1] */
1373 0xe0257006, /* eor r7, r5, r6 */
1374 0xe0147007, /* ands r7, r4, r7 */
1375 0x0a000007, /* beq 81f0 <sp_8_cont> */
1376 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1377 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1378 0xe5d16000, /* ldrb r6, [r1] */
1379 0xe0257006, /* eor r7, r5, r6 */
1380 0xe0147007, /* ands r7, r4, r7 */
1381 0x0a000001, /* beq 81f0 <sp_8_cont> */
1382 0xe3a05000, /* mov r5, #0 ; 0x0 */
1383 0x1a000004, /* bne 8204 <sp_8_done> */
1384 /* */
1385 /* 000081f0 <sp_8_cont>: */
1386 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1387 0x03a05080, /* moveq r5, #128 ; 0x80 */
1388 0x0a000001, /* beq 8204 <sp_8_done> */
1389 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1390 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1391 /* */
1392 /* 00008204 <sp_8_done>: */
1393 0xeafffffe /* b 8204 <sp_8_done> */
1394 };
1395
1396 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1397 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1398 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1399
1400 /* flash write code */
1401 if (!cfi_info->write_algorithm)
1402 {
1403 u8 *target_code;
1404 int target_code_size;
1405 const u32 *src;
1406
1407 /* convert bus-width dependent algorithm code to correct endiannes */
1408 switch (bank->bus_width)
1409 {
1410 case 1:
1411 src = word_8_code;
1412 target_code_size = sizeof(word_8_code);
1413 break;
1414 case 2:
1415 src = word_16_code;
1416 target_code_size = sizeof(word_16_code);
1417 break;
1418 case 4:
1419 src = word_32_code;
1420 target_code_size = sizeof(word_32_code);
1421 break;
1422 default:
1423 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1424 return ERROR_FLASH_OPERATION_FAILED;
1425 }
1426 target_code = malloc(target_code_size);
1427 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1428
1429 /* allocate working area */
1430 retval=target_alloc_working_area(target, target_code_size,
1431 &cfi_info->write_algorithm);
1432 if (retval != ERROR_OK)
1433 {
1434 free(target_code);
1435 return retval;
1436 }
1437
1438 /* write algorithm code to working area */
1439 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1440 target_code_size, target_code)) != ERROR_OK)
1441 {
1442 free(target_code);
1443 return retval;
1444 }
1445
1446 free(target_code);
1447 }
1448 /* the following code still assumes target code is fixed 24*4 bytes */
1449
1450 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1451 {
1452 buffer_size /= 2;
1453 if (buffer_size <= 256)
1454 {
1455 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1456 if (cfi_info->write_algorithm)
1457 target_free_working_area(target, cfi_info->write_algorithm);
1458
1459 LOG_WARNING("not enough working area available, can't do block memory writes");
1460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1461 }
1462 };
1463
1464 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1465 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1466 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1467 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1468 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1469 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1470 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1471 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1472 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1473 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1474
1475 while (count > 0)
1476 {
1477 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1478
1479 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1480
1481 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1482 buf_set_u32(reg_params[1].value, 0, 32, address);
1483 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1484 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1485 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1486 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1487 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1488 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1489 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1490
1491 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1492 cfi_info->write_algorithm->address,
1493 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1494 10000, &armv4_5_info);
1495
1496 status = buf_get_u32(reg_params[5].value, 0, 32);
1497
1498 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1499 {
1500 LOG_DEBUG("status: 0x%x", status);
1501 exit_code = ERROR_FLASH_OPERATION_FAILED;
1502 break;
1503 }
1504
1505 buffer += thisrun_count;
1506 address += thisrun_count;
1507 count -= thisrun_count;
1508 }
1509
1510 target_free_working_area(target, source);
1511
1512 destroy_reg_param(&reg_params[0]);
1513 destroy_reg_param(&reg_params[1]);
1514 destroy_reg_param(&reg_params[2]);
1515 destroy_reg_param(&reg_params[3]);
1516 destroy_reg_param(&reg_params[4]);
1517 destroy_reg_param(&reg_params[5]);
1518 destroy_reg_param(&reg_params[6]);
1519 destroy_reg_param(&reg_params[7]);
1520 destroy_reg_param(&reg_params[8]);
1521 destroy_reg_param(&reg_params[9]);
1522
1523 return exit_code;
1524 }
1525
1526 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1527 {
1528 int retval;
1529 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1530 target_t *target = bank->target;
1531 u8 command[8];
1532
1533 cfi_intel_clear_status_register(bank);
1534 cfi_command(bank, 0x40, command);
1535 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1536 {
1537 return retval;
1538 }
1539
1540 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1541 {
1542 return retval;
1543 }
1544
1545 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1546 {
1547 cfi_command(bank, 0xff, command);
1548 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1549 {
1550 return retval;
1551 }
1552
1553 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1554 return ERROR_FLASH_OPERATION_FAILED;
1555 }
1556
1557 return ERROR_OK;
1558 }
1559
1560 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1561 {
1562 int retval;
1563 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1564 target_t *target = bank->target;
1565 u8 command[8];
1566
1567 /* Calculate buffer size and boundary mask */
1568 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1569 u32 buffermask = buffersize-1;
1570 u32 bufferwsize;
1571
1572 /* Check for valid range */
1573 if (address & buffermask)
1574 {
1575 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1576 return ERROR_FLASH_OPERATION_FAILED;
1577 }
1578 switch(bank->chip_width)
1579 {
1580 case 4 : bufferwsize = buffersize / 4; break;
1581 case 2 : bufferwsize = buffersize / 2; break;
1582 case 1 : bufferwsize = buffersize; break;
1583 default:
1584 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1585 return ERROR_FLASH_OPERATION_FAILED;
1586 }
1587
1588 bufferwsize/=(bank->bus_width / bank->chip_width);
1589
1590
1591 /* Check for valid size */
1592 if (wordcount > bufferwsize)
1593 {
1594 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1595 return ERROR_FLASH_OPERATION_FAILED;
1596 }
1597
1598 /* Write to flash buffer */
1599 cfi_intel_clear_status_register(bank);
1600
1601 /* Initiate buffer operation _*/
1602 cfi_command(bank, 0xE8, command);
1603 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1604 {
1605 return retval;
1606 }
1607 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1608 {
1609 cfi_command(bank, 0xff, command);
1610 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1611 {
1612 return retval;
1613 }
1614
1615 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1616 return ERROR_FLASH_OPERATION_FAILED;
1617 }
1618
1619 /* Write buffer wordcount-1 and data words */
1620 cfi_command(bank, bufferwsize-1, command);
1621 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1622 {
1623 return retval;
1624 }
1625
1626 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1627 {
1628 return retval;
1629 }
1630
1631 /* Commit write operation */
1632 cfi_command(bank, 0xd0, command);
1633 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1634 {
1635 return retval;
1636 }
1637 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1638 {
1639 cfi_command(bank, 0xff, command);
1640 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1641 {
1642 return retval;
1643 }
1644
1645 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1646 return ERROR_FLASH_OPERATION_FAILED;
1647 }
1648
1649 return ERROR_OK;
1650 }
1651
1652 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1653 {
1654 int retval;
1655 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1656 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1657 target_t *target = bank->target;
1658 u8 command[8];
1659
1660 cfi_command(bank, 0xaa, command);
1661 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1662 {
1663 return retval;
1664 }
1665
1666 cfi_command(bank, 0x55, command);
1667 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1668 {
1669 return retval;
1670 }
1671
1672 cfi_command(bank, 0xa0, command);
1673 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1674 {
1675 return retval;
1676 }
1677
1678 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1679 {
1680 return retval;
1681 }
1682
1683 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1684 {
1685 cfi_command(bank, 0xf0, command);
1686 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1687 {
1688 return retval;
1689 }
1690
1691 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1692 return ERROR_FLASH_OPERATION_FAILED;
1693 }
1694
1695 return ERROR_OK;
1696 }
1697
1698 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1699 {
1700 int retval;
1701 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1702 target_t *target = bank->target;
1703 u8 command[8];
1704 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1705
1706 /* Calculate buffer size and boundary mask */
1707 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1708 u32 buffermask = buffersize-1;
1709 u32 bufferwsize;
1710
1711 /* Check for valid range */
1712 if (address & buffermask)
1713 {
1714 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1715 return ERROR_FLASH_OPERATION_FAILED;
1716 }
1717 switch(bank->chip_width)
1718 {
1719 case 4 : bufferwsize = buffersize / 4; break;
1720 case 2 : bufferwsize = buffersize / 2; break;
1721 case 1 : bufferwsize = buffersize; break;
1722 default:
1723 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1724 return ERROR_FLASH_OPERATION_FAILED;
1725 }
1726
1727 bufferwsize/=(bank->bus_width / bank->chip_width);
1728
1729 /* Check for valid size */
1730 if (wordcount > bufferwsize)
1731 {
1732 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1733 return ERROR_FLASH_OPERATION_FAILED;
1734 }
1735
1736 // Unlock
1737 cfi_command(bank, 0xaa, command);
1738 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1739 {
1740 return retval;
1741 }
1742
1743 cfi_command(bank, 0x55, command);
1744 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1745 {
1746 return retval;
1747 }
1748
1749 // Buffer load command
1750 cfi_command(bank, 0x25, command);
1751 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1752 {
1753 return retval;
1754 }
1755
1756 /* Write buffer wordcount-1 and data words */
1757 cfi_command(bank, bufferwsize-1, command);
1758 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1759 {
1760 return retval;
1761 }
1762
1763 if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1764 {
1765 return retval;
1766 }
1767
1768 /* Commit write operation */
1769 cfi_command(bank, 0x29, command);
1770 if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1771 {
1772 return retval;
1773 }
1774
1775 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1776 {
1777 cfi_command(bank, 0xf0, command);
1778 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1779 {
1780 return retval;
1781 }
1782
1783 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1784 return ERROR_FLASH_OPERATION_FAILED;
1785 }
1786
1787 return ERROR_OK;
1788 }
1789
1790 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1791 {
1792 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1793
1794 switch(cfi_info->pri_id)
1795 {
1796 case 1:
1797 case 3:
1798 return cfi_intel_write_word(bank, word, address);
1799 break;
1800 case 2:
1801 return cfi_spansion_write_word(bank, word, address);
1802 break;
1803 default:
1804 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1805 break;
1806 }
1807
1808 return ERROR_FLASH_OPERATION_FAILED;
1809 }
1810
1811 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1812 {
1813 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1814
1815 switch(cfi_info->pri_id)
1816 {
1817 case 1:
1818 case 3:
1819 return cfi_intel_write_words(bank, word, wordcount, address);
1820 break;
1821 case 2:
1822 return cfi_spansion_write_words(bank, word, wordcount, address);
1823 break;
1824 default:
1825 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1826 break;
1827 }
1828
1829 return ERROR_FLASH_OPERATION_FAILED;
1830 }
1831
1832 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1833 {
1834 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1835 target_t *target = bank->target;
1836 u32 address = bank->base + offset; /* address of first byte to be programmed */
1837 u32 write_p, copy_p;
1838 int align; /* number of unaligned bytes */
1839 int blk_count; /* number of bus_width bytes for block copy */
1840 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1841 int i;
1842 int retval;
1843
1844 if (bank->target->state != TARGET_HALTED)
1845 {
1846 LOG_ERROR("Target not halted");
1847 return ERROR_TARGET_NOT_HALTED;
1848 }
1849
1850 if (offset + count > bank->size)
1851 return ERROR_FLASH_DST_OUT_OF_BANK;
1852
1853 if (cfi_info->qry[0] != 'Q')
1854 return ERROR_FLASH_BANK_NOT_PROBED;
1855
1856 /* start at the first byte of the first word (bus_width size) */
1857 write_p = address & ~(bank->bus_width - 1);
1858 if ((align = address - write_p) != 0)
1859 {
1860 LOG_INFO("Fixup %d unaligned head bytes", align );
1861
1862 for (i = 0; i < bank->bus_width; i++)
1863 current_word[i] = 0;
1864 copy_p = write_p;
1865
1866 /* copy bytes before the first write address */
1867 for (i = 0; i < align; ++i, ++copy_p)
1868 {
1869 u8 byte;
1870 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1871 {
1872 return retval;
1873 }
1874 cfi_add_byte(bank, current_word, byte);
1875 }
1876
1877 /* add bytes from the buffer */
1878 for (; (i < bank->bus_width) && (count > 0); i++)
1879 {
1880 cfi_add_byte(bank, current_word, *buffer++);
1881 count--;
1882 copy_p++;
1883 }
1884
1885 /* if the buffer is already finished, copy bytes after the last write address */
1886 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1887 {
1888 u8 byte;
1889 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1890 {
1891 return retval;
1892 }
1893 cfi_add_byte(bank, current_word, byte);
1894 }
1895
1896 retval = cfi_write_word(bank, current_word, write_p);
1897 if (retval != ERROR_OK)
1898 return retval;
1899 write_p = copy_p;
1900 }
1901
1902 /* handle blocks of bus_size aligned bytes */
1903 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1904 switch(cfi_info->pri_id)
1905 {
1906 /* try block writes (fails without working area) */
1907 case 1:
1908 case 3:
1909 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1910 break;
1911 case 2:
1912 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1913 break;
1914 default:
1915 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1916 retval = ERROR_FLASH_OPERATION_FAILED;
1917 break;
1918 }
1919 if (retval == ERROR_OK)
1920 {
1921 /* Increment pointers and decrease count on succesful block write */
1922 buffer += blk_count;
1923 write_p += blk_count;
1924 count -= blk_count;
1925 }
1926 else
1927 {
1928 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1929 {
1930 //adjust buffersize for chip width
1931 u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1932 u32 buffermask = buffersize-1;
1933 u32 bufferwsize;
1934
1935 switch(bank->chip_width)
1936 {
1937 case 4 : bufferwsize = buffersize / 4; break;
1938 case 2 : bufferwsize = buffersize / 2; break;
1939 case 1 : bufferwsize = buffersize; break;
1940 default:
1941 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1942 return ERROR_FLASH_OPERATION_FAILED;
1943 }
1944
1945 bufferwsize/=(bank->bus_width / bank->chip_width);
1946
1947 /* fall back to memory writes */
1948 while (count >= (u32)bank->bus_width)
1949 {
1950 int fallback;
1951 if ((write_p & 0xff) == 0)
1952 {
1953 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1954 }
1955 fallback = 1;
1956 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1957 {
1958 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1959 if (retval == ERROR_OK)
1960 {
1961 buffer += buffersize;
1962 write_p += buffersize;
1963 count -= buffersize;
1964 fallback=0;
1965 }
1966 }
1967 /* try the slow way? */
1968 if (fallback)
1969 {
1970 for (i = 0; i < bank->bus_width; i++)
1971 current_word[i] = 0;
1972
1973 for (i = 0; i < bank->bus_width; i++)
1974 {
1975 cfi_add_byte(bank, current_word, *buffer++);
1976 }
1977
1978 retval = cfi_write_word(bank, current_word, write_p);
1979 if (retval != ERROR_OK)
1980 return retval;
1981
1982 write_p += bank->bus_width;
1983 count -= bank->bus_width;
1984 }
1985 }
1986 }
1987 else
1988 return retval;
1989 }
1990
1991 /* return to read array mode, so we can read from flash again for padding */
1992 cfi_command(bank, 0xf0, current_word);
1993 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
1994 {
1995 return retval;
1996 }
1997 cfi_command(bank, 0xff, current_word);
1998 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
1999 {
2000 return retval;
2001 }
2002
2003 /* handle unaligned tail bytes */
2004 if (count > 0)
2005 {
2006 LOG_INFO("Fixup %d unaligned tail bytes", count );
2007
2008 copy_p = write_p;
2009 for (i = 0; i < bank->bus_width; i++)
2010 current_word[i] = 0;
2011
2012 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2013 {
2014 cfi_add_byte(bank, current_word, *buffer++);
2015 count--;
2016 }
2017 for (; i < bank->bus_width; ++i, ++copy_p)
2018 {
2019 u8 byte;
2020 if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2021 {
2022 return retval;
2023 }
2024 cfi_add_byte(bank, current_word, byte);
2025 }
2026 retval = cfi_write_word(bank, current_word, write_p);
2027 if (retval != ERROR_OK)
2028 return retval;
2029 }
2030
2031 /* return to read array mode */
2032 cfi_command(bank, 0xf0, current_word);
2033 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2034 {
2035 return retval;
2036 }
2037 cfi_command(bank, 0xff, current_word);
2038 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2039 }
2040
2041 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2042 {
2043 (void) param;
2044 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2045 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2046
2047 pri_ext->_reversed_geometry = 1;
2048 }
2049
2050 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2051 {
2052 int i;
2053 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2054 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2055 (void) param;
2056
2057 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2058 {
2059 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2060
2061 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2062 {
2063 int j = (cfi_info->num_erase_regions - 1) - i;
2064 u32 swap;
2065
2066 swap = cfi_info->erase_region_info[i];
2067 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2068 cfi_info->erase_region_info[j] = swap;
2069 }
2070 }
2071 }
2072
2073 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2074 {
2075 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2076 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2077 cfi_unlock_addresses_t *unlock_addresses = param;
2078
2079 pri_ext->_unlock1 = unlock_addresses->unlock1;
2080 pri_ext->_unlock2 = unlock_addresses->unlock2;
2081 }
2082
2083 static int cfi_probe(struct flash_bank_s *bank)
2084 {
2085 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2086 target_t *target = bank->target;
2087 u8 command[8];
2088 int num_sectors = 0;
2089 int i;
2090 int sector = 0;
2091 u32 unlock1 = 0x555;
2092 u32 unlock2 = 0x2aa;
2093 int retval;
2094
2095 if (bank->target->state != TARGET_HALTED)
2096 {
2097 LOG_ERROR("Target not halted");
2098 return ERROR_TARGET_NOT_HALTED;
2099 }
2100
2101 cfi_info->probed = 0;
2102
2103 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2104 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2105 */
2106 if (cfi_info->jedec_probe)
2107 {
2108 unlock1 = 0x5555;
2109 unlock2 = 0x2aaa;
2110 }
2111
2112 /* switch to read identifier codes mode ("AUTOSELECT") */
2113 cfi_command(bank, 0xaa, command);
2114 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2115 {
2116 return retval;
2117 }
2118 cfi_command(bank, 0x55, command);
2119 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2120 {
2121 return retval;
2122 }
2123 cfi_command(bank, 0x90, command);
2124 if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2125 {
2126 return retval;
2127 }
2128
2129 if (bank->chip_width == 1)
2130 {
2131 u8 manufacturer, device_id;
2132 if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
2133 {
2134 return retval;
2135 }
2136 if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
2137 {
2138 return retval;
2139 }
2140 cfi_info->manufacturer = manufacturer;
2141 cfi_info->device_id = device_id;
2142 }
2143 else if (bank->chip_width == 2)
2144 {
2145 if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
2146 {
2147 return retval;
2148 }
2149 if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
2150 {
2151 return retval;
2152 }
2153 }
2154
2155 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2156 /* switch back to read array mode */
2157 cfi_command(bank, 0xf0, command);
2158 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2159 {
2160 return retval;
2161 }
2162 cfi_command(bank, 0xff, command);
2163 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2164 {
2165 return retval;
2166 }
2167
2168 /* check device/manufacturer ID for known non-CFI flashes. */
2169 cfi_fixup_non_cfi(bank);
2170
2171 /* query only if this is a CFI compatible flash,
2172 * otherwise the relevant info has already been filled in
2173 */
2174 if (cfi_info->not_cfi == 0)
2175 {
2176 /* enter CFI query mode
2177 * according to JEDEC Standard No. 68.01,
2178 * a single bus sequence with address = 0x55, data = 0x98 should put
2179 * the device into CFI query mode.
2180 *
2181 * SST flashes clearly violate this, and we will consider them incompatbile for now
2182 */
2183 cfi_command(bank, 0x98, command);
2184 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2185 {
2186 return retval;
2187 }
2188
2189 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2190 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2191 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2192
2193 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2194
2195 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2196 {
2197 cfi_command(bank, 0xf0, command);
2198 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2199 {
2200 return retval;
2201 }
2202 cfi_command(bank, 0xff, command);
2203 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2204 {
2205 return retval;
2206 }
2207 LOG_ERROR("Could not probe bank: no QRY");
2208 return ERROR_FLASH_BANK_INVALID;
2209 }
2210
2211 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2212 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2213 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2214 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2215
2216 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2217
2218 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2219 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2220 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2221 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2222 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2223 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2224 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2225 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2226 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2227 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2228 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2229 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2230
2231 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2232 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2233 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2234 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2235 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2236 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2237 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2238 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2239 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2240 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2241 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2242
2243 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2244 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2245 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2246 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2247
2248 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2249
2250 if (cfi_info->num_erase_regions)
2251 {
2252 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2253 for (i = 0; i < cfi_info->num_erase_regions; i++)
2254 {
2255 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2256 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2257 }
2258 }
2259 else
2260 {
2261 cfi_info->erase_region_info = NULL;
2262 }
2263
2264 /* We need to read the primary algorithm extended query table before calculating
2265 * the sector layout to be able to apply fixups
2266 */
2267 switch(cfi_info->pri_id)
2268 {
2269 /* Intel command set (standard and extended) */
2270 case 0x0001:
2271 case 0x0003:
2272 cfi_read_intel_pri_ext(bank);
2273 break;
2274 /* AMD/Spansion, Atmel, ... command set */
2275 case 0x0002:
2276 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2277 cfi_read_0002_pri_ext(bank);
2278 break;
2279 default:
2280 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2281 break;
2282 }
2283
2284 /* return to read array mode
2285 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2286 */
2287 cfi_command(bank, 0xf0, command);
2288 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2289 {
2290 return retval;
2291 }
2292 cfi_command(bank, 0xff, command);
2293 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2294 {
2295 return retval;
2296 }
2297 } /* end CFI case */
2298
2299 /* apply fixups depending on the primary command set */
2300 switch(cfi_info->pri_id)
2301 {
2302 /* Intel command set (standard and extended) */
2303 case 0x0001:
2304 case 0x0003:
2305 cfi_fixup(bank, cfi_0001_fixups);
2306 break;
2307 /* AMD/Spansion, Atmel, ... command set */
2308 case 0x0002:
2309 cfi_fixup(bank, cfi_0002_fixups);
2310 break;
2311 default:
2312 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2313 break;
2314 }
2315
2316 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2317 {
2318 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2319 }
2320
2321 if (cfi_info->num_erase_regions == 0)
2322 {
2323 /* a device might have only one erase block, spanning the whole device */
2324 bank->num_sectors = 1;
2325 bank->sectors = malloc(sizeof(flash_sector_t));
2326
2327 bank->sectors[sector].offset = 0x0;
2328 bank->sectors[sector].size = bank->size;
2329 bank->sectors[sector].is_erased = -1;
2330 bank->sectors[sector].is_protected = -1;
2331 }
2332 else
2333 {
2334 u32 offset = 0;
2335
2336 for (i = 0; i < cfi_info->num_erase_regions; i++)
2337 {
2338 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2339 }
2340
2341 bank->num_sectors = num_sectors;
2342 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2343
2344 for (i = 0; i < cfi_info->num_erase_regions; i++)
2345 {
2346 u32 j;
2347 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2348 {
2349 bank->sectors[sector].offset = offset;
2350 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2351 offset += bank->sectors[sector].size;
2352 bank->sectors[sector].is_erased = -1;
2353 bank->sectors[sector].is_protected = -1;
2354 sector++;
2355 }
2356 }
2357 if (offset != cfi_info->dev_size)
2358 {
2359 LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2360 }
2361 }
2362
2363 cfi_info->probed = 1;
2364
2365 return ERROR_OK;
2366 }
2367
2368 static int cfi_auto_probe(struct flash_bank_s *bank)
2369 {
2370 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2371 if (cfi_info->probed)
2372 return ERROR_OK;
2373 return cfi_probe(bank);
2374 }
2375
2376
2377 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2378 {
2379 int retval;
2380 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2381 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2382 target_t *target = bank->target;
2383 u8 command[CFI_MAX_BUS_WIDTH];
2384 int i;
2385
2386 /* check if block lock bits are supported on this device */
2387 if (!(pri_ext->blk_status_reg_mask & 0x1))
2388 return ERROR_FLASH_OPERATION_FAILED;
2389
2390 cfi_command(bank, 0x90, command);
2391 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2392 {
2393 return retval;
2394 }
2395
2396 for (i = 0; i < bank->num_sectors; i++)
2397 {
2398 u8 block_status = cfi_get_u8(bank, i, 0x2);
2399
2400 if (block_status & 1)
2401 bank->sectors[i].is_protected = 1;
2402 else
2403 bank->sectors[i].is_protected = 0;
2404 }
2405
2406 cfi_command(bank, 0xff, command);
2407 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2408 }
2409
2410 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2411 {
2412 int retval;
2413 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2414 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2415 target_t *target = bank->target;
2416 u8 command[8];
2417 int i;
2418
2419 cfi_command(bank, 0xaa, command);
2420 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2421 {
2422 return retval;
2423 }
2424
2425 cfi_command(bank, 0x55, command);
2426 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2427 {
2428 return retval;
2429 }
2430
2431 cfi_command(bank, 0x90, command);
2432 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2433 {
2434 return retval;
2435 }
2436
2437 for (i = 0; i < bank->num_sectors; i++)
2438 {
2439 u8 block_status = cfi_get_u8(bank, i, 0x2);
2440
2441 if (block_status & 1)
2442 bank->sectors[i].is_protected = 1;
2443 else
2444 bank->sectors[i].is_protected = 0;
2445 }
2446
2447 cfi_command(bank, 0xf0, command);
2448 return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2449 }
2450
2451 static int cfi_protect_check(struct flash_bank_s *bank)
2452 {
2453 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2454
2455 if (bank->target->state != TARGET_HALTED)
2456 {
2457 LOG_ERROR("Target not halted");
2458 return ERROR_TARGET_NOT_HALTED;
2459 }
2460
2461 if (cfi_info->qry[0] != 'Q')
2462 return ERROR_FLASH_BANK_NOT_PROBED;
2463
2464 switch(cfi_info->pri_id)
2465 {
2466 case 1:
2467 case 3:
2468 return cfi_intel_protect_check(bank);
2469 break;
2470 case 2:
2471 return cfi_spansion_protect_check(bank);
2472 break;
2473 default:
2474 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2475 break;
2476 }
2477
2478 return ERROR_OK;
2479 }
2480
2481 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2482 {
2483 int printed;
2484 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2485
2486 if (cfi_info->qry[0] == (char)-1)
2487 {
2488 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2489 return ERROR_OK;
2490 }
2491
2492 if (cfi_info->not_cfi == 0)
2493 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2494 else
2495 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2496 buf += printed;
2497 buf_size -= printed;
2498
2499 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2500 cfi_info->manufacturer, cfi_info->device_id);
2501 buf += printed;
2502 buf_size -= printed;
2503
2504 if (cfi_info->not_cfi == 0)
2505 {
2506 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2507 buf += printed;
2508 buf_size -= printed;
2509
2510 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2511 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2512 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2513 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2514 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2515 buf += printed;
2516 buf_size -= printed;
2517
2518 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2519 1 << cfi_info->word_write_timeout_typ,
2520 1 << cfi_info->buf_write_timeout_typ,
2521 1 << cfi_info->block_erase_timeout_typ,
2522 1 << cfi_info->chip_erase_timeout_typ);
2523 buf += printed;
2524 buf_size -= printed;
2525
2526 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2527 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2528 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2529 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2530 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2531 buf += printed;
2532 buf_size -= printed;
2533
2534 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2535 cfi_info->dev_size,
2536 cfi_info->interface_desc,
2537 1 << cfi_info->max_buf_write_size);
2538 buf += printed;
2539 buf_size -= printed;
2540
2541 switch(cfi_info->pri_id)
2542 {
2543 case 1:
2544 case 3:
2545 cfi_intel_info(bank, buf, buf_size);
2546 break;
2547 case 2:
2548 cfi_spansion_info(bank, buf, buf_size);
2549 break;
2550 default:
2551 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2552 break;
2553 }
2554 }
2555
2556 return ERROR_OK;
2557 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)