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[openocd.git] / lpc3180.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "imp.h"
25 #include "lpc3180.h"
26 #include <target/target.h>
27
28
29 static int lpc3180_reset(struct nand_device *nand);
30 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
31
32 /* nand device lpc3180 <target#> <oscillator_frequency>
33 */
34 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
35 {
36 if (CMD_ARGC < 3)
37 {
38 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
39 return ERROR_FLASH_BANK_INVALID;
40 }
41
42 struct target *target = get_target(CMD_ARGV[1]);
43 if (NULL == target)
44 {
45 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
46 return ERROR_NAND_DEVICE_INVALID;
47 }
48
49 uint32_t osc_freq;
50 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
51
52 struct lpc3180_nand_controller *lpc3180_info;
53 lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
54 nand->controller_priv = lpc3180_info;
55
56 lpc3180_info->target = target;
57 lpc3180_info->osc_freq = osc_freq;
58
59 if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
60 {
61 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
62 }
63 lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
64 lpc3180_info->sw_write_protection = 0;
65 lpc3180_info->sw_wp_lower_bound = 0x0;
66 lpc3180_info->sw_wp_upper_bound = 0x0;
67
68 return ERROR_OK;
69 }
70
71 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
72 {
73 int bypass = (pll_ctrl & 0x8000) >> 15;
74 int direct = (pll_ctrl & 0x4000) >> 14;
75 int feedback = (pll_ctrl & 0x2000) >> 13;
76 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
77 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
78 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
79 int lock = (pll_ctrl & 0x1);
80
81 if (!lock)
82 LOG_WARNING("PLL is not locked");
83
84 if (!bypass && direct) /* direct mode */
85 return (m * fclkin) / n;
86
87 if (bypass && !direct) /* bypass mode */
88 return fclkin / (2 * p);
89
90 if (bypass & direct) /* direct bypass mode */
91 return fclkin;
92
93 if (feedback) /* integer mode */
94 return m * (fclkin / n);
95 else /* non-integer mode */
96 return (m / (2 * p)) * (fclkin / n);
97 }
98
99 static float lpc3180_cycle_time(struct lpc3180_nand_controller *lpc3180_info)
100 {
101 struct target *target = lpc3180_info->target;
102 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
103 int sysclk;
104 int hclk;
105 int hclk_pll;
106 float cycle;
107
108 /* calculate timings */
109
110 /* determine current SYSCLK (13'MHz or main oscillator) */
111 target_read_u32(target, 0x40004050, &sysclk_ctrl);
112
113 if ((sysclk_ctrl & 1) == 0)
114 sysclk = lpc3180_info->osc_freq;
115 else
116 sysclk = 13000;
117
118 /* determine selected HCLK source */
119 target_read_u32(target, 0x40004044, &pwr_ctrl);
120
121 if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
122 {
123 hclk = sysclk;
124 }
125 else
126 {
127 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
128 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
129
130 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
131
132 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
133 {
134 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
135 }
136 else /* HCLK uses HCLK_PLL */
137 {
138 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
139 }
140 }
141
142 LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
143
144 cycle = (1.0 / hclk) * 1000000.0;
145
146 return cycle;
147 }
148
149 static int lpc3180_init(struct nand_device *nand)
150 {
151 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
152 struct target *target = lpc3180_info->target;
153 int bus_width = nand->bus_width ? : 8;
154 int address_cycles = nand->address_cycles ? : 3;
155 int page_size = nand->page_size ? : 512;
156
157 if (target->state != TARGET_HALTED)
158 {
159 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
160 return ERROR_NAND_OPERATION_FAILED;
161 }
162
163 /* sanitize arguments */
164 if ((bus_width != 8) && (bus_width != 16))
165 {
166 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
167 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
168 }
169
170 /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
171 * would support 16 bit, too, so we just warn about this for now
172 */
173 if (bus_width == 16)
174 {
175 LOG_WARNING("LPC3180 only supports 8 bit bus width");
176 }
177
178 /* inform calling code about selected bus width */
179 nand->bus_width = bus_width;
180
181 if ((address_cycles != 3) && (address_cycles != 4))
182 {
183 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
184 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
185 }
186
187 if ((page_size != 512) && (page_size != 2048))
188 {
189 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
190 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
191 }
192
193 /* select MLC controller if none is currently selected */
194 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
195 {
196 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
197 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
198 }
199
200 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
201 {
202 uint32_t mlc_icr_value = 0x0;
203 float cycle;
204 int twp, twh, trp, treh, trhz, trbwb, tcea;
205
206 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
207 target_write_u32(target, 0x400040c8, 0x22);
208
209 /* MLC_CEH = 0x0 (Force nCE assert) */
210 target_write_u32(target, 0x200b804c, 0x0);
211
212 /* MLC_LOCK = 0xa25e (unlock protected registers) */
213 target_write_u32(target, 0x200b8044, 0xa25e);
214
215 /* MLC_ICR = configuration */
216 if (lpc3180_info->sw_write_protection)
217 mlc_icr_value |= 0x8;
218 if (page_size == 2048)
219 mlc_icr_value |= 0x4;
220 if (address_cycles == 4)
221 mlc_icr_value |= 0x2;
222 if (bus_width == 16)
223 mlc_icr_value |= 0x1;
224 target_write_u32(target, 0x200b8030, mlc_icr_value);
225
226 /* calculate NAND controller timings */
227 cycle = lpc3180_cycle_time(lpc3180_info);
228
229 twp = ((40 / cycle) + 1);
230 twh = ((20 / cycle) + 1);
231 trp = ((30 / cycle) + 1);
232 treh = ((15 / cycle) + 1);
233 trhz = ((30 / cycle) + 1);
234 trbwb = ((100 / cycle) + 1);
235 tcea = ((45 / cycle) + 1);
236
237 /* MLC_LOCK = 0xa25e (unlock protected registers) */
238 target_write_u32(target, 0x200b8044, 0xa25e);
239
240 /* MLC_TIME_REG */
241 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
242 ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
243 ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
244
245 lpc3180_reset(nand);
246 }
247 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
248 {
249 float cycle;
250 int r_setup, r_hold, r_width, r_rdy;
251 int w_setup, w_hold, w_width, w_rdy;
252
253 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
254 target_write_u32(target, 0x400040c8, 0x05);
255
256 /* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
257 target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
258
259 /* calculate NAND controller timings */
260 cycle = lpc3180_cycle_time(lpc3180_info);
261
262 r_setup = w_setup = 0;
263 r_hold = w_hold = 10 / cycle;
264 r_width = 30 / cycle;
265 w_width = 40 / cycle;
266 r_rdy = w_rdy = 100 / cycle;
267
268 /* SLC_TAC: SLC timing arcs register */
269 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
270 ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
271 ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
272
273 lpc3180_reset(nand);
274 }
275
276 return ERROR_OK;
277 }
278
279 static int lpc3180_reset(struct nand_device *nand)
280 {
281 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
282 struct target *target = lpc3180_info->target;
283
284 if (target->state != TARGET_HALTED)
285 {
286 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
287 return ERROR_NAND_OPERATION_FAILED;
288 }
289
290 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
291 {
292 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
293 return ERROR_NAND_OPERATION_FAILED;
294 }
295 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
296 {
297 /* MLC_CMD = 0xff (reset controller and NAND device) */
298 target_write_u32(target, 0x200b8000, 0xff);
299
300 if (!lpc3180_controller_ready(nand, 100))
301 {
302 LOG_ERROR("LPC3180 NAND controller timed out after reset");
303 return ERROR_NAND_OPERATION_TIMEOUT;
304 }
305 }
306 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
307 {
308 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
309 target_write_u32(target, 0x20020010, 0x6);
310
311 if (!lpc3180_controller_ready(nand, 100))
312 {
313 LOG_ERROR("LPC3180 NAND controller timed out after reset");
314 return ERROR_NAND_OPERATION_TIMEOUT;
315 }
316 }
317
318 return ERROR_OK;
319 }
320
321 static int lpc3180_command(struct nand_device *nand, uint8_t command)
322 {
323 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
324 struct target *target = lpc3180_info->target;
325
326 if (target->state != TARGET_HALTED)
327 {
328 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
329 return ERROR_NAND_OPERATION_FAILED;
330 }
331
332 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
333 {
334 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
335 return ERROR_NAND_OPERATION_FAILED;
336 }
337 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
338 {
339 /* MLC_CMD = command */
340 target_write_u32(target, 0x200b8000, command);
341 }
342 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
343 {
344 /* SLC_CMD = command */
345 target_write_u32(target, 0x20020008, command);
346 }
347
348 return ERROR_OK;
349 }
350
351 static int lpc3180_address(struct nand_device *nand, uint8_t address)
352 {
353 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
354 struct target *target = lpc3180_info->target;
355
356 if (target->state != TARGET_HALTED)
357 {
358 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
359 return ERROR_NAND_OPERATION_FAILED;
360 }
361
362 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
363 {
364 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
365 return ERROR_NAND_OPERATION_FAILED;
366 }
367 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
368 {
369 /* MLC_ADDR = address */
370 target_write_u32(target, 0x200b8004, address);
371 }
372 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
373 {
374 /* SLC_ADDR = address */
375 target_write_u32(target, 0x20020004, address);
376 }
377
378 return ERROR_OK;
379 }
380
381 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
382 {
383 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
384 struct target *target = lpc3180_info->target;
385
386 if (target->state != TARGET_HALTED)
387 {
388 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
389 return ERROR_NAND_OPERATION_FAILED;
390 }
391
392 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
393 {
394 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
395 return ERROR_NAND_OPERATION_FAILED;
396 }
397 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
398 {
399 /* MLC_DATA = data */
400 target_write_u32(target, 0x200b0000, data);
401 }
402 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
403 {
404 /* SLC_DATA = data */
405 target_write_u32(target, 0x20020000, data);
406 }
407
408 return ERROR_OK;
409 }
410
411 static int lpc3180_read_data(struct nand_device *nand, void *data)
412 {
413 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
414 struct target *target = lpc3180_info->target;
415
416 if (target->state != TARGET_HALTED)
417 {
418 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
419 return ERROR_NAND_OPERATION_FAILED;
420 }
421
422 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
423 {
424 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
425 return ERROR_NAND_OPERATION_FAILED;
426 }
427 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
428 {
429 /* data = MLC_DATA, use sized access */
430 if (nand->bus_width == 8)
431 {
432 uint8_t *data8 = data;
433 target_read_u8(target, 0x200b0000, data8);
434 }
435 else if (nand->bus_width == 16)
436 {
437 uint16_t *data16 = data;
438 target_read_u16(target, 0x200b0000, data16);
439 }
440 else
441 {
442 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
443 return ERROR_NAND_OPERATION_FAILED;
444 }
445 }
446 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
447 {
448 uint32_t data32;
449
450 /* data = SLC_DATA, must use 32-bit access */
451 target_read_u32(target, 0x20020000, &data32);
452
453 if (nand->bus_width == 8)
454 {
455 uint8_t *data8 = data;
456 *data8 = data32 & 0xff;
457 }
458 else if (nand->bus_width == 16)
459 {
460 uint16_t *data16 = data;
461 *data16 = data32 & 0xffff;
462 }
463 else
464 {
465 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
466 return ERROR_NAND_OPERATION_FAILED;
467 }
468 }
469
470 return ERROR_OK;
471 }
472
473 static int lpc3180_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
474 {
475 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
476 struct target *target = lpc3180_info->target;
477 int retval;
478 uint8_t status;
479
480 if (target->state != TARGET_HALTED)
481 {
482 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
483 return ERROR_NAND_OPERATION_FAILED;
484 }
485
486 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
487 {
488 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
489 return ERROR_NAND_OPERATION_FAILED;
490 }
491 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
492 {
493 uint8_t *page_buffer;
494 uint8_t *oob_buffer;
495 int quarter, num_quarters;
496
497 if (!data && oob)
498 {
499 LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
500 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
501 }
502
503 if (oob && (oob_size > 24))
504 {
505 LOG_ERROR("LPC3180 MLC controller can't write more "
506 "than 6 bytes for each quarter's OOB data");
507 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
508 }
509
510 if (data_size > (uint32_t)nand->page_size)
511 {
512 LOG_ERROR("data size exceeds page size");
513 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
514 }
515
516 /* MLC_CMD = sequential input */
517 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
518
519 page_buffer = malloc(512);
520 oob_buffer = malloc(6);
521
522 if (nand->page_size == 512)
523 {
524 /* MLC_ADDR = 0x0 (one column cycle) */
525 target_write_u32(target, 0x200b8004, 0x0);
526
527 /* MLC_ADDR = row */
528 target_write_u32(target, 0x200b8004, page & 0xff);
529 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
530
531 if (nand->address_cycles == 4)
532 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
533 }
534 else
535 {
536 /* MLC_ADDR = 0x0 (two column cycles) */
537 target_write_u32(target, 0x200b8004, 0x0);
538 target_write_u32(target, 0x200b8004, 0x0);
539
540 /* MLC_ADDR = row */
541 target_write_u32(target, 0x200b8004, page & 0xff);
542 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
543 }
544
545 /* when using the MLC controller, we have to treat a large page device
546 * as being made out of four quarters, each the size of a small page device
547 */
548 num_quarters = (nand->page_size == 2048) ? 4 : 1;
549
550 for (quarter = 0; quarter < num_quarters; quarter++)
551 {
552 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
553 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
554
555 memset(page_buffer, 0xff, 512);
556 if (data)
557 {
558 memcpy(page_buffer, data, thisrun_data_size);
559 data_size -= thisrun_data_size;
560 data += thisrun_data_size;
561 }
562
563 memset(oob_buffer, 0xff, 6);
564 if (oob)
565 {
566 memcpy(oob_buffer, oob, thisrun_oob_size);
567 oob_size -= thisrun_oob_size;
568 oob += thisrun_oob_size;
569 }
570
571 /* write MLC_ECC_ENC_REG to start encode cycle */
572 target_write_u32(target, 0x200b8008, 0x0);
573
574 target_write_memory(target, 0x200a8000,
575 4, 128, page_buffer);
576 target_write_memory(target, 0x200a8000,
577 1, 6, oob_buffer);
578
579 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
580 target_write_u32(target, 0x200b8010, 0x0);
581
582 if (!lpc3180_controller_ready(nand, 1000))
583 {
584 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
585 return ERROR_NAND_OPERATION_FAILED;
586 }
587 }
588
589 /* MLC_CMD = auto program command */
590 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
591
592 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
593 {
594 LOG_ERROR("couldn't read status");
595 return ERROR_NAND_OPERATION_FAILED;
596 }
597
598 if (status & NAND_STATUS_FAIL)
599 {
600 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
601 return ERROR_NAND_OPERATION_FAILED;
602 }
603
604 free(page_buffer);
605 free(oob_buffer);
606 }
607 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
608 {
609 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
610 }
611
612 return ERROR_OK;
613 }
614
615 static int lpc3180_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
616 {
617 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
618 struct target *target = lpc3180_info->target;
619
620 if (target->state != TARGET_HALTED)
621 {
622 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
623 return ERROR_NAND_OPERATION_FAILED;
624 }
625
626 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
627 {
628 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
629 return ERROR_NAND_OPERATION_FAILED;
630 }
631 else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
632 {
633 uint8_t *page_buffer;
634 uint8_t *oob_buffer;
635 uint32_t page_bytes_done = 0;
636 uint32_t oob_bytes_done = 0;
637 uint32_t mlc_isr;
638
639 #if 0
640 if (oob && (oob_size > 6))
641 {
642 LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
643 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
644 }
645 #endif
646
647 if (data_size > (uint32_t)nand->page_size)
648 {
649 LOG_ERROR("data size exceeds page size");
650 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
651 }
652
653 if (nand->page_size == 2048)
654 {
655 page_buffer = malloc(2048);
656 oob_buffer = malloc(64);
657 }
658 else
659 {
660 page_buffer = malloc(512);
661 oob_buffer = malloc(16);
662 }
663
664 if (!data && oob)
665 {
666 /* MLC_CMD = Read OOB
667 * we can use the READOOB command on both small and large page devices,
668 * as the controller translates the 0x50 command to a 0x0 with appropriate
669 * positioning of the serial buffer read pointer
670 */
671 target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
672 }
673 else
674 {
675 /* MLC_CMD = Read0 */
676 target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
677 }
678
679 if (nand->page_size == 512)
680 {
681 /* small page device */
682 /* MLC_ADDR = 0x0 (one column cycle) */
683 target_write_u32(target, 0x200b8004, 0x0);
684
685 /* MLC_ADDR = row */
686 target_write_u32(target, 0x200b8004, page & 0xff);
687 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
688
689 if (nand->address_cycles == 4)
690 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
691 }
692 else
693 {
694 /* large page device */
695 /* MLC_ADDR = 0x0 (two column cycles) */
696 target_write_u32(target, 0x200b8004, 0x0);
697 target_write_u32(target, 0x200b8004, 0x0);
698
699 /* MLC_ADDR = row */
700 target_write_u32(target, 0x200b8004, page & 0xff);
701 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
702
703 /* MLC_CMD = Read Start */
704 target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
705 }
706
707 while (page_bytes_done < (uint32_t)nand->page_size)
708 {
709 /* MLC_ECC_AUTO_DEC_REG = dummy */
710 target_write_u32(target, 0x200b8014, 0xaa55aa55);
711
712 if (!lpc3180_controller_ready(nand, 1000))
713 {
714 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
715 return ERROR_NAND_OPERATION_FAILED;
716 }
717
718 target_read_u32(target, 0x200b8048, &mlc_isr);
719
720 if (mlc_isr & 0x8)
721 {
722 if (mlc_isr & 0x40)
723 {
724 LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
725 return ERROR_NAND_OPERATION_FAILED;
726 }
727
728 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
729 }
730
731 if (data)
732 {
733 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
734 }
735
736 if (oob)
737 {
738 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
739 }
740
741 page_bytes_done += 512;
742 oob_bytes_done += 16;
743 }
744
745 if (data)
746 memcpy(data, page_buffer, data_size);
747
748 if (oob)
749 memcpy(oob, oob_buffer, oob_size);
750
751 free(page_buffer);
752 free(oob_buffer);
753 }
754 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
755 {
756 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
757 }
758
759 return ERROR_OK;
760 }
761
762 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
763 {
764 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
765 struct target *target = lpc3180_info->target;
766
767 if (target->state != TARGET_HALTED)
768 {
769 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
770 return ERROR_NAND_OPERATION_FAILED;
771 }
772
773 LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
774
775 do
776 {
777 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
778 {
779 uint8_t status;
780
781 /* Read MLC_ISR, wait for controller to become ready */
782 target_read_u8(target, 0x200b8048, &status);
783
784 if (status & 2) {
785 LOG_DEBUG("lpc3180_controller_ready count=%d",
786 timeout);
787 return 1;
788 }
789 }
790 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
791 {
792 uint32_t status;
793
794 /* Read SLC_STAT and check READY bit */
795 target_read_u32(target, 0x20020018, &status);
796
797 if (status & 1) {
798 LOG_DEBUG("lpc3180_controller_ready count=%d",
799 timeout);
800 return 1;
801 }
802 }
803
804 alive_sleep(1);
805 } while (timeout-- > 0);
806
807 return 0;
808 }
809
810 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
811 {
812 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
813 struct target *target = lpc3180_info->target;
814
815 if (target->state != TARGET_HALTED)
816 {
817 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
818 return ERROR_NAND_OPERATION_FAILED;
819 }
820
821 LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
822
823 do
824 {
825 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
826 {
827 uint8_t status = 0x0;
828
829 /* Read MLC_ISR, wait for NAND flash device to become ready */
830 target_read_u8(target, 0x200b8048, &status);
831
832 if (status & 1) {
833 LOG_DEBUG("lpc3180_nand_ready count end=%d",
834 timeout);
835 return 1;
836 }
837 }
838 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
839 {
840 uint32_t status = 0x0;
841
842 /* Read SLC_STAT and check READY bit */
843 target_read_u32(target, 0x20020018, &status);
844
845 if (status & 1) {
846 LOG_DEBUG("lpc3180_nand_ready count end=%d",
847 timeout);
848 return 1;
849 }
850 }
851
852 alive_sleep(1);
853 } while (timeout-- > 0);
854
855 return 0;
856 }
857
858 COMMAND_HANDLER(handle_lpc3180_select_command)
859 {
860 struct lpc3180_nand_controller *lpc3180_info = NULL;
861 char *selected[] =
862 {
863 "no", "mlc", "slc"
864 };
865
866 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
867 {
868 return ERROR_COMMAND_SYNTAX_ERROR;
869 }
870
871 unsigned num;
872 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
873 struct nand_device *nand = get_nand_device_by_num(num);
874 if (!nand)
875 {
876 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
877 return ERROR_OK;
878 }
879
880 lpc3180_info = nand->controller_priv;
881
882 if (CMD_ARGC == 2)
883 {
884 if (strcmp(CMD_ARGV[1], "mlc") == 0)
885 {
886 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
887 }
888 else if (strcmp(CMD_ARGV[1], "slc") == 0)
889 {
890 lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
891 }
892 else
893 {
894 return ERROR_COMMAND_SYNTAX_ERROR;
895 }
896 }
897
898 command_print(CMD_CTX, "%s controller selected", selected[lpc3180_info->selected_controller]);
899
900 return ERROR_OK;
901 }
902
903 static const struct command_registration lpc3180_exec_command_handlers[] = {
904 {
905 .name = "select",
906 .handler = handle_lpc3180_select_command,
907 .mode = COMMAND_EXEC,
908 .help = "select MLC or SLC controller (default is MLC)",
909 .usage = "bank_id ['mlc'|'slc']",
910 },
911 COMMAND_REGISTRATION_DONE
912 };
913 static const struct command_registration lpc3180_command_handler[] = {
914 {
915 .name = "lpc3180",
916 .mode = COMMAND_ANY,
917 .help = "LPC3180 NAND flash controller commands",
918 .chain = lpc3180_exec_command_handlers,
919 },
920 COMMAND_REGISTRATION_DONE
921 };
922
923 struct nand_flash_controller lpc3180_nand_controller = {
924 .name = "lpc3180",
925 .commands = lpc3180_command_handler,
926 .nand_device_command = lpc3180_nand_device_command,
927 .init = lpc3180_init,
928 .reset = lpc3180_reset,
929 .command = lpc3180_command,
930 .address = lpc3180_address,
931 .write_data = lpc3180_write_data,
932 .read_data = lpc3180_read_data,
933 .write_page = lpc3180_write_page,
934 .read_page = lpc3180_read_page,
935 .controller_ready = lpc3180_controller_ready,
936 .nand_ready = lpc3180_nand_ready,
937 };
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