1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (openocd)
27 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (openocd) version @value{VERSION}, @value{UPDATED}.
45 * About:: About Openocd.
46 * Developers:: Openocd developers
47 * Building:: Building Openocd
48 * Running:: Running Openocd
49 * Configuration:: Openocd Configuration.
50 * Target library:: Target library
51 * Commands:: Openocd Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and Openocd:: Using GDB and Openocd
54 * Upgrading:: Deprecated/Removed Commands
55 * FAQ:: Frequently Asked Questions
56 * License:: GNU Free Documentation License
64 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
65 and boundary-scan testing for embedded target devices. The targets are interfaced
66 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
67 connection types in the future.
69 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
70 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
71 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
72 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
74 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
75 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
76 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
82 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
83 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
84 Others interested in improving the state of free and open debug and testing technology
85 are welcome to participate.
87 Other developers have contributed support for additional targets and flashes as well
88 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
92 @cindex building openocd
94 You can download the current SVN version with SVN client of your choice from the
95 following repositories:
97 (@uref{svn://svn.berlios.de/openocd/trunk})
101 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
103 Using the SVN command line client, you could use the following command to fetch the
104 latest version (make sure there is no (non-svn) directory called "openocd" in the
108 svn checkout svn://svn.berlios.de/openocd/trunk openocd
111 Building the OpenOCD requires a recent version of the GNU autotools.
112 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
113 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
114 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
115 paths, resulting in obscure dependency errors (This is an observation I've gathered
116 from the logs of one user - correct me if I'm wrong).
118 You further need the appropriate driver files, if you want to build support for
119 a FTDI FT2232 based interface:
121 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
122 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
123 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
124 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
127 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
128 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
130 In general, the D2XX driver provides superior performance (several times as fast),
131 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
132 a kernel module, only a user space library.
134 To build OpenOCD (on both Linux and Cygwin), use the following commands:
138 Bootstrap generates the configure script, and prepares building on your system.
142 Configure generates the Makefiles used to build OpenOCD.
146 Make builds the OpenOCD, and places the final executable in ./src/.
148 The configure script takes several options, specifying which JTAG interfaces
153 @option{--enable-parport}
155 @option{--enable-parport_ppdev}
157 @option{--enable-parport_giveio}
159 @option{--enable-amtjtagaccel}
161 @option{--enable-ft2232_ftd2xx}
162 @footnote{Using the latest D2XX drivers from FTDI and following their installation
163 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
166 @option{--enable-ft2232_libftdi}
168 @option{--with-ftd2xx=/path/to/d2xx/}
170 @option{--enable-gw16012}
172 @option{--enable-usbprog}
174 @option{--enable-presto_libftdi}
176 @option{--enable-presto_ftd2xx}
179 If you want to access the parallel port using the PPDEV interface you have to specify
180 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
181 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
182 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
184 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
185 absolute path containing no spaces.
187 Linux users should copy the various parts of the D2XX package to the appropriate
188 locations, i.e. /usr/include, /usr/lib.
192 @cindex running openocd
194 @cindex --debug_level
197 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
198 Run with @option{--help} or @option{-h} to view the available command line arguments.
200 It reads its configuration by default from the file openocd.cfg located in the current
201 working directory. This may be overwritten with the @option{-f <configfile>} command line
202 switch. @option{-f} can be specified multiple times, in which case the config files
203 are executed in order.
205 Also it is possible to interleave commands w/config scripts using the @option{-c}.
207 To enable debug output (when reporting problems or working on OpenOCD itself), use
208 the @option{-d} command line switch. This sets the debug_level to "3", outputting
209 the most information, including debug messages. The default setting is "2", outputting
210 only informational messages, warnings and errors. You can also change this setting
211 from within a telnet or gdb session (@option{debug_level <n>}).
213 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
215 Search paths for config/script files can be added to openocd by using
216 the @option{-s <search>} switch. The current directory and the OpenOCD target library
217 is in the search path by default.
219 NB! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
220 with the target. In general, it is possible for the JTAG controller to be unresponsive until
221 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
224 @chapter Configuration
225 @cindex configuration
226 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
227 by default from the file openocd.cfg in the current directory. A different configuration
228 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
230 The configuration file is used to specify on which ports the daemon listens for new
231 connections, the JTAG interface used to connect to the target, the layout of the JTAG
232 chain, the targets that should be debugged, and connected flashes.
234 @section Daemon configuration
237 @item @b{init} This command terminates the configuration stage and enters the normal
238 command mode. This can be useful to add commands to the startup scripts and commands
239 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
240 add "init" and "reset" at the end of the config script or at the end of the
241 openocd command line using the -c option.
243 @item @b{telnet_port} <@var{number}>
245 Port on which to listen for incoming telnet connections
246 @item @b{gdb_port} <@var{number}>
248 First port on which to listen for incoming GDB connections. The GDB port for the
249 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
250 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
252 Configures what openocd will do when gdb detaches from the daeman.
253 Default behaviour is <@var{resume}>
254 @item @b{gdb_memory_map} <@var{enable|disable}>
255 @cindex gdb_memory_map
256 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
257 requested. gdb will then know when to set hardware breakpoints, and program flash
258 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
259 for flash programming to work.
260 Default behaviour is <@var{disable}>
261 @item @b{gdb_flash_program} <@var{enable|disable}>
262 @cindex gdb_flash_program
263 Set to <@var{enable}> so that openocd will program the flash memory when a
264 vFlash packet is received.
265 Default behaviour is <@var{enable}>
266 @item @b{daemon_startup} <@var{mode}>
267 @cindex daemon_startup
268 @option{mode} can either @option{attach} or @option{reset}
269 This is equivalent to adding "init" and "reset" to the end of the config script.
271 It is availble as a command mainly for backwards compatibility.
274 @section JTAG interface configuration
277 @item @b{interface} <@var{name}>
279 Use the interface driver <@var{name}> to connect to the target. Currently supported
283 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
286 @item @b{amt_jtagaccel}
287 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
292 FTDI FT2232 based devices using either the open-source libftdi or the binary only
293 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
294 platform. The libftdi uses libusb, and should be portable to all systems that provide
299 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
303 ASIX PRESTO USB JTAG programmer.
307 usbprog is a freely programmable USB adapter.
311 Gateworks GW16012 JTAG programmer.
316 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
318 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
319 speed. The actual effect of this option depends on the JTAG interface used. Reset
320 speed is used during reset and post reset speed after reset. post reset speed
321 is optional, in which case the reset speed is used.
324 @item wiggler: maximum speed / @var{number}
325 @item ft2232: 6MHz / (@var{number}+1)
326 @item amt jtagaccel: 8 / 2**@var{number}
329 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
330 especially true for synthesized cores (-S).
332 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
334 Same as jtag_speed, except that the speed is specified in maximum kHz. If
335 the device can not support the rate asked for, or can not translate from
336 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
337 is not supported, then an error is reported.
339 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
341 The configuration of the reset signals available on the JTAG interface AND the target.
342 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
343 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
344 @option{srst_only} or @option{trst_and_srst}.
346 [@var{combination}] is an optional value specifying broken reset signal implementations.
347 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
348 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
349 that the system is reset together with the test logic (only hypothetical, I haven't
350 seen hardware with such a bug, and can be worked around).
351 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
352 The default behaviour if no option given is @option{separate}.
354 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
355 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
356 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
357 (default) and @option{srst_push_pull} for the system reset. These values only affect
358 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
360 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
362 Describes the devices that form the JTAG daisy chain, with the first device being
363 the one closest to TDO. The parameters are the length of the instruction register
364 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
365 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
366 The IDCODE instruction will in future be used to query devices for their JTAG
367 identification code. This line is the same for all ARM7 and ARM9 devices.
368 Other devices, like CPLDs, require different parameters. An example configuration
369 line for a Xilinx XC9500 CPLD would look like this:
371 jtag_device 8 0x01 0x0e3 0xfe
373 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
374 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
375 The IDCODE instruction is 0xfe.
377 @item @b{jtag_nsrst_delay} <@var{ms}>
378 @cindex jtag_nsrst_delay
379 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
380 starting new JTAG operations.
381 @item @b{jtag_ntrst_delay} <@var{ms}>
382 @cindex jtag_ntrst_delay
383 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
384 starting new JTAG operations.
386 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
387 or on-chip features) keep a reset line asserted for some time after the external reset
391 @section parport options
394 @item @b{parport_port} <@var{number}>
396 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
397 the @file{/dev/parport} device
399 When using PPDEV to access the parallel port, use the number of the parallel port:
400 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
401 you may encounter a problem.
402 @item @b{parport_cable} <@var{name}>
403 @cindex parport_cable
404 The layout of the parallel port cable used to connect to the target.
405 Currently supported cables are
409 Original Wiggler layout, also supported by several clones, such
410 as the Olimex ARM-JTAG
411 @item @b{old_amt_wiggler}
412 @cindex old_amt_wiggler
413 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
414 version available from the website uses the original Wiggler layout ('@var{wiggler}')
417 Describes the connection of the Amontec Chameleon's CPLD when operated in
418 configuration mode. This is only used to program the Chameleon itself, not
422 Xilinx Parallel cable III.
425 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
426 This is also the layout used by the HollyGates design
427 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
432 @item @b{parport_write_on_exit} <@var{on|off}>
433 @cindex parport_write_on_exit
434 This will configure the parallel driver to write a known value to the parallel
435 interface on exiting openocd
438 @section amt_jtagaccel options
440 @item @b{parport_port} <@var{number}>
442 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
443 @file{/dev/parport} device
445 @section ft2232 options
448 @item @b{ft2232_device_desc} <@var{description}>
449 @cindex ft2232_device_desc
450 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
451 default value is used. This setting is only valid if compiled with FTD2XX support.
452 @item @b{ft2232_layout} <@var{name}>
453 @cindex ft2232_layout
454 The layout of the FT2232 GPIO signals used to control output-enables and reset
455 signals. Valid layouts are
458 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
460 Amontec JTAGkey and JTAGkey-tiny
463 @item @b{olimex-jtag}
466 American Microsystems M5960
467 @item @b{evb_lm3s811}
468 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
469 SRST signals on external connector
473 Hitex STM32 Performance Stick
475 Tin Can Tools Flyswatter
476 @item @b{turtelizer2}
477 egnite Software turtelizer2
482 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
483 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
484 default values are used. This command is not available on Windows.
485 @item @b{ft2232_latency} <@var{ms}>
486 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
487 ft2232_read() fails to return the expected number of bytes. This can be caused by
488 USB communication delays and has proved hard to reproduce and debug. Setting the
489 FT2232 latency timer to a larger value increases delays for short USB packages but it
490 also reduces the risk of timeouts before receiving the expected number of bytes.
491 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
494 @section ep93xx options
495 @cindex ep93xx options
496 Currently, there are no options available for the ep93xx interface.
499 @section Target configuration
502 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
505 Defines a target that should be debugged. Currently supported types are:
519 If you want to use a target board that is not on this list, see Adding a new
522 Endianess may be @option{little} or @option{big}.
524 The reset_mode specifies what should happen to the target when a reset occurs:
528 Immediately request a target halt after reset. This allows targets to be debugged
529 from the very first instruction. This is only possible with targets and JTAG
530 interfaces that correctly implement the reset signals.
533 Similar to @option{reset_halt}, but executes the script file defined to handle the
534 'reset' event for the target. Like @option{reset_halt} this only works with
535 correct reset implementations.
538 Simply let the target run after a reset.
539 @item @b{run_and_halt}
541 Let the target run for some time (default: 1s), and then request halt.
542 @item @b{run_and_init}
544 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
545 to run for some time, then halted, and the @option{reset} event script is executed.
548 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
549 completely independent (like the LPC2000 series), or where the JTAG interface is
550 unavailable for some time during startup (like the STR7 series), you can't use
551 @option{reset_halt} or @option{reset_init}.
553 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
554 @cindex target_script
555 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
557 TODO: describe exact semantic of events
558 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
559 @cindex run_and_halt_time
560 The amount of time the debugger should wait after releasing reset before it asserts
561 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
563 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
564 <@var{backup}|@var{nobackup}>
566 Specifies a working area for the debugger to use. This may be used to speed-up
567 downloads to target memory and flash operations, or to perform otherwise unavailable
568 operations (some coprocessor operations on ARM7/9 systems, for example). The last
569 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
570 a working_area that doesn't need to be backed up, as that slows down operation.
573 @subsection arm7tdmi options
574 @cindex arm7tdmi options
575 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
576 The arm7tdmi target definition requires at least one additional argument, specifying
577 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
578 The optional [@var{variant}] parameter has been removed in recent versions.
579 The correct feature set is determined at runtime.
581 @subsection arm720t options
582 @cindex arm720t options
583 ARM720t options are similar to ARM7TDMI options.
585 @subsection arm9tdmi options
586 @cindex arm9tdmi options
587 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
588 @option{arm920t}, @option{arm922t} and @option{arm940t}.
589 This enables the hardware single-stepping support found on these cores.
591 @subsection arm920t options
592 @cindex arm920t options
593 ARM920t options are similar to ARM9TDMI options.
595 @subsection arm966e options
596 @cindex arm966e options
597 ARM966e options are similar to ARM9TDMI options.
599 @subsection cortex_m3 options
600 @cindex cortex_m3 options
601 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
602 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
603 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
604 be detected and the normal reset behaviour used.
606 @subsection xscale options
607 @cindex xscale options
608 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
609 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
611 @section Flash configuration
612 @cindex Flash configuration
615 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
616 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
618 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
619 and <@var{bus_width}> bytes using the selected flash <driver>.
622 @subsection lpc2000 options
623 @cindex lpc2000 options
625 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
626 <@var{clock}> [@var{calc_checksum}]
627 LPC flashes don't require the chip and bus width to be specified. Additional
628 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
629 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
630 of the target this flash belongs to (first is 0), the frequency at which the core
631 is currently running (in kHz - must be an integral number), and the optional keyword
632 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
635 @subsection cfi options
638 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
640 CFI flashes require the number of the target they're connected to as an additional
641 argument. The CFI driver makes use of a working area (specified for the target)
642 to significantly speed up operation.
644 @var{chip_width} and @var{bus_width} are specified in bytes.
646 @subsection at91sam7 options
647 @cindex at91sam7 options
649 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
650 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
651 reading the chip-id and type.
653 @subsection str7 options
656 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
657 variant can be either STR71x, STR73x or STR75x.
659 @subsection str9 options
662 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
663 The str9 needs the flash controller to be configured prior to Flash programming, eg.
665 str9x flash_config 0 4 2 0 0x80000
667 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
669 @subsection str9 options (str9xpec driver)
671 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
672 Before using the flash commands the turbo mode will need enabling using str9xpec
673 @option{enable_turbo} <@var{num>.}
675 Only use this driver for locking/unlocking the device or configuring the option bytes.
676 Use the standard str9 driver for programming.
678 @subsection stellaris (LM3Sxxx) options
679 @cindex stellaris (LM3Sxxx) options
681 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
682 stellaris flash plugin only require the @var{target#}.
684 @subsection stm32x options
685 @cindex stm32x options
687 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
688 stm32x flash plugin only require the @var{target#}.
691 @chapter Target library
692 @cindex Target library
694 OpenOCD comes with a target configuration script library. These scripts can be
695 used as-is or serve as a starting point.
697 The target library is published together with the openocd executable and
698 the path to the target library is in the OpenOCD script search path.
699 Similarly there are example scripts for configuring the JTAG interface.
701 The command line below uses the example parport configuration scripts
702 that ships with OpenOCD, then configures the str710.cfg target and
703 finally issues the init and reset command. The communication speed
704 is set to 10kHz for reset and 8MHz for post reset.
708 openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
712 To list the target scripts available:
715 $ ls /usr/local/lib/openocd/target
717 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
718 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
719 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
720 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
728 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
729 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
730 is available from both the telnet interface and a GDB session. To issue commands to the
731 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
732 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
738 @item @b{sleep} <@var{msec}>
740 Wait for n milliseconds before resuming. Useful in connection with script files
741 (@var{script} command and @var{target_script} configuration).
745 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
747 @item @b{debug_level} [@var{n}]
749 Display or adjust debug level to n<0-3>
751 @item @b{fast} [@var{enable/disable}]
753 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
754 downloads and fast memory access will work if the JTAG interface isn't too fast and
755 the core doesn't run at a too low frequency. Note that this option only changes the default
756 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
759 The target specific "dangerous" optimisation tweaking options may come and go
760 as more robust and user friendly ways are found to ensure maximum throughput
761 and robustness with a minimum of configuration.
763 Typically the "fast enable" is specified first on the command line:
765 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
767 @item @b{log_output} <@var{file}>
769 Redirect logging to <file> (default: stderr)
771 @item @b{script} <@var{file}>
773 Execute commands from <file>
777 @subsection Target state handling
779 @item @b{poll} [@option{on}|@option{off}]
781 Poll the target for its current state. If the target is in debug mode, architecture
782 specific information about the current state are printed. An optional parameter
783 allows continuous polling to be enabled and disabled.
785 @item @b{halt} [@option{ms}]
787 Send a halt request to the target and waits for it to halt for [@option{ms}].
788 Default [@option{ms}] is 5 seconds if no arg given.
789 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
790 will stop openocd from waiting.
792 @item @b{wait_halt} [@option{ms}]
794 Wait for the target to enter debug mode. Optional [@option{ms}] is
795 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
798 @item @b{resume} [@var{address}]
800 Resume the target at its current code position, or at an optional address.
801 Openocd will wait 5 seconds for the target to resume.
803 @item @b{step} [@var{address}]
805 Single-step the target at its current code position, or at an optional address.
807 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
808 |@option{run_and_init}]
810 Do a hard-reset. The optional parameter specifies what should happen after the reset.
811 This optional parameter overwrites the setting specified in the configuration file,
812 making the new behaviour the default for the @option{reset} command.
819 Immediately halt the target (works only with certain configurations).
822 Immediately halt the target, and execute the reset script (works only with certain
824 @item @b{run_and_halt}
825 @cindex reset run_and_halt
826 Let the target run for a certain amount of time, then request a halt.
827 @item @b{run_and_init}
828 @cindex reset run_and_init
829 Let the target run for a certain amount of time, then request a halt. Execute the
830 reset script once the target entered debug mode.
834 @subsection Memory access commands
835 These commands allow accesses of a specific size to the memory system:
837 @item @b{mdw} <@var{addr}> [@var{count}]
840 @item @b{mdh} <@var{addr}> [@var{count}]
842 display memory half-words
843 @item @b{mdb} <@var{addr}> [@var{count}]
846 @item @b{mww} <@var{addr}> <@var{value}>
849 @item @b{mwh} <@var{addr}> <@var{value}>
851 write memory half-word
852 @item @b{mwb} <@var{addr}> <@var{value}>
856 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
858 Load image <@var{file}> to target memory at <@var{address}>
859 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
861 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
862 (binary) <@var{file}>.
863 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
865 Verify <@var{file}> to target memory starting at <@var{address}>.
866 This will first attempt using a crc checksum, if this fails it will try a binary compare.
869 @subsection Flash commands
870 @cindex Flash commands
872 @item @b{flash banks}
874 List configured flash banks
875 @item @b{flash info} <@var{num}>
877 Print info about flash bank <@option{num}>
878 @item @b{flash probe} <@var{num}>
880 Identify the flash, or validate the parameters of the configured flash. Operation
881 depends on the flash type.
882 @item @b{flash erase_check} <@var{num}>
883 @cindex flash erase_check
884 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
885 updates the erase state information displayed by @option{flash info}. That means you have
886 to issue an @option{erase_check} command after erasing or programming the device to get
888 @item @b{flash protect_check} <@var{num}>
889 @cindex flash protect_check
890 Check protection state of sectors in flash bank <num>.
891 @option{flash erase_sector} using the same syntax.
892 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
893 @cindex flash erase_sector
894 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
895 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
896 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
898 @item @b{flash erase_address} <@var{address}> <@var{length}>
899 @cindex flash erase_address
900 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
901 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
902 @cindex flash write_bank
903 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
904 <@option{offset}> bytes from the beginning of the bank.
905 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
906 @cindex flash write_image
907 Write the image <@var{file}> to the current target's flash bank(s). A relocation
908 [@var{offset}] can be specified and the file [@var{type}] can be specified
909 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
910 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
911 if the @option{erase} parameter is given.
912 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
913 @cindex flash protect
914 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
915 <@var{last}> of @option{flash bank} <@var{num}>.
919 @section Target Specific Commands
920 @cindex Target Specific Commands
922 @subsection AT91SAM7 specific commands
923 @cindex AT91SAM7 specific commands
924 The flash configuration is deduced from the chip identification register. The flash
925 controller handles erases automatically on a page (128/265 byte) basis so erase is
926 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
927 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
928 that can be erased separatly.Only an EraseAll command is supported by the controller
929 for each flash plane and this is called with
931 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
932 bulk erase flash planes first_plane to last_plane.
933 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
934 @cindex at91sam7 gpnvm
935 set or clear a gpnvm bit for the processor
938 @subsection STR9 specific commands
939 @cindex STR9 specific commands
940 These are flash specific commands when using the str9xpec driver.
942 @item @b{str9xpec enable_turbo} <@var{num}>
943 @cindex str9xpec enable_turbo
944 enable turbo mode, simply this will remove the str9 from the chain and talk
945 directly to the embedded flash controller.
946 @item @b{str9xpec disable_turbo} <@var{num}>
947 @cindex str9xpec disable_turbo
948 restore the str9 into jtag chain.
949 @item @b{str9xpec lock} <@var{num}>
950 @cindex str9xpec lock
951 lock str9 device. The str9 will only respond to an unlock command that will
953 @item @b{str9xpec unlock} <@var{num}>
954 @cindex str9xpec unlock
956 @item @b{str9xpec options_read} <@var{num}>
957 @cindex str9xpec options_read
958 read str9 option bytes.
959 @item @b{str9xpec options_write} <@var{num}>
960 @cindex str9xpec options_write
961 write str9 option bytes.
964 @subsection STR9 configuration
965 @cindex STR9 configuration
967 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
968 <@var{BBADR}> <@var{NBBADR}>
969 @cindex str9x flash_config
970 Configure str9 flash controller.
972 eg. str9x flash_config 0 4 2 0 0x80000
974 BBSR - Boot Bank Size register
975 NBBSR - Non Boot Bank Size register
976 BBADR - Boot Bank Start Address register
977 NBBADR - Boot Bank Start Address register
981 @subsection STR9 option byte configuration
982 @cindex STR9 option byte configuration
984 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
985 @cindex str9xpec options_cmap
986 configure str9 boot bank.
987 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
988 @cindex str9xpec options_lvdthd
989 configure str9 lvd threshold.
990 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
991 @cindex str9xpec options_lvdsel
992 configure str9 lvd source.
993 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
994 @cindex str9xpec options_lvdwarn
995 configure str9 lvd reset warning source.
998 @subsection STM32x specific commands
999 @cindex STM32x specific commands
1001 These are flash specific commands when using the stm32x driver.
1003 @item @b{stm32x lock} <@var{num}>
1006 @item @b{stm32x unlock} <@var{num}>
1007 @cindex stm32x unlock
1008 unlock stm32 device.
1009 @item @b{stm32x options_read} <@var{num}>
1010 @cindex stm32x options_read
1011 read stm32 option bytes.
1012 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1013 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1014 @cindex stm32x options_write
1015 write stm32 option bytes.
1016 @item @b{stm32x mass_erase} <@var{num}>
1017 @cindex stm32x mass_erase
1018 mass erase flash memory.
1022 @section Architecture Specific Commands
1023 @cindex Architecture Specific Commands
1025 @subsection ARMV4/5 specific commands
1026 @cindex ARMV4/5 specific commands
1028 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1029 or Intel XScale (XScale isn't supported yet).
1031 @item @b{armv4_5 reg}
1033 Display a list of all banked core registers, fetching the current value from every
1034 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1036 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1037 @cindex armv4_5 core_mode
1038 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1039 The target is resumed in the currently set @option{core_mode}.
1042 @subsection ARM7/9 specific commands
1043 @cindex ARM7/9 specific commands
1045 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1046 ARM920t or ARM926EJ-S.
1048 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1049 @cindex arm7_9 sw_bkpts
1050 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1051 one of the watchpoint registers to implement software breakpoints. Disabling
1052 SW Bkpts frees that register again.
1053 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1054 @cindex arm7_9 force_hw_bkpts
1055 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1056 breakpoints are turned into hardware breakpoints.
1057 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1058 @cindex arm7_9 dbgrq
1059 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1060 safe for all but ARM7TDMI--S cores (like Philips LPC).
1061 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1062 @cindex arm7_9 fast_memory_access
1063 Allow the OpenOCD to read and write memory without checking completion of
1064 the operation. This provides a huge speed increase, especially with USB JTAG
1065 cables (FT2232), but might be unsafe if used with targets running at a very low
1066 speed, like the 32kHz startup clock of an AT91RM9200.
1067 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1068 @cindex arm7_9 dcc_downloads
1069 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1070 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1071 unsafe, especially with targets running at a very low speed. This command was introduced
1072 with OpenOCD rev. 60.
1075 @subsection ARM720T specific commands
1076 @cindex ARM720T specific commands
1079 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1080 @cindex arm720t cp15
1081 display/modify cp15 register <@option{num}> [@option{value}].
1082 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1083 @cindex arm720t md<bhw>_phys
1084 Display memory at physical address addr.
1085 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1086 @cindex arm720t mw<bhw>_phys
1087 Write memory at physical address addr.
1088 @item @b{arm720t virt2phys} <@var{va}>
1089 @cindex arm720t virt2phys
1090 Translate a virtual address to a physical address.
1093 @subsection ARM9TDMI specific commands
1094 @cindex ARM9TDMI specific commands
1097 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1098 @cindex arm9tdmi vector_catch
1099 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1100 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1101 @option{irq} @option{fiq}.
1103 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1106 @subsection ARM966E specific commands
1107 @cindex ARM966E specific commands
1110 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1111 @cindex arm966e cp15
1112 display/modify cp15 register <@option{num}> [@option{value}].
1115 @subsection ARM920T specific commands
1116 @cindex ARM920T specific commands
1119 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1120 @cindex arm920t cp15
1121 display/modify cp15 register <@option{num}> [@option{value}].
1122 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1123 @cindex arm920t cp15i
1124 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1125 @item @b{arm920t cache_info}
1126 @cindex arm920t cache_info
1127 Print information about the caches found. This allows you to see if your target
1128 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1129 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1130 @cindex arm920t md<bhw>_phys
1131 Display memory at physical address addr.
1132 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1133 @cindex arm920t mw<bhw>_phys
1134 Write memory at physical address addr.
1135 @item @b{arm920t read_cache} <@var{filename}>
1136 @cindex arm920t read_cache
1137 Dump the content of ICache and DCache to a file.
1138 @item @b{arm920t read_mmu} <@var{filename}>
1139 @cindex arm920t read_mmu
1140 Dump the content of the ITLB and DTLB to a file.
1141 @item @b{arm920t virt2phys} <@var{va}>
1142 @cindex arm920t virt2phys
1143 Translate a virtual address to a physical address.
1146 @subsection ARM926EJS specific commands
1147 @cindex ARM926EJS specific commands
1150 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1151 @cindex arm926ejs cp15
1152 display/modify cp15 register <@option{num}> [@option{value}].
1153 @item @b{arm926ejs cache_info}
1154 @cindex arm926ejs cache_info
1155 Print information about the caches found.
1156 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1157 @cindex arm926ejs md<bhw>_phys
1158 Display memory at physical address addr.
1159 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1160 @cindex arm926ejs mw<bhw>_phys
1161 Write memory at physical address addr.
1162 @item @b{arm926ejs virt2phys} <@var{va}>
1163 @cindex arm926ejs virt2phys
1164 Translate a virtual address to a physical address.
1168 @section Debug commands
1169 @cindex Debug commands
1170 The following commands give direct access to the core, and are most likely
1171 only useful while debugging the OpenOCD.
1173 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1174 @cindex arm7_9 write_xpsr
1175 Immediately write either the current program status register (CPSR) or the saved
1176 program status register (SPSR), without changing the register cache (as displayed
1177 by the @option{reg} and @option{armv4_5 reg} commands).
1178 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1179 <@var{0=cpsr},@var{1=spsr}>
1180 @cindex arm7_9 write_xpsr_im8
1181 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1182 operation (similar to @option{write_xpsr}).
1183 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1184 @cindex arm7_9 write_core_reg
1185 Write a core register, without changing the register cache (as displayed by the
1186 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1187 encoding of the [M4:M0] bits of the PSR.
1191 @section JTAG commands
1192 @cindex JTAG commands
1194 @item @b{scan_chain}
1196 Print current scan chain configuration.
1197 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1200 @item @b{endstate} <@var{tap_state}>
1202 Finish JTAG operations in <@var{tap_state}>.
1203 @item @b{runtest} <@var{num_cycles}>
1205 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1206 @item @b{statemove} [@var{tap_state}]
1208 Move to current endstate or [@var{tap_state}]
1209 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1211 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1212 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1214 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1215 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1216 @cindex verify_ircapture
1217 Verify value captured during Capture-IR. Default is enabled.
1218 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1220 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1221 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1223 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1227 @section Target Requests
1228 @cindex Target Requests
1229 Openocd can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1230 See libdcc in the contrib dir for more details.
1232 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1233 @cindex target_request debugmsgs
1234 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1237 @node Sample Scripts
1238 @chapter Sample Scripts
1241 This page shows how to use the target library.
1243 The configuration script can be divided in the following section:
1245 @item daemon configuration
1247 @item jtag scan chain
1248 @item target configuration
1249 @item flash configuration
1252 Detailed information about each section can be found at OpenOCD configuration.
1254 @section AT91R40008 example
1255 @cindex AT91R40008 example
1256 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1257 the CPU upon startup of the OpenOCD daemon.
1259 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1263 @node GDB and Openocd
1264 @chapter GDB and Openocd
1265 @cindex GDB and Openocd
1266 Openocd complies with the remote gdbserver protocol, and as such can be used
1267 to debug remote targets.
1269 @section Connecting to gdb
1270 @cindex Connecting to gdb
1271 A connection is typically started as follows:
1273 target remote localhost:3333
1275 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1277 To see a list of available openocd commands type @option{monitor help} on the
1280 Openocd supports the gdb @option{qSupported} packet, this enables information
1281 to be sent by the gdb server (openocd) to gdb. Typical information includes
1282 packet size and device memory map.
1284 Previous versions of openocd required the following gdb options to increase
1285 the packet size and speed up gdb communication.
1287 set remote memory-write-packet-size 1024
1288 set remote memory-write-packet-size fixed
1289 set remote memory-read-packet-size 1024
1290 set remote memory-read-packet-size fixed
1292 This is now handled in the @option{qSupported} PacketSize.
1294 @section Programming using gdb
1295 @cindex Programming using gdb
1297 By default the target memory map is sent to gdb, this can be disabled by
1298 the following openocd config option:
1300 gdb_memory_map disable
1302 For this to function correctly a valid flash config must also be configured
1303 in openocd. For speed also configure a valid working area.
1305 Informing gdb of the memory map of the target will enable gdb to protect any
1306 flash area of the target and use hardware breakpoints by default. This means
1307 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1310 To view the configured memory map in gdb, use the gdb command @option{info mem}
1311 All other unasigned addresses within gdb are treated as RAM.
1313 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1314 this can be changed to the old behaviour by using the following gdb command.
1316 set mem inaccessible-by-default off
1319 If @option{gdb_flash_program enable} is also used, gdb will be able to
1320 program any flash memory using the vFlash interface.
1322 gdb will look at the target memory map when a load command is given, if any
1323 areas to be programmed lie within the target flash area the vFlash packets
1326 Incase the target needs configuring before gdb programming, a script can be executed.
1328 target_script 0 gdb_program_config config.script
1331 To verify any flash programming the gdb command @option{compare-sections}
1335 @chapter Deprecated/Removed Commands
1336 @cindex Deprecated/Removed Commands
1337 Certain openocd commands have been deprecated/removed during the various revisions.
1340 @item @b{load_binary}
1342 use @option{load_image} command with same args
1343 @item @b{dump_binary}
1345 use @option{dump_image} command with same args
1346 @item @b{flash erase}
1348 use @option{flash erase_sector} command with same args
1349 @item @b{flash write}
1351 use @option{flash write_bank} command with same args
1352 @item @b{flash write_binary}
1353 @cindex flash write_binary
1354 use @option{flash write_bank} command with same args
1355 @item @b{arm7_9 fast_writes}
1356 @cindex arm7_9 fast_writes
1357 use @option{arm7_9 fast_memory_access} command with same args
1358 @item @b{flash auto_erase}
1359 @cindex flash auto_erase
1360 use @option{flash write_image} command passing @option{erase} as the first parameter.
1367 @item OpenOCD complains about a missing cygwin1.dll.
1369 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1370 claims to come with all the necessary dlls. When using Cygwin, try launching
1371 the OpenOCD from the Cygwin shell.
1373 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1374 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1375 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1377 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1378 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1379 software breakpoints consume one of the two available hardware breakpoints,
1380 and are therefore disabled by default. If your code is running from RAM, you
1381 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1382 your code resides in Flash, you can't use software breakpoints, but you can force
1383 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1385 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1386 and works sometimes fine.
1388 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1389 clock at the time you're programming the flash. If you've specified the crystal's
1390 frequency, make sure the PLL is disabled, if you've specified the full core speed
1391 (e.g. 60MHz), make sure the PLL is enabled.
1393 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1394 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1395 out while waiting for end of scan, rtck was disabled".
1397 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1398 settings in your PC BIOS (ECP, EPP, and different versions of those).
1400 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1401 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1402 memory read caused data abort".
1404 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1405 beyond the last valid frame. It might be possible to prevent this by setting up
1406 a proper "initial" stack frame, if you happen to know what exactly has to
1407 be done, feel free to add this here.
1409 @item I get the following message in the OpenOCD console (or log file):
1410 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1412 This warning doesn't indicate any serious problem, as long as you don't want to
1413 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1414 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1415 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1416 independently. With this setup, it's not possible to halt the core right out of
1417 reset, everything else should work fine.
1419 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1420 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1421 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1422 quit with an error message. Is there a stability issue with OpenOCD?
1424 No, this is not a stability issue concerning OpenOCD. Most users have solved
1425 this issue by simply using a self-powered USB hub, which they connect their
1426 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1427 supply stable enough for the Amontec JTAGkey to be operated.
1429 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1430 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1431 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1432 What does that mean and what might be the reason for this?
1434 First of all, the reason might be the USB power supply. Try using a self-powered
1435 hub instead of a direct connection to your computer. Secondly, the error code 4
1436 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1437 chip ran into some sort of error - this points us to a USB problem.
1439 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1440 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1441 What does that mean and what might be the reason for this?
1443 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1444 has closed the connection to OpenOCD. This might be a GDB issue.
1446 @item In the configuration file in the section where flash device configurations
1447 are described, there is a parameter for specifying the clock frequency for
1448 LPC2000 internal flash devices (e.g.
1449 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1450 which must be specified in kilohertz. However, I do have a quartz crystal of a
1451 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1452 Is it possible to specify real numbers for the clock frequency?
1454 No. The clock frequency specified here must be given as an integral number.
1455 However, this clock frequency is used by the In-Application-Programming (IAP)
1456 routines of the LPC2000 family only, which seems to be very tolerant concerning
1457 the given clock frequency, so a slight difference between the specified clock
1458 frequency and the actual clock frequency will not cause any trouble.
1460 @item Do I have to keep a specific order for the commands in the configuration file?
1462 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1463 listed for the JTAG scan chain must be given in the right order (jtag_device),
1464 with the device closest to the TDO-Pin being listed first. In general,
1465 whenever objects of the same type exist which require an index number, then
1466 these objects must be given in the right order (jtag_devices, targets and flash
1467 banks - a target references a jtag_device and a flash bank references a target).
1469 @item Sometimes my debugging session terminates with an error. When I look into the
1470 log file, I can see these error messages: Error: arm7_9_common.c:561
1471 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP