1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (OpenOCD)
27 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
45 * About:: About OpenOCD.
46 * Developers:: OpenOCD developers
47 * Building:: Building OpenOCD
48 * Running:: Running OpenOCD
49 * Configuration:: OpenOCD Configuration.
50 * Target library:: Target library
51 * Commands:: OpenOCD Commands
52 * Sample Scripts:: Sample Target Scripts
53 * GDB and OpenOCD:: Using GDB and OpenOCD
54 * TCL and OpenOCD:: Using TCL and OpenOCD
55 * TCL scripting API:: Tcl scripting API
56 * Upgrading:: Deprecated/Removed Commands
57 * FAQ:: Frequently Asked Questions
58 * License:: GNU Free Documentation License
66 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
67 and boundary-scan testing for embedded target devices. The targets are interfaced
68 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
69 connection types in the future.
71 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
72 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
73 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
74 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
76 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
77 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
78 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
84 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
85 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
86 Others interested in improving the state of free and open debug and testing technology
87 are welcome to participate.
89 Other developers have contributed support for additional targets and flashes as well
90 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
92 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
96 @cindex building OpenOCD
98 You can download the current SVN version with SVN client of your choice from the
99 following repositories:
101 (@uref{svn://svn.berlios.de/openocd/trunk})
105 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
107 Using the SVN command line client, you can use the following command to fetch the
108 latest version (make sure there is no (non-svn) directory called "openocd" in the
112 svn checkout svn://svn.berlios.de/openocd/trunk openocd
115 Building OpenOCD requires a recent version of the GNU autotools.
116 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
117 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
118 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
119 paths, resulting in obscure dependency errors (This is an observation I've gathered
120 from the logs of one user - correct me if I'm wrong).
122 You further need the appropriate driver files, if you want to build support for
123 a FTDI FT2232 based interface:
125 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
126 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
127 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
128 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
131 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
132 see contrib/libftdi for more details.
134 In general, the D2XX driver provides superior performance (several times as fast),
135 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
136 a kernel module, only a user space library.
138 To build OpenOCD (on both Linux and Cygwin), use the following commands:
142 Bootstrap generates the configure script, and prepares building on your system.
146 Configure generates the Makefiles used to build OpenOCD.
150 Make builds OpenOCD, and places the final executable in ./src/.
152 The configure script takes several options, specifying which JTAG interfaces
157 @option{--enable-parport}
159 @option{--enable-parport_ppdev}
161 @option{--enable-parport_giveio}
163 @option{--enable-amtjtagaccel}
165 @option{--enable-ft2232_ftd2xx}
166 @footnote{Using the latest D2XX drivers from FTDI and following their installation
167 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
170 @option{--enable-ft2232_libftdi}
172 @option{--with-ftd2xx=/path/to/d2xx/}
174 @option{--enable-gw16012}
176 @option{--enable-usbprog}
178 @option{--enable-presto_libftdi}
180 @option{--enable-presto_ftd2xx}
182 @option{--enable-jlink}
185 If you want to access the parallel port using the PPDEV interface you have to specify
186 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
187 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
188 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
190 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
191 absolute path containing no spaces.
193 Linux users should copy the various parts of the D2XX package to the appropriate
194 locations, i.e. /usr/include, /usr/lib.
196 Miscellaneous configure options
200 @option{--enable-gccwarnings} - enable extra gcc warnings during build
205 @cindex running OpenOCD
207 @cindex --debug_level
210 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
211 Run with @option{--help} or @option{-h} to view the available command line switches.
213 It reads its configuration by default from the file openocd.cfg located in the current
214 working directory. This may be overwritten with the @option{-f <configfile>} command line
215 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
216 are executed in order.
218 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
220 To enable debug output (when reporting problems or working on OpenOCD itself), use
221 the @option{-d} command line switch. This sets the debug_level to "3", outputting
222 the most information, including debug messages. The default setting is "2", outputting
223 only informational messages, warnings and errors. You can also change this setting
224 from within a telnet or gdb session (@option{debug_level <n>}).
226 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
228 Search paths for config/script files can be added to OpenOCD by using
229 the @option{-s <search>} switch. The current directory and the OpenOCD target library
230 is in the search path by default.
232 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
233 with the target. In general, it is possible for the JTAG controller to be unresponsive until
234 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
237 @chapter Configuration
238 @cindex configuration
239 OpenOCD runs as a daemon, and reads it current configuration
240 by default from the file openocd.cfg in the current directory. A different configuration
241 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
243 The configuration file is used to specify on which ports the daemon listens for new
244 connections, the JTAG interface used to connect to the target, the layout of the JTAG
245 chain, the targets that should be debugged, and connected flashes.
247 @section Daemon configuration
250 @item @b{init} This command terminates the configuration stage and enters the normal
251 command mode. This can be useful to add commands to the startup scripts and commands
252 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
253 add "init" and "reset" at the end of the config script or at the end of the
254 OpenOCD command line using the @option{-c} command line switch.
256 @item @b{telnet_port} <@var{number}>
258 Port on which to listen for incoming telnet connections
259 @item @b{gdb_port} <@var{number}>
261 First port on which to listen for incoming GDB connections. The GDB port for the
262 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
263 @item @b{gdb_breakpoint_override} <@var{hard/soft/disabled}>
264 @cindex gdb_breakpoint_override
265 hard/soft/disabled - force breakpoint type for gdb 'break' commands.
266 The raison d'etre for this option is to support GDB GUI's without
267 a hard/soft breakpoint concept where the default OpenOCD and
268 GDB behaviour is not sufficient. Note that GDB will use hardware
269 breakpoints if the memory map has been set up for flash regions.
271 This option replaces older arm7_9 target commands that addressed
273 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
275 Configures what OpenOCD will do when gdb detaches from the daeman.
276 Default behaviour is <@var{resume}>
277 @item @b{gdb_memory_map} <@var{enable|disable}>
278 @cindex gdb_memory_map
279 Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
280 requested. gdb will then know when to set hardware breakpoints, and program flash
281 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
282 for flash programming to work.
283 Default behaviour is <@var{enable}>
284 @item @b{gdb_flash_program} <@var{enable|disable}>
285 @cindex gdb_flash_program
286 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
287 vFlash packet is received.
288 Default behaviour is <@var{enable}>
289 at item @b{tcl_port} <@var{number}>
291 Port on which to listen for incoming TCL syntax. This port is intended as
292 a simplified RPC connection that can be used by clients to issue commands
293 and get the output from the TCL engine.
296 @section JTAG interface configuration
299 @item @b{interface} <@var{name}>
301 Use the interface driver <@var{name}> to connect to the target. Currently supported
305 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
308 @item @b{amt_jtagaccel}
309 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
314 FTDI FT2232 based devices using either the open-source libftdi or the binary only
315 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
316 platform. The libftdi uses libusb, and should be portable to all systems that provide
321 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
325 ASIX PRESTO USB JTAG programmer.
329 usbprog is a freely programmable USB adapter.
333 Gateworks GW16012 JTAG programmer.
337 Segger jlink usb adapter
342 @item @b{jtag_speed} <@var{reset speed}>
344 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
345 speed. The actual effect of this option depends on the JTAG interface used.
347 The speed used during reset can be adjusted using setting jtag_speed during
348 pre_reset and post_reset events.
351 @item wiggler: maximum speed / @var{number}
352 @item ft2232: 6MHz / (@var{number}+1)
353 @item amt jtagaccel: 8 / 2**@var{number}
354 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
357 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
358 especially true for synthesized cores (-S).
360 @item @b{jtag_khz} <@var{reset speed kHz}>
362 Same as jtag_speed, except that the speed is specified in maximum kHz. If
363 the device can not support the rate asked for, or can not translate from
364 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
365 is not supported, then an error is reported.
367 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
369 The configuration of the reset signals available on the JTAG interface AND the target.
370 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
371 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
372 @option{srst_only} or @option{trst_and_srst}.
374 [@var{combination}] is an optional value specifying broken reset signal implementations.
375 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
376 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
377 that the system is reset together with the test logic (only hypothetical, I haven't
378 seen hardware with such a bug, and can be worked around).
379 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
380 The default behaviour if no option given is @option{separate}.
382 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
383 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
384 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
385 (default) and @option{srst_push_pull} for the system reset. These values only affect
386 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
388 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
390 Describes the devices that form the JTAG daisy chain, with the first device being
391 the one closest to TDO. The parameters are the length of the instruction register
392 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
393 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
394 The IDCODE instruction will in future be used to query devices for their JTAG
395 identification code. This line is the same for all ARM7 and ARM9 devices.
396 Other devices, like CPLDs, require different parameters. An example configuration
397 line for a Xilinx XC9500 CPLD would look like this:
399 jtag_device 8 0x01 0x0e3 0xfe
401 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
402 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
403 The IDCODE instruction is 0xfe.
405 @item @b{jtag_nsrst_delay} <@var{ms}>
406 @cindex jtag_nsrst_delay
407 How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
408 starting new JTAG operations.
409 @item @b{jtag_ntrst_delay} <@var{ms}>
410 @cindex jtag_ntrst_delay
411 How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
412 starting new JTAG operations.
414 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
415 or on-chip features) keep a reset line asserted for some time after the external reset
419 @section parport options
422 @item @b{parport_port} <@var{number}>
424 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
425 the @file{/dev/parport} device
427 When using PPDEV to access the parallel port, use the number of the parallel port:
428 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
429 you may encounter a problem.
430 @item @b{parport_cable} <@var{name}>
431 @cindex parport_cable
432 The layout of the parallel port cable used to connect to the target.
433 Currently supported cables are
437 The original Wiggler layout, also supported by several clones, such
438 as the Olimex ARM-JTAG
439 @item @b{old_amt_wiggler}
440 @cindex old_amt_wiggler
441 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
442 version available from the website uses the original Wiggler layout ('@var{wiggler}')
445 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
448 The Xilinx Parallel cable III.
451 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
452 This is also the layout used by the HollyGates design
453 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
456 The ST Parallel cable.
458 @item @b{parport_write_on_exit} <@var{on|off}>
459 @cindex parport_write_on_exit
460 This will configure the parallel driver to write a known value to the parallel
461 interface on exiting OpenOCD
464 @section amt_jtagaccel options
466 @item @b{parport_port} <@var{number}>
468 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
469 @file{/dev/parport} device
471 @section ft2232 options
474 @item @b{ft2232_device_desc} <@var{description}>
475 @cindex ft2232_device_desc
476 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
477 default value is used. This setting is only valid if compiled with FTD2XX support.
478 @item @b{ft2232_layout} <@var{name}>
479 @cindex ft2232_layout
480 The layout of the FT2232 GPIO signals used to control output-enables and reset
481 signals. Valid layouts are
484 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
486 Amontec JTAGkey and JTAGkey-tiny
489 @item @b{olimex-jtag}
492 American Microsystems M5960
493 @item @b{evb_lm3s811}
494 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
495 SRST signals on external connector
499 Hitex STM32 Performance Stick
501 Tin Can Tools Flyswatter
502 @item @b{turtelizer2}
503 egnite Software turtelizer2
508 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
509 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
510 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
512 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
514 @item @b{ft2232_latency} <@var{ms}>
515 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
516 ft2232_read() fails to return the expected number of bytes. This can be caused by
517 USB communication delays and has proved hard to reproduce and debug. Setting the
518 FT2232 latency timer to a larger value increases delays for short USB packages but it
519 also reduces the risk of timeouts before receiving the expected number of bytes.
520 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
523 @section ep93xx options
524 @cindex ep93xx options
525 Currently, there are no options available for the ep93xx interface.
528 @section Target configuration
531 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
534 Defines a target that should be debugged. Currently supported types are:
548 If you want to use a target board that is not on this list, see Adding a new
551 Endianess may be @option{little} or @option{big}.
553 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
554 @cindex target_script
555 Event is one of the following:
556 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
557 @option{pre_resume} or @option{gdb_program_config}.
558 @option{post_reset} and @option{reset} will produce the same results.
560 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
561 <@var{backup}|@var{nobackup}>
563 Specifies a working area for the debugger to use. This may be used to speed-up
564 downloads to target memory and flash operations, or to perform otherwise unavailable
565 operations (some coprocessor operations on ARM7/9 systems, for example). The last
566 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
567 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
570 @subsection arm7tdmi options
571 @cindex arm7tdmi options
572 target arm7tdmi <@var{endianess}> <@var{jtag#}>
573 The arm7tdmi target definition requires at least one additional argument, specifying
574 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
575 The optional [@var{variant}] parameter has been removed in recent versions.
576 The correct feature set is determined at runtime.
578 @subsection arm720t options
579 @cindex arm720t options
580 ARM720t options are similar to ARM7TDMI options.
582 @subsection arm9tdmi options
583 @cindex arm9tdmi options
584 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
585 @option{arm920t}, @option{arm922t} and @option{arm940t}.
586 This enables the hardware single-stepping support found on these cores.
588 @subsection arm920t options
589 @cindex arm920t options
590 ARM920t options are similar to ARM9TDMI options.
592 @subsection arm966e options
593 @cindex arm966e options
594 ARM966e options are similar to ARM9TDMI options.
596 @subsection cortex_m3 options
597 @cindex cortex_m3 options
598 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
599 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
600 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
601 be detected and the normal reset behaviour used.
603 @subsection xscale options
604 @cindex xscale options
605 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
606 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
608 @section Flash configuration
609 @cindex Flash configuration
612 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
613 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
615 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
616 and <@var{bus_width}> bytes using the selected flash <driver>.
619 @subsection lpc2000 options
620 @cindex lpc2000 options
622 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
623 <@var{clock}> [@var{calc_checksum}]
624 LPC flashes don't require the chip and bus width to be specified. Additional
625 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
626 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
627 of the target this flash belongs to (first is 0), the frequency at which the core
628 is currently running (in kHz - must be an integral number), and the optional keyword
629 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
632 @subsection cfi options
635 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
636 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
637 CFI flashes require the number of the target they're connected to as an additional
638 argument. The CFI driver makes use of a working area (specified for the target)
639 to significantly speed up operation.
641 @var{chip_width} and @var{bus_width} are specified in bytes.
643 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
647 @subsection at91sam7 options
648 @cindex at91sam7 options
650 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
651 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
652 reading the chip-id and type.
654 @subsection str7 options
657 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
658 variant can be either STR71x, STR73x or STR75x.
660 @subsection str9 options
663 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
664 The str9 needs the flash controller to be configured prior to Flash programming, eg.
666 str9x flash_config 0 4 2 0 0x80000
668 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
670 @subsection str9 options (str9xpec driver)
672 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
673 Before using the flash commands the turbo mode will need enabling using str9xpec
674 @option{enable_turbo} <@var{num>.}
676 Only use this driver for locking/unlocking the device or configuring the option bytes.
677 Use the standard str9 driver for programming.
679 @subsection stellaris (LM3Sxxx) options
680 @cindex stellaris (LM3Sxxx) options
682 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
683 stellaris flash plugin only require the @var{target#}.
685 @subsection stm32x options
686 @cindex stm32x options
688 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
689 stm32x flash plugin only require the @var{target#}.
692 @chapter Target library
693 @cindex Target library
695 OpenOCD comes with a target configuration script library. These scripts can be
696 used as-is or serve as a starting point.
698 The target library is published together with the openocd executable and
699 the path to the target library is in the OpenOCD script search path.
700 Similarly there are example scripts for configuring the JTAG interface.
702 The command line below uses the example parport configuration scripts
703 that ship with OpenOCD, then configures the str710.cfg target and
704 finally issues the init and reset command. The communication speed
705 is set to 10kHz for reset and 8MHz for post reset.
709 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
713 To list the target scripts available:
716 $ ls /usr/local/lib/openocd/target
718 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
719 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
720 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
721 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
729 OpenOCD allows user interaction through a GDB server (default: port 3333),
730 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
731 is available from both the telnet interface and a GDB session. To issue commands to the
732 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
733 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
736 The TCL interface is used as a simplified RPC mechanism that feeds all the
737 input into the TCL interpreter and returns the output from the evaluation of
743 @item @b{sleep} <@var{msec}>
745 Wait for n milliseconds before resuming. Useful in connection with script files
746 (@var{script} command and @var{target_script} configuration).
750 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
752 @item @b{debug_level} [@var{n}]
754 Display or adjust debug level to n<0-3>
756 @item @b{fast} [@var{enable/disable}]
758 Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
759 downloads and fast memory access will work if the JTAG interface isn't too fast and
760 the core doesn't run at a too low frequency. Note that this option only changes the default
761 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
764 The target specific "dangerous" optimisation tweaking options may come and go
765 as more robust and user friendly ways are found to ensure maximum throughput
766 and robustness with a minimum of configuration.
768 Typically the "fast enable" is specified first on the command line:
771 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
774 @item @b{log_output} <@var{file}>
776 Redirect logging to <file> (default: stderr)
778 @item @b{script} <@var{file}>
780 Execute commands from <file>
784 @subsection Target state handling
786 @item @b{poll} [@option{on}|@option{off}]
788 Poll the target for its current state. If the target is in debug mode, architecture
789 specific information about the current state is printed. An optional parameter
790 allows continuous polling to be enabled and disabled.
792 @item @b{halt} [@option{ms}]
794 Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
795 Default [@option{ms}] is 5 seconds if no arg given.
796 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
797 will stop OpenOCD from waiting.
799 @item @b{wait_halt} [@option{ms}]
801 Wait for the target to enter debug mode. Optional [@option{ms}] is
802 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
805 @item @b{resume} [@var{address}]
807 Resume the target at its current code position, or at an optional address.
808 OpenOCD will wait 5 seconds for the target to resume.
810 @item @b{step} [@var{address}]
812 Single-step the target at its current code position, or at an optional address.
814 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
816 Perform a hard-reset. The optional parameter specifies what should happen after the reset.
818 With no arguments a "reset run" is executed
825 Immediately halt the target (works only with certain configurations).
828 Immediately halt the target, and execute the reset script (works only with certain
833 @subsection Memory access commands
834 These commands allow accesses of a specific size to the memory system:
836 @item @b{mdw} <@var{addr}> [@var{count}]
839 @item @b{mdh} <@var{addr}> [@var{count}]
841 display memory half-words
842 @item @b{mdb} <@var{addr}> [@var{count}]
845 @item @b{mww} <@var{addr}> <@var{value}>
848 @item @b{mwh} <@var{addr}> <@var{value}>
850 write memory half-word
851 @item @b{mwb} <@var{addr}> <@var{value}>
855 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
857 Load image <@var{file}> to target memory at <@var{address}>
858 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
860 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
861 (binary) <@var{file}>.
862 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
864 Verify <@var{file}> against target memory starting at <@var{address}>.
865 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
868 @subsection Flash commands
869 @cindex Flash commands
871 @item @b{flash banks}
873 List configured flash banks
874 @item @b{flash info} <@var{num}>
876 Print info about flash bank <@option{num}>
877 @item @b{flash probe} <@var{num}>
879 Identify the flash, or validate the parameters of the configured flash. Operation
880 depends on the flash type.
881 @item @b{flash erase_check} <@var{num}>
882 @cindex flash erase_check
883 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
884 updates the erase state information displayed by @option{flash info}. That means you have
885 to issue an @option{erase_check} command after erasing or programming the device to get
887 @item @b{flash protect_check} <@var{num}>
888 @cindex flash protect_check
889 Check protection state of sectors in flash bank <num>.
890 @option{flash erase_sector} using the same syntax.
891 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
892 @cindex flash erase_sector
893 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
894 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
895 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
897 @item @b{flash erase_address} <@var{address}> <@var{length}>
898 @cindex flash erase_address
899 Erase sectors starting at <@var{address}> for <@var{length}> bytes
900 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
901 @cindex flash write_bank
902 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
903 <@option{offset}> bytes from the beginning of the bank.
904 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
905 @cindex flash write_image
906 Write the image <@var{file}> to the current target's flash bank(s). A relocation
907 [@var{offset}] can be specified and the file [@var{type}] can be specified
908 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
909 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
910 if the @option{erase} parameter is given.
911 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
912 @cindex flash protect
913 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
914 <@var{last}> of @option{flash bank} <@var{num}>.
918 @section Target Specific Commands
919 @cindex Target Specific Commands
921 @subsection AT91SAM7 specific commands
922 @cindex AT91SAM7 specific commands
923 The flash configuration is deduced from the chip identification register. The flash
924 controller handles erases automatically on a page (128/265 byte) basis so erase is
925 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
926 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
927 that can be erased separatly. Only an EraseAll command is supported by the controller
928 for each flash plane and this is called with
930 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
931 bulk erase flash planes first_plane to last_plane.
932 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
933 @cindex at91sam7 gpnvm
934 set or clear a gpnvm bit for the processor
937 @subsection STR9 specific commands
938 @cindex STR9 specific commands
939 These are flash specific commands when using the str9xpec driver.
941 @item @b{str9xpec enable_turbo} <@var{num}>
942 @cindex str9xpec enable_turbo
943 enable turbo mode, simply this will remove the str9 from the chain and talk
944 directly to the embedded flash controller.
945 @item @b{str9xpec disable_turbo} <@var{num}>
946 @cindex str9xpec disable_turbo
947 restore the str9 into jtag chain.
948 @item @b{str9xpec lock} <@var{num}>
949 @cindex str9xpec lock
950 lock str9 device. The str9 will only respond to an unlock command that will
952 @item @b{str9xpec unlock} <@var{num}>
953 @cindex str9xpec unlock
955 @item @b{str9xpec options_read} <@var{num}>
956 @cindex str9xpec options_read
957 read str9 option bytes.
958 @item @b{str9xpec options_write} <@var{num}>
959 @cindex str9xpec options_write
960 write str9 option bytes.
963 @subsection STR9 configuration
964 @cindex STR9 configuration
966 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
967 <@var{BBADR}> <@var{NBBADR}>
968 @cindex str9x flash_config
969 Configure str9 flash controller.
971 eg. str9x flash_config 0 4 2 0 0x80000
973 BBSR - Boot Bank Size register
974 NBBSR - Non Boot Bank Size register
975 BBADR - Boot Bank Start Address register
976 NBBADR - Boot Bank Start Address register
980 @subsection STR9 option byte configuration
981 @cindex STR9 option byte configuration
983 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
984 @cindex str9xpec options_cmap
985 configure str9 boot bank.
986 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
987 @cindex str9xpec options_lvdthd
988 configure str9 lvd threshold.
989 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
990 @cindex str9xpec options_lvdsel
991 configure str9 lvd source.
992 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
993 @cindex str9xpec options_lvdwarn
994 configure str9 lvd reset warning source.
997 @subsection STM32x specific commands
998 @cindex STM32x specific commands
1000 These are flash specific commands when using the stm32x driver.
1002 @item @b{stm32x lock} <@var{num}>
1005 @item @b{stm32x unlock} <@var{num}>
1006 @cindex stm32x unlock
1007 unlock stm32 device.
1008 @item @b{stm32x options_read} <@var{num}>
1009 @cindex stm32x options_read
1010 read stm32 option bytes.
1011 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1012 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1013 @cindex stm32x options_write
1014 write stm32 option bytes.
1015 @item @b{stm32x mass_erase} <@var{num}>
1016 @cindex stm32x mass_erase
1017 mass erase flash memory.
1020 @subsection Stellaris specific commands
1021 @cindex Stellaris specific commands
1023 These are flash specific commands when using the Stellaris driver.
1025 @item @b{stellaris mass_erase} <@var{num}>
1026 @cindex stellaris mass_erase
1027 mass erase flash memory.
1031 @section Architecture Specific Commands
1032 @cindex Architecture Specific Commands
1034 @subsection ARMV4/5 specific commands
1035 @cindex ARMV4/5 specific commands
1037 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1038 or Intel XScale (XScale isn't supported yet).
1040 @item @b{armv4_5 reg}
1042 Display a list of all banked core registers, fetching the current value from every
1043 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1045 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1046 @cindex armv4_5 core_mode
1047 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1048 The target is resumed in the currently set @option{core_mode}.
1051 @subsection ARM7/9 specific commands
1052 @cindex ARM7/9 specific commands
1054 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1055 ARM920t or ARM926EJ-S.
1057 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1058 @cindex arm7_9 sw_bkpts
1059 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1060 one of the watchpoint registers to implement software breakpoints. Disabling
1061 SW Bkpts frees that register again.
1062 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1063 @cindex arm7_9 force_hw_bkpts
1064 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1065 breakpoints are turned into hardware breakpoints.
1066 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1067 @cindex arm7_9 dbgrq
1068 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1069 safe for all but ARM7TDMI--S cores (like Philips LPC).
1070 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1071 @cindex arm7_9 fast_memory_access
1072 Allow OpenOCD to read and write memory without checking completion of
1073 the operation. This provides a huge speed increase, especially with USB JTAG
1074 cables (FT2232), but might be unsafe if used with targets running at a very low
1075 speed, like the 32kHz startup clock of an AT91RM9200.
1076 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1077 @cindex arm7_9 dcc_downloads
1078 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1079 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1080 unsafe, especially with targets running at a very low speed. This command was introduced
1081 with OpenOCD rev. 60.
1084 @subsection ARM720T specific commands
1085 @cindex ARM720T specific commands
1088 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1089 @cindex arm720t cp15
1090 display/modify cp15 register <@option{num}> [@option{value}].
1091 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1092 @cindex arm720t md<bhw>_phys
1093 Display memory at physical address addr.
1094 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1095 @cindex arm720t mw<bhw>_phys
1096 Write memory at physical address addr.
1097 @item @b{arm720t virt2phys} <@var{va}>
1098 @cindex arm720t virt2phys
1099 Translate a virtual address to a physical address.
1102 @subsection ARM9TDMI specific commands
1103 @cindex ARM9TDMI specific commands
1106 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1107 @cindex arm9tdmi vector_catch
1108 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1109 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1110 @option{irq} @option{fiq}.
1112 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1115 @subsection ARM966E specific commands
1116 @cindex ARM966E specific commands
1119 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1120 @cindex arm966e cp15
1121 display/modify cp15 register <@option{num}> [@option{value}].
1124 @subsection ARM920T specific commands
1125 @cindex ARM920T specific commands
1128 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1129 @cindex arm920t cp15
1130 display/modify cp15 register <@option{num}> [@option{value}].
1131 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1132 @cindex arm920t cp15i
1133 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1134 @item @b{arm920t cache_info}
1135 @cindex arm920t cache_info
1136 Print information about the caches found. This allows you to see if your target
1137 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1138 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1139 @cindex arm920t md<bhw>_phys
1140 Display memory at physical address addr.
1141 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1142 @cindex arm920t mw<bhw>_phys
1143 Write memory at physical address addr.
1144 @item @b{arm920t read_cache} <@var{filename}>
1145 @cindex arm920t read_cache
1146 Dump the content of ICache and DCache to a file.
1147 @item @b{arm920t read_mmu} <@var{filename}>
1148 @cindex arm920t read_mmu
1149 Dump the content of the ITLB and DTLB to a file.
1150 @item @b{arm920t virt2phys} <@var{va}>
1151 @cindex arm920t virt2phys
1152 Translate a virtual address to a physical address.
1155 @subsection ARM926EJS specific commands
1156 @cindex ARM926EJS specific commands
1159 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1160 @cindex arm926ejs cp15
1161 display/modify cp15 register <@option{num}> [@option{value}].
1162 @item @b{arm926ejs cache_info}
1163 @cindex arm926ejs cache_info
1164 Print information about the caches found.
1165 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1166 @cindex arm926ejs md<bhw>_phys
1167 Display memory at physical address addr.
1168 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1169 @cindex arm926ejs mw<bhw>_phys
1170 Write memory at physical address addr.
1171 @item @b{arm926ejs virt2phys} <@var{va}>
1172 @cindex arm926ejs virt2phys
1173 Translate a virtual address to a physical address.
1177 @section Debug commands
1178 @cindex Debug commands
1179 The following commands give direct access to the core, and are most likely
1180 only useful while debugging OpenOCD.
1182 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1183 @cindex arm7_9 write_xpsr
1184 Immediately write either the current program status register (CPSR) or the saved
1185 program status register (SPSR), without changing the register cache (as displayed
1186 by the @option{reg} and @option{armv4_5 reg} commands).
1187 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1188 <@var{0=cpsr},@var{1=spsr}>
1189 @cindex arm7_9 write_xpsr_im8
1190 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1191 operation (similar to @option{write_xpsr}).
1192 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1193 @cindex arm7_9 write_core_reg
1194 Write a core register, without changing the register cache (as displayed by the
1195 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1196 encoding of the [M4:M0] bits of the PSR.
1200 @section JTAG commands
1201 @cindex JTAG commands
1203 @item @b{scan_chain}
1205 Print current scan chain configuration.
1206 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1209 @item @b{endstate} <@var{tap_state}>
1211 Finish JTAG operations in <@var{tap_state}>.
1212 @item @b{runtest} <@var{num_cycles}>
1214 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1215 @item @b{statemove} [@var{tap_state}]
1217 Move to current endstate or [@var{tap_state}]
1218 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1220 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1221 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1223 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1224 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1225 @cindex verify_ircapture
1226 Verify value captured during Capture-IR. Default is enabled.
1227 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1229 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1230 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1232 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1236 @section Target Requests
1237 @cindex Target Requests
1238 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1239 See libdcc in the contrib dir for more details.
1241 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1242 @cindex target_request debugmsgs
1243 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1246 @node Sample Scripts
1247 @chapter Sample Scripts
1250 This page shows how to use the target library.
1252 The configuration script can be divided in the following section:
1254 @item daemon configuration
1256 @item jtag scan chain
1257 @item target configuration
1258 @item flash configuration
1261 Detailed information about each section can be found at OpenOCD configuration.
1263 @section AT91R40008 example
1264 @cindex AT91R40008 example
1265 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1266 the CPU upon startup of the OpenOCD daemon.
1268 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1272 @node GDB and OpenOCD
1273 @chapter GDB and OpenOCD
1274 @cindex GDB and OpenOCD
1275 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1276 to debug remote targets.
1278 @section Connecting to gdb
1279 @cindex Connecting to gdb
1280 A connection is typically started as follows:
1282 target remote localhost:3333
1284 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1286 To see a list of available OpenOCD commands type @option{monitor help} on the
1289 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1290 to be sent by the gdb server (openocd) to gdb. Typical information includes
1291 packet size and device memory map.
1293 Previous versions of OpenOCD required the following gdb options to increase
1294 the packet size and speed up gdb communication.
1296 set remote memory-write-packet-size 1024
1297 set remote memory-write-packet-size fixed
1298 set remote memory-read-packet-size 1024
1299 set remote memory-read-packet-size fixed
1301 This is now handled in the @option{qSupported} PacketSize.
1303 @section Programming using gdb
1304 @cindex Programming using gdb
1306 By default the target memory map is sent to gdb, this can be disabled by
1307 the following OpenOCD config option:
1309 gdb_memory_map disable
1311 For this to function correctly a valid flash config must also be configured
1312 in OpenOCD. For faster performance you should also configure a valid
1315 Informing gdb of the memory map of the target will enable gdb to protect any
1316 flash area of the target and use hardware breakpoints by default. This means
1317 that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
1320 To view the configured memory map in gdb, use the gdb command @option{info mem}
1321 All other unasigned addresses within gdb are treated as RAM.
1323 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1324 this can be changed to the old behaviour by using the following gdb command.
1326 set mem inaccessible-by-default off
1329 If @option{gdb_flash_program enable} is also used, gdb will be able to
1330 program any flash memory using the vFlash interface.
1332 gdb will look at the target memory map when a load command is given, if any
1333 areas to be programmed lie within the target flash area the vFlash packets
1336 If the target needs configuring before gdb programming, a script can be executed.
1338 target_script 0 gdb_program_config config.script
1341 To verify any flash programming the gdb command @option{compare-sections}
1344 @node TCL and OpenOCD
1345 @chapter TCL and OpenOCD
1346 @cindex TCL and OpenOCD
1347 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1350 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1352 The command and file interfaces are fairly straightforward, while the network
1353 port is geared toward intergration with external clients. A small example
1354 of an external TCL script that can connect to openocd is shown below.
1357 # Simple tcl client to connect to openocd
1358 puts "Use empty line to exit"
1359 set fo [socket 127.0.0.1 6666]
1360 puts -nonewline stdout "> "
1362 while {[gets stdin line] >= 0} {
1363 if {$line eq {}} break
1368 puts -nonewline stdout "> "
1374 This script can easily be modified to front various GUIs or be a sub
1375 component of a larger framework for control and interaction.
1378 @node TCL scripting API
1379 @chapter TCL scripting API
1380 @cindex TCL scripting API
1383 The commands are stateless. E.g. the telnet command line has a concept
1384 of currently active target, the Tcl API proc's take this sort of state
1385 information as an argument to each proc.
1387 There are three main types of return values: single value, name value
1388 pair list and lists.
1390 Name value pair. The proc 'foo' below returns a name/value pair
1396 > set foo(you) Oyvind
1397 > set foo(mouse) Micky
1398 > set foo(duck) Donald
1406 me Duane you Oyvind mouse Micky duck Donald
1408 Thus, to get the names of the associative array is easy:
1410 foreach { name value } [set foo] {
1411 puts "Name: $name, Value: $value"
1415 Lists returned must be relatively small. Otherwise a range
1416 should be passed in to the proc in question.
1418 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
1419 is the low level API upon which "flash banks" is implemented.
1421 OpenOCD commands can consist of two words, e.g. "flash banks". The
1422 startup.tcl "unknown" proc will translate this into a tcl proc
1423 called "flash_banks".
1427 @chapter Deprecated/Removed Commands
1428 @cindex Deprecated/Removed Commands
1429 Certain OpenOCD commands have been deprecated/removed during the various revisions.
1432 @item @b{load_binary}
1434 use @option{load_image} command with same args
1435 @item @b{dump_binary}
1437 use @option{dump_image} command with same args
1438 @item @b{flash erase}
1440 use @option{flash erase_sector} command with same args
1441 @item @b{flash write}
1443 use @option{flash write_bank} command with same args
1444 @item @b{flash write_binary}
1445 @cindex flash write_binary
1446 use @option{flash write_bank} command with same args
1447 @item @b{arm7_9 fast_writes}
1448 @cindex arm7_9 fast_writes
1449 use @option{arm7_9 fast_memory_access} command with same args
1450 @item @b{flash auto_erase}
1451 @cindex flash auto_erase
1452 use @option{flash write_image} command passing @option{erase} as the first parameter.
1453 @item @b{daemon_startup}
1454 @cindex daemon_startup
1455 this config option has been removed, simply adding @option{init} and @option{reset halt} to
1456 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
1457 and @option{target cortex_m3 little reset_halt 0}.
1458 @item @b{run_and_halt_time}
1459 @cindex run_and_halt_time
1460 This command has been removed for simpler reset behaviour, it can be simulated with the
1473 @item OpenOCD complains about a missing cygwin1.dll.
1475 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1476 claims to come with all the necessary dlls. When using Cygwin, try launching
1477 OpenOCD from the Cygwin shell.
1479 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1480 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1481 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1483 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1484 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1485 software breakpoints consume one of the two available hardware breakpoints,
1486 and are therefore disabled by default. If your code is running from RAM, you
1487 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1488 your code resides in Flash, you can't use software breakpoints, but you can force
1489 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1491 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1492 and works sometimes fine.
1494 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1495 clock at the time you're programming the flash. If you've specified the crystal's
1496 frequency, make sure the PLL is disabled, if you've specified the full core speed
1497 (e.g. 60MHz), make sure the PLL is enabled.
1499 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1500 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1501 out while waiting for end of scan, rtck was disabled".
1503 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1504 settings in your PC BIOS (ECP, EPP, and different versions of those).
1506 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1507 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1508 memory read caused data abort".
1510 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1511 beyond the last valid frame. It might be possible to prevent this by setting up
1512 a proper "initial" stack frame, if you happen to know what exactly has to
1513 be done, feel free to add this here.
1515 @item I get the following message in the OpenOCD console (or log file):
1516 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1518 This warning doesn't indicate any serious problem, as long as you don't want to
1519 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1520 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
1521 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1522 independently. With this setup, it's not possible to halt the core right out of
1523 reset, everything else should work fine.
1525 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1526 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1527 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1528 quit with an error message. Is there a stability issue with OpenOCD?
1530 No, this is not a stability issue concerning OpenOCD. Most users have solved
1531 this issue by simply using a self-powered USB hub, which they connect their
1532 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1533 supply stable enough for the Amontec JTAGkey to be operated.
1535 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1536 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1537 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1538 What does that mean and what might be the reason for this?
1540 First of all, the reason might be the USB power supply. Try using a self-powered
1541 hub instead of a direct connection to your computer. Secondly, the error code 4
1542 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1543 chip ran into some sort of error - this points us to a USB problem.
1545 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1546 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1547 What does that mean and what might be the reason for this?
1549 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1550 has closed the connection to OpenOCD. This might be a GDB issue.
1552 @item In the configuration file in the section where flash device configurations
1553 are described, there is a parameter for specifying the clock frequency for
1554 LPC2000 internal flash devices (e.g.
1555 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1556 which must be specified in kilohertz. However, I do have a quartz crystal of a
1557 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1558 Is it possible to specify real numbers for the clock frequency?
1560 No. The clock frequency specified here must be given as an integral number.
1561 However, this clock frequency is used by the In-Application-Programming (IAP)
1562 routines of the LPC2000 family only, which seems to be very tolerant concerning
1563 the given clock frequency, so a slight difference between the specified clock
1564 frequency and the actual clock frequency will not cause any trouble.
1566 @item Do I have to keep a specific order for the commands in the configuration file?
1568 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1569 listed for the JTAG scan chain must be given in the right order (jtag_device),
1570 with the device closest to the TDO-Pin being listed first. In general,
1571 whenever objects of the same type exist which require an index number, then
1572 these objects must be given in the right order (jtag_devices, targets and flash
1573 banks - a target references a jtag_device and a flash bank references a target).
1575 @item Sometimes my debugging session terminates with an error. When I look into the
1576 log file, I can see these error messages: Error: arm7_9_common.c:561
1577 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP