1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developers
64 * JTAG Hardware Dongles:: JTAG Hardware Dongles
65 * About JIM-Tcl:: About JIM-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Daemon Configuration:: Daemon Configuration
70 * Interface - Dongle Configuration:: Interface - Dongle Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * NAND Flash Commands:: NAND Flash Commands
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * Upgrading:: Deprecated/Removed Commands
85 * Target Library:: Target Library
86 * FAQ:: Frequently Asked Questions
87 * Tcl Crash Course:: Tcl Crash Course
88 * License:: GNU Free Documentation License
90 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
91 @comment case issue with ``Index.html'' and ``index.html''
92 @comment Occurs when creating ``--html --no-split'' output
93 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
94 * OpenOCD Concept Index:: Concept Index
95 * Command and Driver Index:: Command and Driver Index
102 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
103 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
104 Since that time, the project has grown into an active open-source project,
105 supported by a diverse community of software and hardware developers from
108 @section What is OpenOCD?
112 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
113 in-system programming and boundary-scan testing for embedded target
116 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
117 with the JTAG (IEEE 1149.1) compliant TAPs on your target board.
118 A @dfn{TAP} is a ``Test Access Port'', a module which processes
119 special instructions and data. TAPs are daisy-chained within and
120 between chips and boards.
122 @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
123 based, parallel port based, and other standalone boxes that run
124 OpenOCD internally. @xref{JTAG Hardware Dongles}.
126 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
127 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
128 Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be
129 debugged via the GDB protocol.
131 @b{Flash Programing:} Flash writing is supported for external CFI
132 compatible NOR flashes (Intel and AMD/Spansion command set) and several
133 internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
134 STM32x). Preliminary support for various NAND flash controllers
135 (LPC3180, Orion, S3C24xx, more) controller is included.
137 @section OpenOCD Web Site
139 The OpenOCD web site provides the latest public news from the community:
141 @uref{http://openocd.berlios.de/web/}
143 @section Latest User's Guide:
145 The user's guide you are now reading may not be the latest one
146 available. A version for more recent code may be available.
147 Its HTML form is published irregularly at:
149 @uref{http://openocd.berlios.de/doc/html/index.html}
151 PDF form is likewise published at:
153 @uref{http://openocd.berlios.de/doc/pdf/openocd.pdf}
155 @section OpenOCD User's Forum
157 There is an OpenOCD forum (phpBB) hosted by SparkFun:
159 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
163 @chapter OpenOCD Developer Resources
166 If you are interested in improving the state of OpenOCD's debugging and
167 testing support, new contributions will be welcome. Motivated developers
168 can produce new target, flash or interface drivers, improve the
169 documentation, as well as more conventional bug fixes and enhancements.
171 The resources in this chapter are available for developers wishing to explore
172 or expand the OpenOCD source code.
174 @section OpenOCD Subversion Repository
176 You can download the current SVN version with an SVN client of your
177 choice from the following repositories:
179 @uref{svn://svn.berlios.de/openocd/trunk}
183 @uref{http://svn.berlios.de/svnroot/repos/openocd/trunk}
185 Using the SVN command line client, you can use the following command to
186 fetch the latest version (make sure there is no (non-svn) directory
187 called "openocd" in the current directory):
189 svn checkout svn://svn.berlios.de/openocd/trunk openocd
191 If you prefer GIT based tools, the @command{git-svn} package works too:
193 git svn clone -s svn://svn.berlios.de/openocd
195 The ``README'' file contains the instructions for building the project
198 Developers that want to contribute patches to the OpenOCD system are
199 @b{strongly} encouraged to base their work off of the most recent trunk
200 revision. Patches created against older versions may require additional
201 work from their submitter in order to be updated for newer releases.
203 @section Doxygen Developer Manual
205 During the development of the 0.2.0 release, the OpenOCD project began
206 providing a Doxygen reference manual. This document contains more
207 technical information about the software internals, development
208 processes, and similar documentation:
210 @uref{http://openocd.berlios.de/doc/doxygen/index.html}
212 This document is a work-in-progress, but contributions would be welcome
213 to fill in the gaps. All of the source files are provided in-tree,
214 listed in the Doxyfile configuration in the top of the repository trunk.
216 @section OpenOCD Developer Mailing List
218 The OpenOCD Developer Mailing List provides the primary means of
219 communication between developers:
221 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
223 All drivers developers are enouraged to also subscribe to the list of
224 SVN commits to keep pace with the ongoing changes:
226 @uref{https://lists.berlios.de/mailman/listinfo/openocd-svn}
229 @node JTAG Hardware Dongles
230 @chapter JTAG Hardware Dongles
239 Defined: @b{dongle}: A small device that plugins into a computer and serves as
240 an adapter .... [snip]
242 In the OpenOCD case, this generally refers to @b{a small adapater} one
243 attaches to your computer via USB or the Parallel Printer Port. The
244 execption being the Zylin ZY1000 which is a small box you attach via
245 an ethernet cable. The Zylin ZY1000 has the advantage that it does not
246 require any drivers to be installed on the developer PC. It also has
247 a built in web interface. It supports RTCK/RCLK or adaptive clocking
248 and has a built in relay to power cycle targets remotely.
251 @section Choosing a Dongle
253 There are several things you should keep in mind when choosing a dongle.
256 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
257 Does your dongle support it? You might need a level converter.
258 @item @b{Pinout} What pinout does your target board use?
259 Does your dongle support it? You may be able to use jumper
260 wires, or an "octopus" connector, to convert pinouts.
261 @item @b{Connection} Does your computer have the USB, printer, or
262 Ethernet port needed?
263 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
266 @section Stand alone Systems
268 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
269 dongle, but a standalone box. The ZY1000 has the advantage that it does
270 not require any drivers installed on the developer PC. It also has
271 a built in web interface. It supports RTCK/RCLK or adaptive clocking
272 and has a built in relay to power cycle targets remotely.
274 @section USB FT2232 Based
276 There are many USB JTAG dongles on the market, many of them are based
277 on a chip from ``Future Technology Devices International'' (FTDI)
278 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
279 See: @url{http://www.ftdichip.com} for more information.
280 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
281 chips are starting to become available in JTAG adapters.
285 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
287 @* See: @url{http://www.amontec.com/jtagkey.shtml}
289 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
291 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
293 @* See: @url{http://www.signalyzer.com}
294 @item @b{evb_lm3s811}
295 @* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
296 @item @b{luminary_icdi}
297 @* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
298 @item @b{olimex-jtag}
299 @* See: @url{http://www.olimex.com}
301 @* See: @url{http://www.tincantools.com}
302 @item @b{turtelizer2}
304 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
305 @url{http://www.ethernut.de}
307 @* Link: @url{http://www.hitex.com/index.php?id=383}
309 @* Link @url{http://www.hitex.com/stm32-stick}
310 @item @b{axm0432_jtag}
311 @* Axiom AXM-0432 Link @url{http://www.axman.com}
313 @* Link @url{http://www.hitex.com/index.php?id=cortino}
316 @section USB JLINK based
317 There are several OEM versions of the Segger @b{JLINK} adapter. It is
318 an example of a micro controller based JTAG adapter, it uses an
319 AT91SAM764 internally.
322 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
323 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
324 @item @b{SEGGER JLINK}
325 @* Link: @url{http://www.segger.com/jlink.html}
327 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
330 @section USB RLINK based
331 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer, permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for SWD and not JTAG, thus not supported.
334 @item @b{Raisonance RLink}
335 @* Link: @url{http://www.raisonance.com/products/RLink.php}
336 @item @b{STM32 Primer}
337 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
338 @item @b{STM32 Primer2}
339 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
345 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
347 @item @b{USB - Presto}
348 @* Link: @url{http://tools.asix.net/prg_presto.htm}
350 @item @b{Versaloon-Link}
351 @* Link: @url{http://www.simonqian.com/en/Versaloon}
353 @item @b{ARM-JTAG-EW}
354 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
357 @section IBM PC Parallel Printer Port Based
359 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
360 and the MacGraigor Wiggler. There are many clones and variations of
363 Note that parallel ports are becoming much less common, so if you
364 have the choice you should probably avoid these adapters in favor
369 @item @b{Wiggler} - There are many clones of this.
370 @* Link: @url{http://www.macraigor.com/wiggler.htm}
372 @item @b{DLC5} - From XILINX - There are many clones of this
373 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
374 produced, PDF schematics are easily found and it is easy to make.
376 @item @b{Amontec - JTAG Accelerator}
377 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
380 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
383 @*@uref{http://www.ccac.rwth-aachen.de/@/~michaels/@/index.php/hardware/@/armjtag,
384 Improved parallel-port wiggler-style JTAG adapter}
386 @item @b{Wiggler_ntrst_inverted}
387 @* Yet another variation - See the source code, src/jtag/parport.c
389 @item @b{old_amt_wiggler}
390 @* Unknown - probably not on the market today
393 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
396 @* Link: @url{http://www.amontec.com/chameleon.shtml}
402 @* ispDownload from Lattice Semiconductor
403 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
406 @* From ST Microsystems;
407 @uref{http://www.st.com/stonline/@/products/literature/um/7889.pdf,
408 FlashLINK JTAG programing cable for PSD and uPSD}
416 @* An EP93xx based Linux machine using the GPIO pins directly.
419 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
424 @chapter About JIM-Tcl
428 OpenOCD includes a small ``Tcl Interpreter'' known as JIM-Tcl.
429 This programming language provides a simple and extensible
432 All commands presented in this Guide are extensions to JIM-Tcl.
433 You can use them as simple commands, without needing to learn
434 much of anything about Tcl.
435 Alternatively, can write Tcl programs with them.
437 You can learn more about JIM at its website, @url{http://jim.berlios.de}.
440 @item @b{JIM vs. Tcl}
441 @* JIM-TCL is a stripped down version of the well known Tcl language,
442 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
443 fewer features. JIM-Tcl is a single .C file and a single .H file and
444 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
445 4.2 MB .zip file containing 1540 files.
447 @item @b{Missing Features}
448 @* Our practice has been: Add/clone the real Tcl feature if/when
449 needed. We welcome JIM Tcl improvements, not bloat.
452 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
453 command interpreter today is a mixture of (newer)
454 JIM-Tcl commands, and (older) the orginal command interpreter.
457 @* At the OpenOCD telnet command line (or via the GDB mon command) one
458 can type a Tcl for() loop, set variables, etc.
459 Some of the commands documented in this guide are implemented
460 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
462 @item @b{Historical Note}
463 @* JIM-Tcl was introduced to OpenOCD in spring 2008.
465 @item @b{Need a crash course in Tcl?}
466 @*@xref{Tcl Crash Course}.
471 @cindex command line options
473 @cindex directory search
475 The @option{--help} option shows:
479 --help | -h display this help
480 --version | -v display OpenOCD version
481 --file | -f use configuration file <name>
482 --search | -s dir to search for config files and scripts
483 --debug | -d set debug level <0-3>
484 --log_output | -l redirect log output to file <name>
485 --command | -c run <command>
486 --pipe | -p use pipes when talking to gdb
489 By default OpenOCD reads the file configuration file @file{openocd.cfg}
490 in the current directory. To specify a different (or multiple)
491 configuration file, you can use the ``-f'' option. For example:
494 openocd -f config1.cfg -f config2.cfg -f config3.cfg
497 OpenOCD starts by processing the configuration commands provided
498 on the command line or in @file{openocd.cfg}.
499 @xref{Configuration Stage}.
500 At the end of the configuration stage it verifies the JTAG scan
501 chain defined using those commands; your configuration should
502 ensure that this always succeeds.
503 Normally, OpenOCD then starts running as a daemon.
504 Alternatively, commands may be used to terminate the configuration
505 stage early, perform work (such as updating some flash memory),
506 and then shut down without acting as a daemon.
508 Once OpenOCD starts running as a daemon, it waits for connections from
509 clients (Telnet, GDB, Other) and processes the commands issued through
512 If you are having problems, you can enable internal debug messages via
515 Also it is possible to interleave JIM-Tcl commands w/config scripts using the
516 @option{-c} command line switch.
518 To enable debug output (when reporting problems or working on OpenOCD
519 itself), use the @option{-d} command line switch. This sets the
520 @option{debug_level} to "3", outputting the most information,
521 including debug messages. The default setting is "2", outputting only
522 informational messages, warnings and errors. You can also change this
523 setting from within a telnet or gdb session using @command{debug_level
524 <n>} (@pxref{debug_level}).
526 You can redirect all output from the daemon to a file using the
527 @option{-l <logfile>} switch.
529 Search paths for config/script files can be added to OpenOCD by using
530 the @option{-s <search>} switch. The current directory and the OpenOCD
531 target library is in the search path by default.
533 For details on the @option{-p} option. @xref{Connecting to GDB}.
535 Note! OpenOCD will launch the GDB & telnet server even if it can not
536 establish a connection with the target. In general, it is possible for
537 the JTAG controller to be unresponsive until the target is set up
538 correctly via e.g. GDB monitor commands in a GDB init script.
540 @node OpenOCD Project Setup
541 @chapter OpenOCD Project Setup
543 To use OpenOCD with your development projects, you need to do more than
544 just connecting the JTAG adapter hardware (dongle) to your development board
545 and then starting the OpenOCD server.
546 You also need to configure that server so that it knows
547 about that adapter and board, and helps your work.
549 @section Hooking up the JTAG Adapter
551 Today's most common case is a dongle with a JTAG cable on one side
552 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
553 and a USB cable on the other.
554 Instead of USB, some cables use Ethernet;
555 older ones may use a PC parallel port, or even a serial port.
558 @item @emph{Start with power to your target board turned off},
559 and nothing connected to your JTAG adapter.
560 If you're particularly paranoid, unplug power to the board.
561 It's important to have the ground signal properly set up,
562 unless you are using a JTAG adapter which provides
563 galvanic isolation between the target board and the
566 @item @emph{Be sure it's the right kind of JTAG connector.}
567 If your dongle has a 20-pin ARM connector, you need some kind
568 of adapter (or octopus, see below) to hook it up to
569 boards using 14-pin or 10-pin connectors ... or to 20-pin
570 connectors which don't use ARM's pinout.
572 In the same vein, make sure the voltage levels are compatible.
573 Not all JTAG adapters have the level shifters needed to work
574 with 1.2 Volt boards.
576 @item @emph{Be certain the cable is properly oriented} or you might
577 damage your board. In most cases there are only two possible
578 ways to connect the cable.
579 Connect the JTAG cable from your adapter to the board.
580 Be sure it's firmly connected.
582 In the best case, the connector is keyed to physically
583 prevent you from inserting it wrong.
584 This is most often done using a slot on the board's male connector
585 housing, which must match a key on the JTAG cable's female connector.
586 If there's no housing, then you must look carefully and
587 make sure pin 1 on the cable hooks up to pin 1 on the board.
588 Ribbon cables are frequently all grey except for a wire on one
589 edge, which is red. The red wire is pin 1.
591 Sometimes dongles provide cables where one end is an ``octopus'' of
592 color coded single-wire connectors, instead of a connector block.
593 These are great when converting from one JTAG pinout to another,
594 but are tedious to set up.
595 Use these with connector pinout diagrams to help you match up the
596 adapter signals to the right board pins.
598 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
599 A USB, parallel, or serial port connector will go to the host which
600 you are using to run OpenOCD.
601 For Ethernet, consult the documentation and your network administrator.
603 For USB based JTAG adapters you have an easy sanity check at this point:
604 does the host operating system see the JTAG adapter?
606 @item @emph{Connect the adapter's power supply, if needed.}
607 This step is primarily for non-USB adapters,
608 but sometimes USB adapters need extra power.
610 @item @emph{Power up the target board.}
611 Unless you just let the magic smoke escape,
612 you're now ready to set up the OpenOCD server
613 so you can use JTAG to work with that board.
617 Talk with the OpenOCD server using
618 telnet (@code{telnet localhost 4444} on many systems) or GDB.
619 @xref{GDB and OpenOCD}.
621 @section Project Directory
623 There are many ways you can configure OpenOCD and start it up.
625 A simple way to organize them all involves keeping a
626 single directory for your work with a given board.
627 When you start OpenOCD from that directory,
628 it searches there first for configuration files, scripts,
629 and for code you upload to the target board.
630 It is also the natural place to write files,
631 such as log files and data you download from the board.
633 @section Configuration Basics
635 There are two basic ways of configuring OpenOCD, and
636 a variety of ways you can mix them.
637 Think of the difference as just being how you start the server:
640 @item Many @option{-f file} or @option{-c command} options on the command line
641 @item No options, but a @dfn{user config file}
642 in the current directory named @file{openocd.cfg}
645 Here is an example @file{openocd.cfg} file for a setup
646 using a Signalyzer FT2232-based JTAG adapter to talk to
647 a board with an Atmel AT91SAM7X256 microcontroller:
650 source [find interface/signalyzer.cfg]
652 # GDB can also flash my flash!
653 gdb_memory_map enable
654 gdb_flash_program enable
656 source [find target/sam7x256.cfg]
659 Here is the command line equivalent of that configuration:
662 openocd -f interface/signalyzer.cfg \
663 -c "gdb_memory_map enable" \
664 -c "gdb_flash_program enable" \
665 -f target/sam7x256.cfg
668 You could wrap such long command lines in shell scripts,
669 each supporting a different development task.
670 One might re-flash the board with a specific firmware version.
671 Another might set up a particular debugging or run-time environment.
673 Here we will focus on the simpler solution: one user config
674 file, including basic configuration plus any TCL procedures
675 to simplify your work.
677 @section User Config Files
678 @cindex config file, user
679 @cindex user config file
680 @cindex config file, overview
682 A user configuration file ties together all the parts of a project
684 One of the following will match your situation best:
687 @item Ideally almost everything comes from configuration files
688 provided by someone else.
689 For example, OpenOCD distributes a @file{scripts} directory
690 (probably in @file{/usr/share/openocd/scripts} on Linux).
691 Board and tool vendors can provide these too, as can individual
692 user sites; the @option{-s} command line option lets you say
693 where to find these files. (@xref{Running}.)
694 The AT91SAM7X256 example above works this way.
696 Three main types of non-user configuration file each have their
697 own subdirectory in the @file{scripts} directory:
700 @item @b{interface} -- one for each kind of JTAG adapter/dongle
701 @item @b{board} -- one for each different board
702 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
705 Best case: include just two files, and they handle everything else.
706 The first is an interface config file.
707 The second is board-specific, and it sets up the JTAG TAPs and
708 their GDB targets (by deferring to some @file{target.cfg} file),
709 declares all flash memory, and leaves you nothing to do except
713 source [find interface/olimex-jtag-tiny.cfg]
714 source [find board/csb337.cfg]
717 Boards with a single microcontroller often won't need more
718 than the target config file, as in the AT91SAM7X256 example.
719 That's because there is no external memory (flash, DDR RAM), and
720 the board differences are encapsulated by application code.
722 @item You can often reuse some standard config files but
723 need to write a few new ones, probably a @file{board.cfg} file.
724 You will be using commands described later in this User's Guide,
725 and working with the guidelines in the next chapter.
727 For example, there may be configuration files for your JTAG adapter
728 and target chip, but you need a new board-specific config file
729 giving access to your particular flash chips.
730 Or you might need to write another target chip configuration file
731 for a new chip built around the Cortex M3 core.
734 When you write new configuration files, please submit
735 them for inclusion in the next OpenOCD release.
736 For example, a @file{board/newboard.cfg} file will help the
737 next users of that board, and a @file{target/newcpu.cfg}
738 will help support users of any board using that chip.
742 You may may need to write some C code.
743 It may be as simple as a supporting a new ft2232 or parport
744 based dongle; a bit more involved, like a NAND or NOR flash
745 controller driver; or a big piece of work like supporting
746 a new chip architecture.
749 Reuse the existing config files when you can.
750 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
751 You may find a board configuration that's a good example to follow.
753 When you write config files, separate the reusable parts
754 (things every user of that interface, chip, or board needs)
755 from ones specific to your environment and debugging approach.
759 For example, a @code{gdb-attach} event handler that invokes
760 the @command{reset init} command will interfere with debugging
761 early boot code, which performs some of the same actions
762 that the @code{reset-init} event handler does.
765 Likewise, the @command{arm9tdmi vector_catch} command (or
767 its siblings @command{xscale vector_catch}
768 and @command{cortex_m3 vector_catch}) can be a timesaver
769 during some debug sessions, but don't make everyone use that either.
770 Keep those kinds of debugging aids in your user config file,
771 along with messaging and tracing setup.
772 (@xref{Software Debug Messages and Tracing}.)
775 You might need to override some defaults.
776 For example, you might need to move, shrink, or back up the target's
777 work area if your application needs much SRAM.
780 TCP/IP port configuration is another example of something which
781 is environment-specific, and should only appear in
782 a user config file. @xref{TCP/IP Ports}.
785 @section Project-Specific Utilities
787 A few project-specific utility
788 routines may well speed up your work.
789 Write them, and keep them in your project's user config file.
791 For example, if you are making a boot loader work on a
792 board, it's nice to be able to debug the ``after it's
793 loaded to RAM'' parts separately from the finicky early
794 code which sets up the DDR RAM controller and clocks.
795 A script like this one, or a more GDB-aware sibling,
799 proc ramboot @{ @} @{
800 # Reset, running the target's "reset-init" scripts
801 # to initialize clocks and the DDR RAM controller.
802 # Leave the CPU halted.
805 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
806 load_image u-boot.bin 0x20000000
813 Then once that code is working you will need to make it
814 boot from NOR flash; a different utility would help.
815 Alternatively, some developers write to flash using GDB.
816 (You might use a similar script if you're working with a flash
817 based microcontroller application instead of a boot loader.)
820 proc newboot @{ @} @{
821 # Reset, leaving the CPU halted. The "reset-init" event
822 # proc gives faster access to the CPU and to NOR flash;
823 # "reset halt" would be slower.
826 # Write standard version of U-Boot into the first two
827 # sectors of NOR flash ... the standard version should
828 # do the same lowlevel init as "reset-init".
829 flash protect 0 0 1 off
830 flash erase_sector 0 0 1
831 flash write_bank 0 u-boot.bin 0x0
832 flash protect 0 0 1 on
834 # Reboot from scratch using that new boot loader.
839 You may need more complicated utility procedures when booting
841 That often involves an extra bootloader stage,
842 running from on-chip SRAM to perform DDR RAM setup so it can load
843 the main bootloader code (which won't fit into that SRAM).
845 Other helper scripts might be used to write production system images,
846 involving considerably more than just a three stage bootloader.
848 @section Target Software Changes
850 Sometimes you may want to make some small changes to the software
851 you're developing, to help make JTAG debugging work better.
852 For example, in C or assembly language code you might
853 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
854 handling issues like:
858 @item @b{ARM Wait-For-Interrupt}...
859 Many ARM chips synchronize the JTAG clock using the core clock.
860 Low power states which stop that core clock thus prevent JTAG access.
861 Idle loops in tasking environments often enter those low power states
862 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
864 You may want to @emph{disable that instruction} in source code,
865 or otherwise prevent using that state,
866 to ensure you can get JTAG access at any time.
867 For example, the OpenOCD @command{halt} command may not
868 work for an idle processor otherwise.
870 @item @b{Delay after reset}...
871 Not all chips have good support for debugger access
872 right after reset; many LPC2xxx chips have issues here.
873 Similarly, applications that reconfigure pins used for
874 JTAG access as they start will also block debugger access.
876 To work with boards like this, @emph{enable a short delay loop}
877 the first thing after reset, before "real" startup activities.
878 For example, one second's delay is usually more than enough
879 time for a JTAG debugger to attach, so that
880 early code execution can be debugged
881 or firmware can be replaced.
883 @item @b{Debug Communications Channel (DCC)}...
884 Some processors include mechanisms to send messages over JTAG.
885 Many ARM cores support these, as do some cores from other vendors.
886 (OpenOCD may be able to use this DCC internally, speeding up some
887 operations like writing to memory.)
889 Your application may want to deliver various debugging messages
890 over JTAG, by @emph{linking with a small library of code}
891 provided with OpenOCD and using the utilities there to send
892 various kinds of message.
893 @xref{Software Debug Messages and Tracing}.
897 @node Config File Guidelines
898 @chapter Config File Guidelines
900 This chapter is aimed at any user who needs to write a config file,
901 including developers and integrators of OpenOCD and any user who
902 needs to get a new board working smoothly.
903 It provides guidelines for creating those files.
905 You should find the following directories under @t{$(INSTALLDIR)/scripts}:
908 @item @file{interface} ...
909 think JTAG Dongle. Files that configure JTAG adapters go here.
910 @item @file{board} ...
911 think Circuit Board, PWA, PCB, they go by many names. Board files
912 contain initialization items that are specific to a board. For
913 example, the SDRAM initialization sequence for the board, or the type
914 of external flash and what address it uses. Any initialization
915 sequence to enable that external flash or SDRAM should be found in the
916 board file. Boards may also contain multiple targets: two CPUs; or
917 a CPU and an FPGA or CPLD.
918 @item @file{target} ...
919 think chip. The ``target'' directory represents the JTAG TAPs
921 which OpenOCD should control, not a board. Two common types of targets
922 are ARM chips and FPGA or CPLD chips.
923 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
924 the target config file defines all of them.
927 The @file{openocd.cfg} user config
928 file may override features in any of the above files by
929 setting variables before sourcing the target file, or by adding
930 commands specific to their situation.
932 @section Interface Config Files
935 should be able to source one of these files with a command like this:
938 source [find interface/FOOBAR.cfg]
941 A preconfigured interface file should exist for every interface in use
942 today, that said, perhaps some interfaces have only been used by the
943 sole developer who created it.
945 A separate chapter gives information about how to set these up.
946 @xref{Interface - Dongle Configuration}.
947 Read the OpenOCD source code if you have a new kind of hardware interface
948 and need to provide a driver for it.
950 @section Board Config Files
951 @cindex config file, board
952 @cindex board config file
955 should be able to source one of these files with a command like this:
958 source [find board/FOOBAR.cfg]
961 The point of a board config file is to package everything
962 about a given board that user config files need to know.
963 In summary the board files should contain (if present)
966 @item One or more @command{source [target/...cfg]} statements
967 @item NOR flash configuration (@pxref{NOR Configuration})
968 @item NAND flash configuration (@pxref{NAND Configuration})
969 @item Target @code{reset} handlers for SDRAM and I/O configuration
970 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
971 @item All things that are not ``inside a chip''
974 Generic things inside target chips belong in target config files,
975 not board config files. So for example a @code{reset-init} event
976 handler should know board-specific oscillator and PLL parameters,
977 which it passes to target-specific utility code.
979 The most complex task of a board config file is creating such a
980 @code{reset-init} event handler.
981 Define those handlers last, after you verify the rest of the board
984 @subsection Communication Between Config files
986 In addition to target-specific utility code, another way that
987 board and target config files communicate is by following a
988 convention on how to use certain variables.
990 The full Tcl/Tk language supports ``namespaces'', but JIM-Tcl does not.
991 Thus the rule we follow in OpenOCD is this: Variables that begin with
992 a leading underscore are temporary in nature, and can be modified and
993 used at will within a target configuration file.
995 Complex board config files can do the things like this,
996 for a board with three chips:
999 # Chip #1: PXA270 for network side, big endian
1000 set CHIPNAME network
1002 source [find target/pxa270.cfg]
1003 # on return: _TARGETNAME = network.cpu
1004 # other commands can refer to the "network.cpu" target.
1005 $_TARGETNAME configure .... events for this CPU..
1007 # Chip #2: PXA270 for video side, little endian
1010 source [find target/pxa270.cfg]
1011 # on return: _TARGETNAME = video.cpu
1012 # other commands can refer to the "video.cpu" target.
1013 $_TARGETNAME configure .... events for this CPU..
1015 # Chip #3: Xilinx FPGA for glue logic
1018 source [find target/spartan3.cfg]
1021 That example is oversimplified because it doesn't show any flash memory,
1022 or the @code{reset-init} event handlers to initialize external DRAM
1023 or (assuming it needs it) load a configuration into the FPGA.
1024 Such features are usually needed for low-level work with many boards,
1025 where ``low level'' implies that the board initialization software may
1026 not be working. (That's a common reason to need JTAG tools. Another
1027 is to enable working with microcontroller-based systems, which often
1028 have no debugging support except a JTAG connector.)
1030 Target config files may also export utility functions to board and user
1031 config files. Such functions should use name prefixes, to help avoid
1034 Board files could also accept input variables from user config files.
1035 For example, there might be a @code{J4_JUMPER} setting used to identify
1036 what kind of flash memory a development board is using, or how to set
1037 up other clocks and peripherals.
1039 @subsection Variable Naming Convention
1040 @cindex variable names
1042 Most boards have only one instance of a chip.
1043 However, it should be easy to create a board with more than
1044 one such chip (as shown above).
1045 Accordingly, we encourage these conventions for naming
1046 variables associated with different @file{target.cfg} files,
1047 to promote consistency and
1048 so that board files can override target defaults.
1050 Inputs to target config files include:
1053 @item @code{CHIPNAME} ...
1054 This gives a name to the overall chip, and is used as part of
1055 tap identifier dotted names.
1056 While the default is normally provided by the chip manufacturer,
1057 board files may need to distinguish between instances of a chip.
1058 @item @code{ENDIAN} ...
1059 By default @option{little} - although chips may hard-wire @option{big}.
1060 Chips that can't change endianness don't need to use this variable.
1061 @item @code{CPUTAPID} ...
1062 When OpenOCD examines the JTAG chain, it can be told verify the
1063 chips against the JTAG IDCODE register.
1064 The target file will hold one or more defaults, but sometimes the
1065 chip in a board will use a different ID (perhaps a newer revision).
1068 Outputs from target config files include:
1071 @item @code{_TARGETNAME} ...
1072 By convention, this variable is created by the target configuration
1073 script. The board configuration file may make use of this variable to
1074 configure things like a ``reset init'' script, or other things
1075 specific to that board and that target.
1076 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1077 @code{_TARGETNAME1}, ... etc.
1080 @subsection The reset-init Event Handler
1081 @cindex event, reset-init
1082 @cindex reset-init handler
1084 Board config files run in the OpenOCD configuration stage;
1085 they can't use TAPs or targets, since they haven't been
1087 This means you can't write memory or access chip registers;
1088 you can't even verify that a flash chip is present.
1089 That's done later in event handlers, of which the target @code{reset-init}
1090 handler is one of the most important.
1092 Except on microcontrollers, the basic job of @code{reset-init} event
1093 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1094 Microcontrollers rarely use boot loaders; they run right out of their
1095 on-chip flash and SRAM memory. But they may want to use one of these
1096 handlers too, if just for developer convenience.
1099 Because this is so very board-specific, and chip-specific, no examples
1101 Instead, look at the board config files distributed with OpenOCD.
1102 If you have a boot loader, its source code may also be useful.
1105 Some of this code could probably be shared between different boards.
1106 For example, setting up a DRAM controller often doesn't differ by
1107 much except the bus width (16 bits or 32?) and memory timings, so a
1108 reusable TCL procedure loaded by the @file{target.cfg} file might take
1109 those as parameters.
1110 Similarly with oscillator, PLL, and clock setup;
1111 and disabling the watchdog.
1112 Structure the code cleanly, and provide comments to help
1113 the next developer doing such work.
1114 (@emph{You might be that next person} trying to reuse init code!)
1116 The last thing normally done in a @code{reset-init} handler is probing
1117 whatever flash memory was configured. For most chips that needs to be
1118 done while the associated target is halted, either because JTAG memory
1119 access uses the CPU or to prevent conflicting CPU access.
1121 @subsection JTAG Clock Rate
1123 Before your @code{reset-init} handler has set up
1124 the PLLs and clocking, you may need to run with
1125 a low JTAG clock rate.
1127 Then you'd increase that rate after your handler has
1128 made it possible to use the faster JTAG clock.
1129 When the initial low speed is board-specific, for example
1130 because it depends on a board-specific oscillator speed, then
1131 you should probably set it up in the board config file;
1132 if it's target-specific, it belongs in the target config file.
1134 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1135 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1136 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1137 Consult chip documentation to determine the peak JTAG clock rate,
1138 which might be less than that.
1141 On most ARMs, JTAG clock detection is coupled to the core clock, so
1142 software using a @option{wait for interrupt} operation blocks JTAG access.
1143 Adaptive clocking provides a partial workaround, but a more complete
1144 solution just avoids using that instruction with JTAG debuggers.
1147 If the board supports adaptive clocking, use the @command{jtag_rclk}
1148 command, in case your board is used with JTAG adapter which
1149 also supports it. Otherwise use @command{jtag_khz}.
1150 Set the slow rate at the beginning of the reset sequence,
1151 and the faster rate as soon as the clocks are at full speed.
1153 @section Target Config Files
1154 @cindex config file, target
1155 @cindex target config file
1157 Board config files communicate with target config files using
1158 naming conventions as described above, and may source one or
1159 more target config files like this:
1162 source [find target/FOOBAR.cfg]
1165 The point of a target config file is to package everything
1166 about a given chip that board config files need to know.
1167 In summary the target files should contain
1171 @item Add TAPs to the scan chain
1172 @item Add CPU targets (includes GDB support)
1173 @item CPU/Chip/CPU-Core specific features
1177 As a rule of thumb, a target file sets up only one chip.
1178 For a microcontroller, that will often include a single TAP,
1179 which is a CPU needing a GDB target, and its on-chip flash.
1181 More complex chips may include multiple TAPs, and the target
1182 config file may need to define them all before OpenOCD
1183 can talk to the chip.
1184 For example, some phone chips have JTAG scan chains that include
1185 an ARM core for operating system use, a DSP,
1186 another ARM core embedded in an image processing engine,
1187 and other processing engines.
1189 @subsection Default Value Boiler Plate Code
1191 All target configuration files should start with code like this,
1192 letting board config files express environment-specific
1193 differences in how things should be set up.
1196 # Boards may override chip names, perhaps based on role,
1197 # but the default should match what the vendor uses
1198 if @{ [info exists CHIPNAME] @} @{
1199 set _CHIPNAME $CHIPNAME
1201 set _CHIPNAME sam7x256
1204 # ONLY use ENDIAN with targets that can change it.
1205 if @{ [info exists ENDIAN] @} @{
1211 # TAP identifiers may change as chips mature, for example with
1212 # new revision fields (the "3" here). Pick a good default; you
1213 # can pass several such identifiers to the "jtag newtap" command.
1214 if @{ [info exists CPUTAPID ] @} @{
1215 set _CPUTAPID $CPUTAPID
1217 set _CPUTAPID 0x3f0f0f0f
1220 @c but 0x3f0f0f0f is for an str73x part ...
1222 @emph{Remember:} Board config files may include multiple target
1223 config files, or the same target file multiple times
1224 (changing at least @code{CHIPNAME}).
1226 Likewise, the target configuration file should define
1227 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1228 use it later on when defining debug targets:
1231 set _TARGETNAME $_CHIPNAME.cpu
1232 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1235 @subsection Adding TAPs to the Scan Chain
1236 After the ``defaults'' are set up,
1237 add the TAPs on each chip to the JTAG scan chain.
1238 @xref{TAP Declaration}, and the naming convention
1241 In the simplest case the chip has only one TAP,
1242 probably for a CPU or FPGA.
1243 The config file for the Atmel AT91SAM7X256
1244 looks (in part) like this:
1247 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
1248 -expected-id $_CPUTAPID
1251 A board with two such at91sam7 chips would be able
1252 to source such a config file twice, with different
1253 values for @code{CHIPNAME}, so
1254 it adds a different TAP each time.
1256 If there are one or more nonzero @option{-expected-id} values,
1257 OpenOCD attempts to verify the actual tap id against those values.
1258 It will issue error messages if there is mismatch, which
1259 can help to pinpoint problems in OpenOCD configurations.
1262 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1263 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1264 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1265 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1266 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1269 There are more complex examples too, with chips that have
1270 multiple TAPs. Ones worth looking at include:
1273 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1274 plus a JRC to enable them
1275 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1276 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1277 is not currently used)
1280 @subsection Add CPU targets
1282 After adding a TAP for a CPU, you should set it up so that
1283 GDB and other commands can use it.
1284 @xref{CPU Configuration}.
1285 For the at91sam7 example above, the command can look like this;
1286 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1287 to little endian, and this chip doesn't support changing that.
1290 set _TARGETNAME $_CHIPNAME.cpu
1291 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1294 Work areas are small RAM areas associated with CPU targets.
1295 They are used by OpenOCD to speed up downloads,
1296 and to download small snippets of code to program flash chips.
1297 If the chip includes a form of ``on-chip-ram'' - and many do - define
1298 a work area if you can.
1299 Again using the at91sam7 as an example, this can look like:
1302 $_TARGETNAME configure -work-area-phys 0x00200000 \
1303 -work-area-size 0x4000 -work-area-backup 0
1306 @subsection Chip Reset Setup
1308 As a rule, you should put the @command{reset_config} command
1309 into the board file. Most things you think you know about a
1310 chip can be tweaked by the board.
1312 Some chips have specific ways the TRST and SRST signals are
1313 managed. In the unusual case that these are @emph{chip specific}
1314 and can never be changed by board wiring, they could go here.
1316 Some chips need special attention during reset handling if
1317 they're going to be used with JTAG.
1318 An example might be needing to send some commands right
1319 after the target's TAP has been reset, providing a
1320 @code{reset-deassert-post} event handler that writes a chip
1321 register to report that JTAG debugging is being done.
1323 JTAG clocking constraints often change during reset, and in
1324 some cases target config files (rather than board config files)
1325 are the right places to handle some of those issues.
1326 For example, immediately after reset most chips run using a
1327 slower clock than they will use later.
1328 That means that after reset (and potentially, as OpenOCD
1329 first starts up) they must use a slower JTAG clock rate
1330 than they will use later.
1333 @quotation Important
1334 When you are debugging code that runs right after chip
1335 reset, getting these issues right is critical.
1336 In particular, if you see intermittent failures when
1337 OpenOCD verifies the scan chain after reset,
1338 look at how you are setting up JTAG clocking.
1341 @subsection ARM Core Specific Hacks
1343 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1344 special high speed download features - enable it.
1346 If present, the MMU, the MPU and the CACHE should be disabled.
1348 Some ARM cores are equipped with trace support, which permits
1349 examination of the instruction and data bus activity. Trace
1350 activity is controlled through an ``Embedded Trace Module'' (ETM)
1351 on one of the core's scan chains. The ETM emits voluminous data
1352 through a ``trace port''. (@xref{ARM Hardware Tracing}.)
1353 If you are using an external trace port,
1354 configure it in your board config file.
1355 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1356 configure it in your target config file.
1359 etm config $_TARGETNAME 16 normal full etb
1360 etb config $_TARGETNAME $_CHIPNAME.etb
1363 @subsection Internal Flash Configuration
1365 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1367 @b{Never ever} in the ``target configuration file'' define any type of
1368 flash that is external to the chip. (For example a BOOT flash on
1369 Chip Select 0.) Such flash information goes in a board file - not
1370 the TARGET (chip) file.
1374 @item at91sam7x256 - has 256K flash YES enable it.
1375 @item str912 - has flash internal YES enable it.
1376 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1377 @item pxa270 - again - CS0 flash - it goes in the board file.
1380 @node Daemon Configuration
1381 @chapter Daemon Configuration
1382 @cindex initialization
1383 The commands here are commonly found in the openocd.cfg file and are
1384 used to specify what TCP/IP ports are used, and how GDB should be
1387 @anchor{Configuration Stage}
1388 @section Configuration Stage
1389 @cindex configuration stage
1390 @cindex config command
1392 When the OpenOCD server process starts up, it enters a
1393 @emph{configuration stage} which is the only time that
1394 certain commands, @emph{configuration commands}, may be issued.
1395 In this manual, the definition of a configuration command is
1396 presented as a @emph{Config Command}, not as a @emph{Command}
1397 which may be issued interactively.
1399 Those configuration commands include declaration of TAPs,
1401 the interface used for JTAG communication,
1402 and other basic setup.
1403 The server must leave the configuration stage before it
1404 may access or activate TAPs.
1405 After it leaves this stage, configuration commands may no
1408 The first thing OpenOCD does after leaving the configuration
1409 stage is to verify that it can talk to the scan chain
1410 (list of TAPs) which has been configured.
1411 It will warn if it doesn't find TAPs it expects to find,
1412 or finds TAPs that aren't supposed to be there.
1413 You should see no errors at this point.
1414 If you see errors, resolve them by correcting the
1415 commands you used to configure the server.
1416 Common errors include using an initial JTAG speed that's too
1417 fast, and not providing the right IDCODE values for the TAPs
1420 @deffn {Config Command} init
1421 This command terminates the configuration stage and
1422 enters the normal command mode. This can be useful to add commands to
1423 the startup scripts and commands such as resetting the target,
1424 programming flash, etc. To reset the CPU upon startup, add "init" and
1425 "reset" at the end of the config script or at the end of the OpenOCD
1426 command line using the @option{-c} command line switch.
1428 If this command does not appear in any startup/configuration file
1429 OpenOCD executes the command for you after processing all
1430 configuration files and/or command line options.
1432 @b{NOTE:} This command normally occurs at or near the end of your
1433 openocd.cfg file to force OpenOCD to ``initialize'' and make the
1434 targets ready. For example: If your openocd.cfg file needs to
1435 read/write memory on your target, @command{init} must occur before
1436 the memory read/write commands. This includes @command{nand probe}.
1439 @anchor{TCP/IP Ports}
1440 @section TCP/IP Ports
1445 The OpenOCD server accepts remote commands in several syntaxes.
1446 Each syntax uses a different TCP/IP port, which you may specify
1447 only during configuration (before those ports are opened).
1449 For reasons including security, you may wish to prevent remote
1450 access using one or more of these ports.
1451 In such cases, just specify the relevant port number as zero.
1452 If you disable all access through TCP/IP, you will need to
1453 use the command line @option{-pipe} option.
1455 @deffn {Command} gdb_port (number)
1457 Specify or query the first port used for incoming GDB connections.
1458 The GDB port for the
1459 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
1460 When not specified during the configuration stage,
1461 the port @var{number} defaults to 3333.
1462 When specified as zero, this port is not activated.
1465 @deffn {Command} tcl_port (number)
1466 Specify or query the port used for a simplified RPC
1467 connection that can be used by clients to issue TCL commands and get the
1468 output from the Tcl engine.
1469 Intended as a machine interface.
1470 When not specified during the configuration stage,
1471 the port @var{number} defaults to 6666.
1472 When specified as zero, this port is not activated.
1475 @deffn {Command} telnet_port (number)
1476 Specify or query the
1477 port on which to listen for incoming telnet connections.
1478 This port is intended for interaction with one human through TCL commands.
1479 When not specified during the configuration stage,
1480 the port @var{number} defaults to 4444.
1481 When specified as zero, this port is not activated.
1484 @anchor{GDB Configuration}
1485 @section GDB Configuration
1487 @cindex GDB configuration
1488 You can reconfigure some GDB behaviors if needed.
1489 The ones listed here are static and global.
1490 @xref{Target Configuration}, about configuring individual targets.
1491 @xref{Target Events}, about configuring target-specific event handling.
1493 @anchor{gdb_breakpoint_override}
1494 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
1495 Force breakpoint type for gdb @command{break} commands.
1496 This option supports GDB GUIs which don't
1497 distinguish hard versus soft breakpoints, if the default OpenOCD and
1498 GDB behaviour is not sufficient. GDB normally uses hardware
1499 breakpoints if the memory map has been set up for flash regions.
1502 @deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
1503 Configures what OpenOCD will do when GDB detaches from the daemon.
1504 Default behaviour is @option{resume}.
1507 @anchor{gdb_flash_program}
1508 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
1509 Set to @option{enable} to cause OpenOCD to program the flash memory when a
1510 vFlash packet is received.
1511 The default behaviour is @option{enable}.
1514 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
1515 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
1516 requested. GDB will then know when to set hardware breakpoints, and program flash
1517 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
1518 for flash programming to work.
1519 Default behaviour is @option{enable}.
1520 @xref{gdb_flash_program}.
1523 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
1524 Specifies whether data aborts cause an error to be reported
1525 by GDB memory read packets.
1526 The default behaviour is @option{disable};
1527 use @option{enable} see these errors reported.
1530 @anchor{Event Polling}
1531 @section Event Polling
1533 Hardware debuggers are parts of asynchronous systems,
1534 where significant events can happen at any time.
1535 The OpenOCD server needs to detect some of these events,
1536 so it can report them to through TCL command line
1539 Examples of such events include:
1542 @item One of the targets can stop running ... maybe it triggers
1543 a code breakpoint or data watchpoint, or halts itself.
1544 @item Messages may be sent over ``debug message'' channels ... many
1545 targets support such messages sent over JTAG,
1546 for receipt by the person debugging or tools.
1547 @item Loss of power ... some adapters can detect these events.
1548 @item Resets not issued through JTAG ... such reset sources
1549 can include button presses or other system hardware, sometimes
1550 including the target itself (perhaps through a watchdog).
1551 @item Debug instrumentation sometimes supports event triggering
1552 such as ``trace buffer full'' (so it can quickly be emptied)
1553 or other signals (to correlate with code behavior).
1556 None of those events are signaled through standard JTAG signals.
1557 However, most conventions for JTAG connectors include voltage
1558 level and system reset (SRST) signal detection.
1559 Some connectors also include instrumentation signals, which
1560 can imply events when those signals are inputs.
1562 In general, OpenOCD needs to periodically check for those events,
1563 either by looking at the status of signals on the JTAG connector
1564 or by sending synchronous ``tell me your status'' JTAG requests
1565 to the various active targets.
1566 There is a command to manage and monitor that polling,
1567 which is normally done in the background.
1569 @deffn Command poll [@option{on}|@option{off}]
1570 Poll the current target for its current state.
1571 (Also, @pxref{target curstate}.)
1572 If that target is in debug mode, architecture
1573 specific information about the current state is printed.
1574 An optional parameter
1575 allows background polling to be enabled and disabled.
1577 You could use this from the TCL command shell, or
1578 from GDB using @command{monitor poll} command.
1581 background polling: on
1582 target state: halted
1583 target halted in ARM state due to debug-request, \
1584 current mode: Supervisor
1585 cpsr: 0x800000d3 pc: 0x11081bfc
1586 MMU: disabled, D-Cache: disabled, I-Cache: enabled
1591 @node Interface - Dongle Configuration
1592 @chapter Interface - Dongle Configuration
1593 @cindex config file, interface
1594 @cindex interface config file
1596 JTAG Adapters/Interfaces/Dongles are normally configured
1597 through commands in an interface configuration
1598 file which is sourced by your @file{openocd.cfg} file, or
1599 through a command line @option{-f interface/....cfg} option.
1602 source [find interface/olimex-jtag-tiny.cfg]
1606 OpenOCD what type of JTAG adapter you have, and how to talk to it.
1607 A few cases are so simple that you only need to say what driver to use:
1614 Most adapters need a bit more configuration than that.
1617 @section Interface Configuration
1619 The interface command tells OpenOCD what type of JTAG dongle you are
1620 using. Depending on the type of dongle, you may need to have one or
1621 more additional commands.
1623 @deffn {Config Command} {interface} name
1624 Use the interface driver @var{name} to connect to the
1628 @deffn Command {interface_list}
1629 List the interface drivers that have been built into
1630 the running copy of OpenOCD.
1633 @deffn Command {jtag interface}
1634 Returns the name of the interface driver being used.
1637 @section Interface Drivers
1639 Each of the interface drivers listed here must be explicitly
1640 enabled when OpenOCD is configured, in order to be made
1641 available at run time.
1643 @deffn {Interface Driver} {amt_jtagaccel}
1644 Amontec Chameleon in its JTAG Accelerator configuration,
1645 connected to a PC's EPP mode parallel port.
1646 This defines some driver-specific commands:
1648 @deffn {Config Command} {parport_port} number
1649 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1650 the number of the @file{/dev/parport} device.
1653 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
1654 Displays status of RTCK option.
1655 Optionally sets that option first.
1659 @deffn {Interface Driver} {arm-jtag-ew}
1660 Olimex ARM-JTAG-EW USB adapter
1661 This has one driver-specific command:
1663 @deffn Command {armjtagew_info}
1668 @deffn {Interface Driver} {at91rm9200}
1669 Supports bitbanged JTAG from the local system,
1670 presuming that system is an Atmel AT91rm9200
1671 and a specific set of GPIOs is used.
1672 @c command: at91rm9200_device NAME
1673 @c chooses among list of bit configs ... only one option
1676 @deffn {Interface Driver} {dummy}
1677 A dummy software-only driver for debugging.
1680 @deffn {Interface Driver} {ep93xx}
1681 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1684 @deffn {Interface Driver} {ft2232}
1685 FTDI FT2232 (USB) based devices over one of the userspace libraries.
1686 These interfaces have several commands, used to configure the driver
1687 before initializing the JTAG scan chain:
1689 @deffn {Config Command} {ft2232_device_desc} description
1690 Provides the USB device description (the @emph{iProduct string})
1691 of the FTDI FT2232 device. If not
1692 specified, the FTDI default value is used. This setting is only valid
1693 if compiled with FTD2XX support.
1696 @deffn {Config Command} {ft2232_serial} serial-number
1697 Specifies the @var{serial-number} of the FTDI FT2232 device to use,
1698 in case the vendor provides unique IDs and more than one FT2232 device
1699 is connected to the host.
1700 If not specified, serial numbers are not considered.
1701 (Note that USB serial numbers can be arbitrary Unicode strings,
1702 and are not restricted to containing only decimal digits.)
1705 @deffn {Config Command} {ft2232_layout} name
1706 Each vendor's FT2232 device can use different GPIO signals
1707 to control output-enables, reset signals, and LEDs.
1708 Currently valid layout @var{name} values include:
1710 @item @b{axm0432_jtag} Axiom AXM-0432
1711 @item @b{comstick} Hitex STR9 comstick
1712 @item @b{cortino} Hitex Cortino JTAG interface
1713 @item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
1714 either for the local Cortex-M3 (SRST only)
1715 or in a passthrough mode (neither SRST nor TRST)
1716 @item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
1717 @item @b{flyswatter} Tin Can Tools Flyswatter
1718 @item @b{icebear} ICEbear JTAG adapter from Section 5
1719 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
1720 @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
1721 @item @b{m5960} American Microsystems M5960
1722 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
1723 @item @b{oocdlink} OOCDLink
1724 @c oocdlink ~= jtagkey_prototype_v1
1725 @item @b{sheevaplug} Marvell Sheevaplug development kit
1726 @item @b{signalyzer} Xverve Signalyzer
1727 @item @b{stm32stick} Hitex STM32 Performance Stick
1728 @item @b{turtelizer2} egnite Software turtelizer2
1729 @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
1733 @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
1734 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1735 default values are used.
1736 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
1738 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1742 @deffn {Config Command} {ft2232_latency} ms
1743 On some systems using FT2232 based JTAG interfaces the FT_Read function call in
1744 ft2232_read() fails to return the expected number of bytes. This can be caused by
1745 USB communication delays and has proved hard to reproduce and debug. Setting the
1746 FT2232 latency timer to a larger value increases delays for short USB packets but it
1747 also reduces the risk of timeouts before receiving the expected number of bytes.
1748 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1751 For example, the interface config file for a
1752 Turtelizer JTAG Adapter looks something like this:
1756 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
1757 ft2232_layout turtelizer2
1758 ft2232_vid_pid 0x0403 0xbdc8
1762 @deffn {Interface Driver} {gw16012}
1763 Gateworks GW16012 JTAG programmer.
1764 This has one driver-specific command:
1766 @deffn {Config Command} {parport_port} number
1767 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
1768 the number of the @file{/dev/parport} device.
1772 @deffn {Interface Driver} {jlink}
1773 Segger jlink USB adapter
1774 @c command: jlink_info
1776 @c command: jlink_hw_jtag (2|3)
1777 @c sets version 2 or 3
1780 @deffn {Interface Driver} {parport}
1781 Supports PC parallel port bit-banging cables:
1782 Wigglers, PLD download cable, and more.
1783 These interfaces have several commands, used to configure the driver
1784 before initializing the JTAG scan chain:
1786 @deffn {Config Command} {parport_cable} name
1787 The layout of the parallel port cable used to connect to the target.
1788 Currently valid cable @var{name} values include:
1791 @item @b{altium} Altium Universal JTAG cable.
1792 @item @b{arm-jtag} Same as original wiggler except SRST and
1793 TRST connections reversed and TRST is also inverted.
1794 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
1795 in configuration mode. This is only used to
1796 program the Chameleon itself, not a connected target.
1797 @item @b{dlc5} The Xilinx Parallel cable III.
1798 @item @b{flashlink} The ST Parallel cable.
1799 @item @b{lattice} Lattice ispDOWNLOAD Cable
1800 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
1802 Amontec's Chameleon Programmer. The new version available from
1803 the website uses the original Wiggler layout ('@var{wiggler}')
1804 @item @b{triton} The parallel port adapter found on the
1805 ``Karo Triton 1 Development Board''.
1806 This is also the layout used by the HollyGates design
1807 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1808 @item @b{wiggler} The original Wiggler layout, also supported by
1809 several clones, such as the Olimex ARM-JTAG
1810 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
1811 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
1815 @deffn {Config Command} {parport_port} number
1816 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1817 the @file{/dev/parport} device
1819 When using PPDEV to access the parallel port, use the number of the parallel port:
1820 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1821 you may encounter a problem.
1824 @deffn {Config Command} {parport_write_on_exit} (on|off)
1825 This will configure the parallel driver to write a known
1826 cable-specific value to the parallel interface on exiting OpenOCD
1829 For example, the interface configuration file for a
1830 classic ``Wiggler'' cable might look something like this:
1835 parport_cable wiggler
1839 @deffn {Interface Driver} {presto}
1840 ASIX PRESTO USB JTAG programmer.
1841 @c command: presto_serial str
1842 @c sets serial number
1845 @deffn {Interface Driver} {rlink}
1846 Raisonance RLink USB adapter
1849 @deffn {Interface Driver} {usbprog}
1850 usbprog is a freely programmable USB adapter.
1853 @deffn {Interface Driver} {vsllink}
1854 vsllink is part of Versaloon which is a versatile USB programmer.
1857 This defines quite a few driver-specific commands,
1858 which are not currently documented here.
1862 @deffn {Interface Driver} {ZY1000}
1863 This is the Zylin ZY1000 JTAG debugger.
1866 This defines some driver-specific commands,
1867 which are not currently documented here.
1870 @deffn Command power [@option{on}|@option{off}]
1871 Turn power switch to target on/off.
1872 No arguments: print status.
1879 JTAG clock setup is part of system setup.
1880 It @emph{does not belong with interface setup} since any interface
1881 only knows a few of the constraints for the JTAG clock speed.
1882 Sometimes the JTAG speed is
1883 changed during the target initialization process: (1) slow at
1884 reset, (2) program the CPU clocks, (3) run fast.
1885 Both the "slow" and "fast" clock rates are functions of the
1886 oscillators used, the chip, the board design, and sometimes
1887 power management software that may be active.
1889 The speed used during reset, and the scan chain verification which
1890 follows reset, can be adjusted using a @code{reset-start}
1891 target event handler.
1892 It can then be reconfigured to a faster speed by a
1893 @code{reset-init} target event handler after it reprograms those
1894 CPU clocks, or manually (if something else, such as a boot loader,
1895 sets up those clocks).
1896 @xref{Target Events}.
1897 When the initial low JTAG speed is a chip characteristic, perhaps
1898 because of a required oscillator speed, provide such a handler
1899 in the target config file.
1900 When that speed is a function of a board-specific characteristic
1901 such as which speed oscillator is used, it belongs in the board
1902 config file instead.
1903 In both cases it's safest to also set the initial JTAG clock rate
1904 to that same slow speed, so that OpenOCD never starts up using a
1905 clock speed that's faster than the scan chain can support.
1909 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
1912 If your system supports adaptive clocking (RTCK), configuring
1913 JTAG to use that is probably the most robust approach.
1914 However, it introduces delays to synchronize clocks; so it
1915 may not be the fastest solution.
1917 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
1918 instead of @command{jtag_khz}.
1920 @deffn {Command} jtag_khz max_speed_kHz
1921 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1922 JTAG interfaces usually support a limited number of
1923 speeds. The speed actually used won't be faster
1924 than the speed specified.
1926 Chip data sheets generally include a top JTAG clock rate.
1927 The actual rate is often a function of a CPU core clock,
1928 and is normally less than that peak rate.
1929 For example, most ARM cores accept at most one sixth of the CPU clock.
1931 Speed 0 (khz) selects RTCK method.
1933 If your system uses RTCK, you won't need to change the
1934 JTAG clocking after setup.
1935 Not all interfaces, boards, or targets support ``rtck''.
1936 If the interface device can not
1937 support it, an error is returned when you try to use RTCK.
1940 @defun jtag_rclk fallback_speed_kHz
1941 @cindex adaptive clocking
1943 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
1944 If that fails (maybe the interface, board, or target doesn't
1945 support it), falls back to the specified frequency.
1947 # Fall back to 3mhz if RTCK is not supported
1952 @node Reset Configuration
1953 @chapter Reset Configuration
1954 @cindex Reset Configuration
1956 Every system configuration may require a different reset
1957 configuration. This can also be quite confusing.
1958 Resets also interact with @var{reset-init} event handlers,
1959 which do things like setting up clocks and DRAM, and
1960 JTAG clock rates. (@xref{JTAG Speed}.)
1961 They can also interact with JTAG routers.
1962 Please see the various board files for examples.
1965 To maintainers and integrators:
1966 Reset configuration touches several things at once.
1967 Normally the board configuration file
1968 should define it and assume that the JTAG adapter supports
1969 everything that's wired up to the board's JTAG connector.
1971 However, the target configuration file could also make note
1972 of something the silicon vendor has done inside the chip,
1973 which will be true for most (or all) boards using that chip.
1974 And when the JTAG adapter doesn't support everything, the
1975 user configuration file will need to override parts of
1976 the reset configuration provided by other files.
1979 @section Types of Reset
1981 There are many kinds of reset possible through JTAG, but
1982 they may not all work with a given board and adapter.
1983 That's part of why reset configuration can be error prone.
1987 @emph{System Reset} ... the @emph{SRST} hardware signal
1988 resets all chips connected to the JTAG adapter, such as processors,
1989 power management chips, and I/O controllers. Normally resets triggered
1990 with this signal behave exactly like pressing a RESET button.
1992 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
1993 just the TAP controllers connected to the JTAG adapter.
1994 Such resets should not be visible to the rest of the system; resetting a
1995 device's the TAP controller just puts that controller into a known state.
1997 @emph{Emulation Reset} ... many devices can be reset through JTAG
1998 commands. These resets are often distinguishable from system
1999 resets, either explicitly (a "reset reason" register says so)
2000 or implicitly (not all parts of the chip get reset).
2002 @emph{Other Resets} ... system-on-chip devices often support
2003 several other types of reset.
2004 You may need to arrange that a watchdog timer stops
2005 while debugging, preventing a watchdog reset.
2006 There may be individual module resets.
2009 In the best case, OpenOCD can hold SRST, then reset
2010 the TAPs via TRST and send commands through JTAG to halt the
2011 CPU at the reset vector before the 1st instruction is executed.
2012 Then when it finally releases the SRST signal, the system is
2013 halted under debugger control before any code has executed.
2014 This is the behavior required to support the @command{reset halt}
2015 and @command{reset init} commands; after @command{reset init} a
2016 board-specific script might do things like setting up DRAM.
2017 (@xref{Reset Command}.)
2019 @anchor{SRST and TRST Issues}
2020 @section SRST and TRST Issues
2022 Because SRST and TRST are hardware signals, they can have a
2023 variety of system-specific constraints. Some of the most
2028 @item @emph{Signal not available} ... Some boards don't wire
2029 SRST or TRST to the JTAG connector. Some JTAG adapters don't
2030 support such signals even if they are wired up.
2031 Use the @command{reset_config} @var{signals} options to say
2032 when either of those signals is not connected.
2033 When SRST is not available, your code might not be able to rely
2034 on controllers having been fully reset during code startup.
2035 Missing TRST is not a problem, since JTAG level resets can
2036 be triggered using with TMS signaling.
2038 @item @emph{Signals shorted} ... Sometimes a chip, board, or
2039 adapter will connect SRST to TRST, instead of keeping them separate.
2040 Use the @command{reset_config} @var{combination} options to say
2041 when those signals aren't properly independent.
2043 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
2044 delay circuit, reset supervisor, or on-chip features can extend
2045 the effect of a JTAG adapter's reset for some time after the adapter
2046 stops issuing the reset. For example, there may be chip or board
2047 requirements that all reset pulses last for at least a
2048 certain amount of time; and reset buttons commonly have
2049 hardware debouncing.
2050 Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
2051 commands to say when extra delays are needed.
2053 @item @emph{Drive type} ... Reset lines often have a pullup
2054 resistor, letting the JTAG interface treat them as open-drain
2055 signals. But that's not a requirement, so the adapter may need
2056 to use push/pull output drivers.
2057 Also, with weak pullups it may be advisable to drive
2058 signals to both levels (push/pull) to minimize rise times.
2059 Use the @command{reset_config} @var{trst_type} and
2060 @var{srst_type} parameters to say how to drive reset signals.
2062 @item @emph{Special initialization} ... Targets sometimes need
2063 special JTAG initialization sequences to handle chip-specific
2064 issues (not limited to errata).
2065 For example, certain JTAG commands might need to be issued while
2066 the system as a whole is in a reset state (SRST active)
2067 but the JTAG scan chain is usable (TRST inactive).
2068 (@xref{JTAG Commands}, where the @command{jtag_reset}
2069 command is presented.)
2072 There can also be other issues.
2073 Some devices don't fully conform to the JTAG specifications.
2074 Trivial system-specific differences are common, such as
2075 SRST and TRST using slightly different names.
2076 There are also vendors who distribute key JTAG documentation for
2077 their chips only to developers who have signed a Non-Disclosure
2080 Sometimes there are chip-specific extensions like a requirement to use
2081 the normally-optional TRST signal (precluding use of JTAG adapters which
2082 don't pass TRST through), or needing extra steps to complete a TAP reset.
2084 In short, SRST and especially TRST handling may be very finicky,
2085 needing to cope with both architecture and board specific constraints.
2087 @section Commands for Handling Resets
2089 @deffn {Command} jtag_nsrst_delay milliseconds
2090 How long (in milliseconds) OpenOCD should wait after deasserting
2091 nSRST (active-low system reset) before starting new JTAG operations.
2092 When a board has a reset button connected to SRST line it will
2093 probably have hardware debouncing, implying you should use this.
2096 @deffn {Command} jtag_ntrst_delay milliseconds
2097 How long (in milliseconds) OpenOCD should wait after deasserting
2098 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
2101 @deffn {Command} reset_config mode_flag ...
2102 This command tells OpenOCD the reset configuration
2103 of your combination of JTAG board and target in target
2104 configuration scripts.
2106 Information earlier in this section describes the kind of problems
2107 the command is intended to address (@pxref{SRST and TRST Issues}).
2108 As a rule this command belongs only in board config files,
2109 describing issues like @emph{board doesn't connect TRST};
2110 or in user config files, addressing limitations derived
2111 from a particular combination of interface and board.
2112 (An unlikely example would be using a TRST-only adapter
2113 with a board that only wires up SRST.)
2115 The @var{mode_flag} options can be specified in any order, but only one
2116 of each type -- @var{signals}, @var{combination}, @var{trst_type},
2117 and @var{srst_type} -- may be specified at a time.
2118 If you don't provide a new value for a given type, its previous
2119 value (perhaps the default) is unchanged.
2120 For example, this means that you don't need to say anything at all about
2121 TRST just to declare that if the JTAG adapter should want to drive SRST,
2122 it must explicitly be driven high (@option{srst_push_pull}).
2124 @var{signals} can specify which of the reset signals are connected.
2125 For example, If the JTAG interface provides SRST, but the board doesn't
2126 connect that signal properly, then OpenOCD can't use it.
2127 Possible values are @option{none} (the default), @option{trst_only},
2128 @option{srst_only} and @option{trst_and_srst}.
2131 If your board provides SRST or TRST through the JTAG connector,
2132 you must declare that or else those signals will not be used.
2135 The @var{combination} is an optional value specifying broken reset
2136 signal implementations.
2137 The default behaviour if no option given is @option{separate},
2138 indicating everything behaves normally.
2139 @option{srst_pulls_trst} states that the
2140 test logic is reset together with the reset of the system (e.g. Philips
2141 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
2142 the system is reset together with the test logic (only hypothetical, I
2143 haven't seen hardware with such a bug, and can be worked around).
2144 @option{combined} implies both @option{srst_pulls_trst} and
2145 @option{trst_pulls_srst}.
2147 @option{srst_gates_jtag} indicates that asserting SRST gates the
2148 JTAG clock. This means that no communication can happen on JTAG
2149 while SRST is asserted.
2151 The optional @var{trst_type} and @var{srst_type} parameters allow the
2152 driver mode of each reset line to be specified. These values only affect
2153 JTAG interfaces with support for different driver modes, like the Amontec
2154 JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
2155 relevant signal (TRST or SRST) is not connected.
2157 Possible @var{trst_type} driver modes for the test reset signal (TRST)
2158 are @option{trst_push_pull} (default) and @option{trst_open_drain}.
2159 Most boards connect this signal to a pulldown, so the JTAG TAPs
2160 never leave reset unless they are hooked up to a JTAG adapter.
2162 Possible @var{srst_type} driver modes for the system reset signal (SRST)
2163 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
2164 Most boards connect this signal to a pullup, and allow the
2165 signal to be pulled low by various events including system
2166 powerup and pressing a reset button.
2170 @node TAP Declaration
2171 @chapter TAP Declaration
2172 @cindex TAP declaration
2173 @cindex TAP configuration
2175 @emph{Test Access Ports} (TAPs) are the core of JTAG.
2176 TAPs serve many roles, including:
2179 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
2180 @item @b{Flash Programing} Some chips program the flash directly via JTAG.
2181 Others do it indirectly, making a CPU do it.
2182 @item @b{Program Download} Using the same CPU support GDB uses,
2183 you can initialize a DRAM controller, download code to DRAM, and then
2184 start running that code.
2185 @item @b{Boundary Scan} Most chips support boundary scan, which
2186 helps test for board assembly problems like solder bridges
2187 and missing connections
2190 OpenOCD must know about the active TAPs on your board(s).
2191 Setting up the TAPs is the core task of your configuration files.
2192 Once those TAPs are set up, you can pass their names to code
2193 which sets up CPUs and exports them as GDB targets,
2194 probes flash memory, performs low-level JTAG operations, and more.
2196 @section Scan Chains
2199 TAPs are part of a hardware @dfn{scan chain},
2200 which is daisy chain of TAPs.
2201 They also need to be added to
2202 OpenOCD's software mirror of that hardware list,
2203 giving each member a name and associating other data with it.
2204 Simple scan chains, with a single TAP, are common in
2205 systems with a single microcontroller or microprocessor.
2206 More complex chips may have several TAPs internally.
2207 Very complex scan chains might have a dozen or more TAPs:
2208 several in one chip, more in the next, and connecting
2209 to other boards with their own chips and TAPs.
2211 You can display the list with the @command{scan_chain} command.
2212 (Don't confuse this with the list displayed by the @command{targets}
2213 command, presented in the next chapter.
2214 That only displays TAPs for CPUs which are configured as
2216 Here's what the scan chain might look like for a chip more than one TAP:
2219 TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
2220 -- ------------------ ------- ---------- ---------- ----- ----- ------ -----
2221 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
2222 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
2223 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
2226 Unfortunately those TAPs can't always be autoconfigured,
2227 because not all devices provide good support for that.
2228 JTAG doesn't require supporting IDCODE instructions, and
2229 chips with JTAG routers may not link TAPs into the chain
2230 until they are told to do so.
2232 The configuration mechanism currently supported by OpenOCD
2233 requires explicit configuration of all TAP devices using
2234 @command{jtag newtap} commands, as detailed later in this chapter.
2235 A command like this would declare one tap and name it @code{chip1.cpu}:
2238 jtag newtap chip1 cpu -irlen 7 -ircapture 0x01 -irmask 0x55
2241 Each target configuration file lists the TAPs provided
2243 Board configuration files combine all the targets on a board,
2245 Note that @emph{the order in which TAPs are declared is very important.}
2246 It must match the order in the JTAG scan chain, both inside
2247 a single chip and between them.
2248 @xref{FAQ TAP Order}.
2250 For example, the ST Microsystems STR912 chip has
2251 three separate TAPs@footnote{See the ST
2252 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
2253 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
2254 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
2255 To configure those taps, @file{target/str912.cfg}
2256 includes commands something like this:
2259 jtag newtap str912 flash ... params ...
2260 jtag newtap str912 cpu ... params ...
2261 jtag newtap str912 bs ... params ...
2264 Actual config files use a variable instead of literals like
2265 @option{str912}, to support more than one chip of each type.
2266 @xref{Config File Guidelines}.
2268 @deffn Command {jtag names}
2269 Returns the names of all current TAPs in the scan chain.
2270 Use @command{jtag cget} or @command{jtag tapisenabled}
2271 to examine attributes and state of each TAP.
2273 foreach t [jtag names] @{
2274 puts [format "TAP: %s\n" $t]
2279 @deffn Command {scan_chain}
2280 Displays the TAPs in the scan chain configuration,
2282 The set of TAPs listed by this command is fixed by
2283 exiting the OpenOCD configuration stage,
2284 but systems with a JTAG router can
2285 enable or disable TAPs dynamically.
2286 In addition to the enable/disable status, the contents of
2287 each TAP's instruction register can also change.
2290 @c FIXME! "jtag cget" should be able to return all TAP
2291 @c attributes, like "$target_name cget" does for targets.
2293 @c Probably want "jtag eventlist", and a "tap-reset" event
2294 @c (on entry to RESET state).
2299 When TAP objects are declared with @command{jtag newtap},
2300 a @dfn{dotted.name} is created for the TAP, combining the
2301 name of a module (usually a chip) and a label for the TAP.
2302 For example: @code{xilinx.tap}, @code{str912.flash},
2303 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
2304 Many other commands use that dotted.name to manipulate or
2305 refer to the TAP. For example, CPU configuration uses the
2306 name, as does declaration of NAND or NOR flash banks.
2308 The components of a dotted name should follow ``C'' symbol
2309 name rules: start with an alphabetic character, then numbers
2310 and underscores are OK; while others (including dots!) are not.
2313 In older code, JTAG TAPs were numbered from 0..N.
2314 This feature is still present.
2315 However its use is highly discouraged, and
2316 should not be relied on; it will be removed by mid-2010.
2317 Update all of your scripts to use TAP names rather than numbers,
2318 by paying attention to the runtime warnings they trigger.
2319 Using TAP numbers in target configuration scripts prevents
2320 reusing those scripts on boards with multiple targets.
2323 @section TAP Declaration Commands
2325 @c shouldn't this be(come) a {Config Command}?
2326 @anchor{jtag newtap}
2327 @deffn Command {jtag newtap} chipname tapname configparams...
2328 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
2329 and configured according to the various @var{configparams}.
2331 The @var{chipname} is a symbolic name for the chip.
2332 Conventionally target config files use @code{$_CHIPNAME},
2333 defaulting to the model name given by the chip vendor but
2336 @cindex TAP naming convention
2337 The @var{tapname} reflects the role of that TAP,
2338 and should follow this convention:
2341 @item @code{bs} -- For boundary scan if this is a seperate TAP;
2342 @item @code{cpu} -- The main CPU of the chip, alternatively
2343 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
2344 @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
2345 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
2346 @item @code{flash} -- If the chip has a flash TAP, like the str912;
2347 @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
2348 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
2349 @item @code{tap} -- Should be used only FPGA or CPLD like devices
2351 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
2352 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
2353 For example, the Freescale IMX31 has a SDMA (Smart DMA) with
2354 a JTAG TAP; that TAP should be named @code{sdma}.
2357 Every TAP requires at least the following @var{configparams}:
2360 @item @code{-irlen} @var{NUMBER}
2361 @*The length in bits of the
2362 instruction register, such as 4 or 5 bits.
2365 A TAP may also provide optional @var{configparams}:
2368 @item @code{-disable} (or @code{-enable})
2369 @*Use the @code{-disable} parameter to flag a TAP which is not
2370 linked in to the scan chain after a reset using either TRST
2371 or the JTAG state machine's @sc{reset} state.
2372 You may use @code{-enable} to highlight the default state
2373 (the TAP is linked in).
2374 @xref{Enabling and Disabling TAPs}.
2375 @item @code{-expected-id} @var{number}
2376 @*A non-zero value represents the expected 32-bit IDCODE
2377 found when the JTAG chain is examined.
2378 These codes are not required by all JTAG devices.
2379 @emph{Repeat the option} as many times as required if more than one
2380 ID code could appear (for example, multiple versions).
2381 @item @code{-ircapture} @var{NUMBER}
2382 @*The bit pattern loaded by the TAP into the JTAG shift register
2383 on entry to the @sc{ircapture} state, such as 0x01.
2384 JTAG requires the two LSBs of this value to be 01.
2385 By default, @code{-ircapture} and @code{-irmask} are set
2386 up to verify that two-bit value; but you may provide
2387 additional bits, if you know them.
2388 @item @code{-irmask} @var{NUMBER}
2389 @*A mask used with @code{-ircapture}
2390 to verify that instruction scans work correctly.
2391 Such scans are not used by OpenOCD except to verify that
2392 there seems to be no problems with JTAG scan chain operations.
2396 @section Other TAP commands
2398 @c @deffn Command {jtag arp_init-reset}
2399 @c ... more or less "toggle TRST ... and SRST too, what the heck"
2401 @deffn Command {jtag cget} dotted.name @option{-event} name
2402 @deffnx Command {jtag configure} dotted.name @option{-event} name string
2403 At this writing this TAP attribute
2404 mechanism is used only for event handling.
2405 (It is not a direct analogue of the @code{cget}/@code{configure}
2406 mechanism for debugger targets.)
2407 See the next section for information about the available events.
2409 The @code{configure} subcommand assigns an event handler,
2410 a TCL string which is evaluated when the event is triggered.
2411 The @code{cget} subcommand returns that handler.
2419 OpenOCD includes two event mechanisms.
2420 The one presented here applies to all JTAG TAPs.
2421 The other applies to debugger targets,
2422 which are associated with certain TAPs.
2424 The TAP events currently defined are:
2427 @item @b{post-reset}
2428 @* The TAP has just completed a JTAG reset.
2429 For the first such handler called, the tap is still
2430 in the JTAG @sc{reset} state.
2431 Because the scan chain has not yet been verified, handlers for these events
2432 @emph{should not issue commands which scan the JTAG IR or DR registers}
2433 of any particular target.
2434 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
2435 @item @b{tap-disable}
2436 @* The TAP needs to be disabled. This handler should
2437 implement @command{jtag tapdisable}
2438 by issuing the relevant JTAG commands.
2439 @item @b{tap-enable}
2440 @* The TAP needs to be enabled. This handler should
2441 implement @command{jtag tapenable}
2442 by issuing the relevant JTAG commands.
2445 If you need some action after each JTAG reset, which isn't actually
2446 specific to any TAP (since you can't yet trust the scan chain's
2447 contents to be accurate), you might:
2450 jtag configure CHIP.jrc -event post-reset @{
2452 ... non-scan jtag operations to be done after reset
2457 @anchor{Enabling and Disabling TAPs}
2458 @section Enabling and Disabling TAPs
2459 @cindex JTAG Route Controller
2462 In some systems, a @dfn{JTAG Route Controller} (JRC)
2463 is used to enable and/or disable specific JTAG TAPs.
2464 Many ARM based chips from Texas Instruments include
2465 an ``ICEpick'' module, which is a JRC.
2466 Such chips include DaVinci and OMAP3 processors.
2468 A given TAP may not be visible until the JRC has been
2469 told to link it into the scan chain; and if the JRC
2470 has been told to unlink that TAP, it will no longer
2472 Such routers address problems that JTAG ``bypass mode''
2476 @item The scan chain can only go as fast as its slowest TAP.
2477 @item Having many TAPs slows instruction scans, since all
2478 TAPs receive new instructions.
2479 @item TAPs in the scan chain must be powered up, which wastes
2480 power and prevents debugging some power management mechanisms.
2483 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
2484 as implied by the existence of JTAG routers.
2485 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
2486 does include a kind of JTAG router functionality.
2488 @c (a) currently the event handlers don't seem to be able to
2489 @c fail in a way that could lead to no-change-of-state.
2491 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
2492 shown below, and is implemented using TAP event handlers.
2493 So for example, when defining a TAP for a CPU connected to
2494 a JTAG router, you should define TAP event handlers using
2495 code that looks something like this:
2498 jtag configure CHIP.cpu -event tap-enable @{
2499 echo "Enabling CPU TAP"
2500 ... jtag operations using CHIP.jrc
2502 jtag configure CHIP.cpu -event tap-disable @{
2503 echo "Disabling CPU TAP"
2504 ... jtag operations using CHIP.jrc
2508 @deffn Command {jtag tapdisable} dotted.name
2509 If necessary, disables the tap
2510 by sending it a @option{tap-disable} event.
2511 Returns the string "1" if the tap
2512 specified by @var{dotted.name} is enabled,
2513 and "0" if it is disabled.
2516 @deffn Command {jtag tapenable} dotted.name
2517 If necessary, enables the tap
2518 by sending it a @option{tap-enable} event.
2519 Returns the string "1" if the tap
2520 specified by @var{dotted.name} is enabled,
2521 and "0" if it is disabled.
2524 @deffn Command {jtag tapisenabled} dotted.name
2525 Returns the string "1" if the tap
2526 specified by @var{dotted.name} is enabled,
2527 and "0" if it is disabled.
2530 Humans will find the @command{scan_chain} command more helpful
2531 for querying the state of the JTAG taps.
2535 @node CPU Configuration
2536 @chapter CPU Configuration
2539 This chapter discusses how to set up GDB debug targets for CPUs.
2540 You can also access these targets without GDB
2541 (@pxref{Architecture and Core Commands},
2542 and @ref{Target State handling}) and
2543 through various kinds of NAND and NOR flash commands.
2544 If you have multiple CPUs you can have multiple such targets.
2546 We'll start by looking at how to examine the targets you have,
2547 then look at how to add one more target and how to configure it.
2549 @section Target List
2550 @cindex target, current
2551 @cindex target, list
2553 All targets that have been set up are part of a list,
2554 where each member has a name.
2555 That name should normally be the same as the TAP name.
2556 You can display the list with the @command{targets}
2558 This display often has only one CPU; here's what it might
2559 look like with more than one:
2561 TargetName Type Endian TapName State
2562 -- ------------------ ---------- ------ ------------------ ------------
2563 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
2564 1 MyTarget cortex_m3 little mychip.foo tap-disabled
2567 One member of that list is the @dfn{current target}, which
2568 is implicitly referenced by many commands.
2569 It's the one marked with a @code{*} near the target name.
2570 In particular, memory addresses often refer to the address
2571 space seen by that current target.
2572 Commands like @command{mdw} (memory display words)
2573 and @command{flash erase_address} (erase NOR flash blocks)
2574 are examples; and there are many more.
2576 Several commands let you examine the list of targets:
2578 @deffn Command {target count}
2579 @emph{Note: target numbers are deprecated; don't use them.
2580 They will be removed shortly after August 2010, including this command.
2581 Iterate target using @command{target names}, not by counting.}
2583 Returns the number of targets, @math{N}.
2584 The highest numbered target is @math{N - 1}.
2586 set c [target count]
2587 for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
2588 # Assuming you have created this function
2589 print_target_details $x
2594 @deffn Command {target current}
2595 Returns the name of the current target.
2598 @deffn Command {target names}
2599 Lists the names of all current targets in the list.
2601 foreach t [target names] @{
2602 puts [format "Target: %s\n" $t]
2607 @deffn Command {target number} number
2608 @emph{Note: target numbers are deprecated; don't use them.
2609 They will be removed shortly after August 2010, including this command.}
2611 The list of targets is numbered starting at zero.
2612 This command returns the name of the target at index @var{number}.
2614 set thename [target number $x]
2615 puts [format "Target %d is: %s\n" $x $thename]
2619 @c yep, "target list" would have been better.
2620 @c plus maybe "target setdefault".
2622 @deffn Command targets [name]
2623 @emph{Note: the name of this command is plural. Other target
2624 command names are singular.}
2626 With no parameter, this command displays a table of all known
2627 targets in a user friendly form.
2629 With a parameter, this command sets the current target to
2630 the given target with the given @var{name}; this is
2631 only relevant on boards which have more than one target.
2634 @section Target CPU Types and Variants
2639 Each target has a @dfn{CPU type}, as shown in the output of
2640 the @command{targets} command. You need to specify that type
2641 when calling @command{target create}.
2642 The CPU type indicates more than just the instruction set.
2643 It also indicates how that instruction set is implemented,
2644 what kind of debug support it integrates,
2645 whether it has an MMU (and if so, what kind),
2646 what core-specific commands may be available
2647 (@pxref{Architecture and Core Commands}),
2650 For some CPU types, OpenOCD also defines @dfn{variants} which
2651 indicate differences that affect their handling.
2652 For example, a particular implementation bug might need to be
2653 worked around in some chip versions.
2655 It's easy to see what target types are supported,
2656 since there's a command to list them.
2657 However, there is currently no way to list what target variants
2658 are supported (other than by reading the OpenOCD source code).
2660 @anchor{target types}
2661 @deffn Command {target types}
2662 Lists all supported target types.
2663 At this writing, the supported CPU types and variants are:
2666 @item @code{arm11} -- this is a generation of ARMv6 cores
2667 @item @code{arm720t} -- this is an ARMv4 core
2668 @item @code{arm7tdmi} -- this is an ARMv4 core
2669 @item @code{arm920t} -- this is an ARMv5 core
2670 @item @code{arm926ejs} -- this is an ARMv5 core
2671 @item @code{arm966e} -- this is an ARMv5 core
2672 @item @code{arm9tdmi} -- this is an ARMv4 core
2673 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
2674 (Support for this is preliminary and incomplete.)
2675 @item @code{cortex_a8} -- this is an ARMv7 core
2676 @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
2677 compact Thumb2 instruction set. It supports one variant:
2679 @item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
2680 This will cause OpenOCD to use a software reset rather than asserting
2681 SRST, to avoid a issue with clearing the debug registers.
2682 This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
2683 be detected and the normal reset behaviour used.
2685 @item @code{fa526} -- resembles arm920 (w/o Thumb)
2686 @item @code{feroceon} -- resembles arm926
2687 @item @code{mips_m4k} -- a MIPS core. This supports one variant:
2689 @item @code{ejtag_srst} ... Use this when debugging targets that do not
2690 provide a functional SRST line on the EJTAG connector. This causes
2691 OpenOCD to instead use an EJTAG software reset command to reset the
2693 You still need to enable @option{srst} on the @command{reset_config}
2694 command to enable OpenOCD hardware reset functionality.
2696 @item @code{xscale} -- this is actually an architecture,
2697 not a CPU type. It is based on the ARMv5 architecture.
2698 There are several variants defined:
2700 @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
2701 @code{pxa27x} ... instruction register length is 7 bits
2702 @item @code{pxa250}, @code{pxa255},
2703 @code{pxa26x} ... instruction register length is 5 bits
2708 To avoid being confused by the variety of ARM based cores, remember
2709 this key point: @emph{ARM is a technology licencing company}.
2710 (See: @url{http://www.arm.com}.)
2711 The CPU name used by OpenOCD will reflect the CPU design that was
2712 licenced, not a vendor brand which incorporates that design.
2713 Name prefixes like arm7, arm9, arm11, and cortex
2714 reflect design generations;
2715 while names like ARMv4, ARMv5, ARMv6, and ARMv7
2716 reflect an architecture version implemented by a CPU design.
2718 @anchor{Target Configuration}
2719 @section Target Configuration
2721 Before creating a ``target'', you must have added its TAP to the scan chain.
2722 When you've added that TAP, you will have a @code{dotted.name}
2723 which is used to set up the CPU support.
2724 The chip-specific configuration file will normally configure its CPU(s)
2725 right after it adds all of the chip's TAPs to the scan chain.
2727 Although you can set up a target in one step, it's often clearer if you
2728 use shorter commands and do it in two steps: create it, then configure
2730 All operations on the target after it's created will use a new
2731 command, created as part of target creation.
2733 The two main things to configure after target creation are
2734 a work area, which usually has target-specific defaults even
2735 if the board setup code overrides them later;
2736 and event handlers (@pxref{Target Events}), which tend
2737 to be much more board-specific.
2738 The key steps you use might look something like this
2741 target create MyTarget cortex_m3 -chain-position mychip.cpu
2742 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
2743 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
2744 $MyTarget configure -event reset-init @{ myboard_reinit @}
2747 You should specify a working area if you can; typically it uses some
2749 Such a working area can speed up many things, including bulk
2750 writes to target memory;
2751 flash operations like checking to see if memory needs to be erased;
2752 GDB memory checksumming;
2756 On more complex chips, the work area can become
2757 inaccessible when application code
2758 (such as an operating system)
2759 enables or disables the MMU.
2760 For example, the particular MMU context used to acess the virtual
2761 address will probably matter ... and that context might not have
2762 easy access to other addresses needed.
2763 At this writing, OpenOCD doesn't have much MMU intelligence.
2766 It's often very useful to define a @code{reset-init} event handler.
2767 For systems that are normally used with a boot loader,
2768 common tasks include updating clocks and initializing memory
2770 That may be needed to let you write the boot loader into flash,
2771 in order to ``de-brick'' your board; or to load programs into
2772 external DDR memory without having run the boot loader.
2774 @deffn Command {target create} target_name type configparams...
2775 This command creates a GDB debug target that refers to a specific JTAG tap.
2776 It enters that target into a list, and creates a new
2777 command (@command{@var{target_name}}) which is used for various
2778 purposes including additional configuration.
2781 @item @var{target_name} ... is the name of the debug target.
2782 By convention this should be the same as the @emph{dotted.name}
2783 of the TAP associated with this target, which must be specified here
2784 using the @code{-chain-position @var{dotted.name}} configparam.
2786 This name is also used to create the target object command,
2787 referred to here as @command{$target_name},
2788 and in other places the target needs to be identified.
2789 @item @var{type} ... specifies the target type. @xref{target types}.
2790 @item @var{configparams} ... all parameters accepted by
2791 @command{$target_name configure} are permitted.
2792 If the target is big-endian, set it here with @code{-endian big}.
2793 If the variant matters, set it here with @code{-variant}.
2795 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
2799 @deffn Command {$target_name configure} configparams...
2800 The options accepted by this command may also be
2801 specified as parameters to @command{target create}.
2802 Their values can later be queried one at a time by
2803 using the @command{$target_name cget} command.
2805 @emph{Warning:} changing some of these after setup is dangerous.
2806 For example, moving a target from one TAP to another;
2807 and changing its endianness or variant.
2811 @item @code{-chain-position} @var{dotted.name} -- names the TAP
2812 used to access this target.
2814 @item @code{-endian} (@option{big}|@option{little}) -- specifies
2815 whether the CPU uses big or little endian conventions
2817 @item @code{-event} @var{event_name} @var{event_body} --
2818 @xref{Target Events}.
2819 Note that this updates a list of named event handlers.
2820 Calling this twice with two different event names assigns
2821 two different handlers, but calling it twice with the
2822 same event name assigns only one handler.
2824 @item @code{-variant} @var{name} -- specifies a variant of the target,
2825 which OpenOCD needs to know about.
2827 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
2828 whether the work area gets backed up; by default,
2829 @emph{it is not backed up.}
2830 When possible, use a working_area that doesn't need to be backed up,
2831 since performing a backup slows down operations.
2832 For example, the beginning of an SRAM block is likely to
2833 be used by most build systems, but the end is often unused.
2835 @item @code{-work-area-size} @var{size} -- specify/set the work area
2837 @item @code{-work-area-phys} @var{address} -- set the work area
2838 base @var{address} to be used when no MMU is active.
2840 @item @code{-work-area-virt} @var{address} -- set the work area
2841 base @var{address} to be used when an MMU is active.
2846 @section Other $target_name Commands
2847 @cindex object command
2849 The Tcl/Tk language has the concept of object commands,
2850 and OpenOCD adopts that same model for targets.
2852 A good Tk example is a on screen button.
2853 Once a button is created a button
2854 has a name (a path in Tk terms) and that name is useable as a first
2855 class command. For example in Tk, one can create a button and later
2856 configure it like this:
2860 button .foobar -background red -command @{ foo @}
2862 .foobar configure -foreground blue
2864 set x [.foobar cget -background]
2866 puts [format "The button is %s" $x]
2869 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
2870 button, and its object commands are invoked the same way.
2873 str912.cpu mww 0x1234 0x42
2874 omap3530.cpu mww 0x5555 123
2877 The commands supported by OpenOCD target objects are:
2879 @deffn Command {$target_name arp_examine}
2880 @deffnx Command {$target_name arp_halt}
2881 @deffnx Command {$target_name arp_poll}
2882 @deffnx Command {$target_name arp_reset}
2883 @deffnx Command {$target_name arp_waitstate}
2884 Internal OpenOCD scripts (most notably @file{startup.tcl})
2885 use these to deal with specific reset cases.
2886 They are not otherwise documented here.
2889 @deffn Command {$target_name array2mem} arrayname width address count
2890 @deffnx Command {$target_name mem2array} arrayname width address count
2891 These provide an efficient script-oriented interface to memory.
2892 The @code{array2mem} primitive writes bytes, halfwords, or words;
2893 while @code{mem2array} reads them.
2894 In both cases, the TCL side uses an array, and
2895 the target side uses raw memory.
2897 The efficiency comes from enabling the use of
2898 bulk JTAG data transfer operations.
2899 The script orientation comes from working with data
2900 values that are packaged for use by TCL scripts;
2901 @command{mdw} type primitives only print data they retrieve,
2902 and neither store nor return those values.
2905 @item @var{arrayname} ... is the name of an array variable
2906 @item @var{width} ... is 8/16/32 - indicating the memory access size
2907 @item @var{address} ... is the target memory address
2908 @item @var{count} ... is the number of elements to process
2912 @deffn Command {$target_name cget} queryparm
2913 Each configuration parameter accepted by
2914 @command{$target_name configure}
2915 can be individually queried, to return its current value.
2916 The @var{queryparm} is a parameter name
2917 accepted by that command, such as @code{-work-area-phys}.
2918 There are a few special cases:
2921 @item @code{-event} @var{event_name} -- returns the handler for the
2922 event named @var{event_name}.
2923 This is a special case because setting a handler requires
2925 @item @code{-type} -- returns the target type.
2926 This is a special case because this is set using
2927 @command{target create} and can't be changed
2928 using @command{$target_name configure}.
2931 For example, if you wanted to summarize information about
2932 all the targets you might use something like this:
2935 foreach name [target names] @{
2936 set y [$name cget -endian]
2937 set z [$name cget -type]
2938 puts [format "Chip %d is %s, Endian: %s, type: %s" \
2944 @anchor{target curstate}
2945 @deffn Command {$target_name curstate}
2946 Displays the current target state:
2947 @code{debug-running},
2950 @code{running}, or @code{unknown}.
2951 (Also, @pxref{Event Polling}.)
2954 @deffn Command {$target_name eventlist}
2955 Displays a table listing all event handlers
2956 currently associated with this target.
2957 @xref{Target Events}.
2960 @deffn Command {$target_name invoke-event} event_name
2961 Invokes the handler for the event named @var{event_name}.
2962 (This is primarily intended for use by OpenOCD framework
2963 code, for example by the reset code in @file{startup.tcl}.)
2966 @deffn Command {$target_name mdw} addr [count]
2967 @deffnx Command {$target_name mdh} addr [count]
2968 @deffnx Command {$target_name mdb} addr [count]
2969 Display contents of address @var{addr}, as
2970 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
2971 or 8-bit bytes (@command{mdb}).
2972 If @var{count} is specified, displays that many units.
2973 (If you want to manipulate the data instead of displaying it,
2974 see the @code{mem2array} primitives.)
2977 @deffn Command {$target_name mww} addr word
2978 @deffnx Command {$target_name mwh} addr halfword
2979 @deffnx Command {$target_name mwb} addr byte
2980 Writes the specified @var{word} (32 bits),
2981 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
2982 at the specified address @var{addr}.
2985 @anchor{Target Events}
2986 @section Target Events
2987 @cindex target events
2989 At various times, certain things can happen, or you want them to happen.
2992 @item What should happen when GDB connects? Should your target reset?
2993 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
2994 @item During reset, do you need to write to certain memory locations
2995 to set up system clocks or
2996 to reconfigure the SDRAM?
2999 All of the above items can be addressed by target event handlers.
3000 These are set up by @command{$target_name configure -event} or
3001 @command{target create ... -event}.
3003 The programmer's model matches the @code{-command} option used in Tcl/Tk
3004 buttons and events. The two examples below act the same, but one creates
3005 and invokes a small procedure while the other inlines it.
3008 proc my_attach_proc @{ @} @{
3012 mychip.cpu configure -event gdb-attach my_attach_proc
3013 mychip.cpu configure -event gdb-attach @{
3019 The following target events are defined:
3022 @item @b{debug-halted}
3023 @* The target has halted for debug reasons (i.e.: breakpoint)
3024 @item @b{debug-resumed}
3025 @* The target has resumed (i.e.: gdb said run)
3026 @item @b{early-halted}
3027 @* Occurs early in the halt process
3029 @item @b{examine-end}
3030 @* Currently not used (goal: when JTAG examine completes)
3031 @item @b{examine-start}
3032 @* Currently not used (goal: when JTAG examine starts)
3034 @item @b{gdb-attach}
3035 @* When GDB connects
3036 @item @b{gdb-detach}
3037 @* When GDB disconnects
3039 @* When the target has halted and GDB is not doing anything (see early halt)
3040 @item @b{gdb-flash-erase-start}
3041 @* Before the GDB flash process tries to erase the flash
3042 @item @b{gdb-flash-erase-end}
3043 @* After the GDB flash process has finished erasing the flash
3044 @item @b{gdb-flash-write-start}
3045 @* Before GDB writes to the flash
3046 @item @b{gdb-flash-write-end}
3047 @* After GDB writes to the flash
3049 @* Before the target steps, gdb is trying to start/resume the target
3051 @* The target has halted
3053 @item @b{old-gdb_program_config}
3054 @* DO NOT USE THIS: Used internally
3055 @item @b{old-pre_resume}
3056 @* DO NOT USE THIS: Used internally
3058 @item @b{reset-assert-pre}
3059 @* Issued as part of @command{reset} processing
3060 after SRST and/or TRST were activated and deactivated,
3061 but before SRST alone is re-asserted on the tap.
3062 @item @b{reset-assert-post}
3063 @* Issued as part of @command{reset} processing
3064 when SRST is asserted on the tap.
3065 @item @b{reset-deassert-pre}
3066 @* Issued as part of @command{reset} processing
3067 when SRST is about to be released on the tap.
3068 @item @b{reset-deassert-post}
3069 @* Issued as part of @command{reset} processing
3070 when SRST has been released on the tap.
3072 @* Issued as the final step in @command{reset} processing.
3074 @item @b{reset-halt-post}
3075 @* Currently not used
3076 @item @b{reset-halt-pre}
3077 @* Currently not used
3079 @item @b{reset-init}
3080 @* Used by @b{reset init} command for board-specific initialization.
3081 This event fires after @emph{reset-deassert-post}.
3083 This is where you would configure PLLs and clocking, set up DRAM so
3084 you can download programs that don't fit in on-chip SRAM, set up pin
3085 multiplexing, and so on.
3086 (You may be able to switch to a fast JTAG clock rate here, after
3087 the target clocks are fully set up.)
3088 @item @b{reset-start}
3089 @* Issued as part of @command{reset} processing
3090 before either SRST or TRST are activated.
3092 This is the most robust place to switch to a low JTAG clock rate, if
3093 SRST disables PLLs needed to use a fast clock.
3095 @item @b{reset-wait-pos}
3096 @* Currently not used
3097 @item @b{reset-wait-pre}
3098 @* Currently not used
3100 @item @b{resume-start}
3101 @* Before any target is resumed
3102 @item @b{resume-end}
3103 @* After all targets have resumed
3107 @* Target has resumed
3111 @node Flash Commands
3112 @chapter Flash Commands
3114 OpenOCD has different commands for NOR and NAND flash;
3115 the ``flash'' command works with NOR flash, while
3116 the ``nand'' command works with NAND flash.
3117 This partially reflects different hardware technologies:
3118 NOR flash usually supports direct CPU instruction and data bus access,
3119 while data from a NAND flash must be copied to memory before it can be
3120 used. (SPI flash must also be copied to memory before use.)
3121 However, the documentation also uses ``flash'' as a generic term;
3122 for example, ``Put flash configuration in board-specific files''.
3126 @item Configure via the command @command{flash bank}
3127 @* Do this in a board-specific configuration file,
3128 passing parameters as needed by the driver.
3129 @item Operate on the flash via @command{flash subcommand}
3130 @* Often commands to manipulate the flash are typed by a human, or run
3131 via a script in some automated way. Common tasks include writing a
3132 boot loader, operating system, or other data.
3134 @* Flashing via GDB requires the flash be configured via ``flash
3135 bank'', and the GDB flash features be enabled.
3136 @xref{GDB Configuration}.
3139 Many CPUs have the ablity to ``boot'' from the first flash bank.
3140 This means that misprogramming that bank can ``brick'' a system,
3141 so that it can't boot.
3142 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
3143 board by (re)installing working boot firmware.
3145 @anchor{NOR Configuration}
3146 @section Flash Configuration Commands
3147 @cindex flash configuration
3149 @deffn {Config Command} {flash bank} driver base size chip_width bus_width target [driver_options]
3150 Configures a flash bank which provides persistent storage
3151 for addresses from @math{base} to @math{base + size - 1}.
3152 These banks will often be visible to GDB through the target's memory map.
3153 In some cases, configuring a flash bank will activate extra commands;
3154 see the driver-specific documentation.
3157 @item @var{driver} ... identifies the controller driver
3158 associated with the flash bank being declared.
3159 This is usually @code{cfi} for external flash, or else
3160 the name of a microcontroller with embedded flash memory.
3161 @xref{Flash Driver List}.
3162 @item @var{base} ... Base address of the flash chip.
3163 @item @var{size} ... Size of the chip, in bytes.
3164 For some drivers, this value is detected from the hardware.
3165 @item @var{chip_width} ... Width of the flash chip, in bytes;
3166 ignored for most microcontroller drivers.
3167 @item @var{bus_width} ... Width of the data bus used to access the
3168 chip, in bytes; ignored for most microcontroller drivers.
3169 @item @var{target} ... Names the target used to issue
3170 commands to the flash controller.
3171 @comment Actually, it's currently a controller-specific parameter...
3172 @item @var{driver_options} ... drivers may support, or require,
3173 additional parameters. See the driver-specific documentation
3174 for more information.
3177 This command is not available after OpenOCD initialization has completed.
3178 Use it in board specific configuration files, not interactively.
3182 @comment the REAL name for this command is "ocd_flash_banks"
3183 @comment less confusing would be: "flash list" (like "nand list")
3184 @deffn Command {flash banks}
3185 Prints a one-line summary of each device declared
3186 using @command{flash bank}, numbered from zero.
3187 Note that this is the @emph{plural} form;
3188 the @emph{singular} form is a very different command.
3191 @deffn Command {flash probe} num
3192 Identify the flash, or validate the parameters of the configured flash. Operation
3193 depends on the flash type.
3194 The @var{num} parameter is a value shown by @command{flash banks}.
3195 Most flash commands will implicitly @emph{autoprobe} the bank;
3196 flash drivers can distinguish between probing and autoprobing,
3197 but most don't bother.
3200 @section Erasing, Reading, Writing to Flash
3201 @cindex flash erasing
3202 @cindex flash reading
3203 @cindex flash writing
3204 @cindex flash programming
3206 One feature distinguishing NOR flash from NAND or serial flash technologies
3207 is that for read access, it acts exactly like any other addressible memory.
3208 This means you can use normal memory read commands like @command{mdw} or
3209 @command{dump_image} with it, with no special @command{flash} subcommands.
3210 @xref{Memory access}, and @ref{Image access}.
3212 Write access works differently. Flash memory normally needs to be erased
3213 before it's written. Erasing a sector turns all of its bits to ones, and
3214 writing can turn ones into zeroes. This is why there are special commands
3215 for interactive erasing and writing, and why GDB needs to know which parts
3216 of the address space hold NOR flash memory.
3219 Most of these erase and write commands leverage the fact that NOR flash
3220 chips consume target address space. They implicitly refer to the current
3221 JTAG target, and map from an address in that target's address space
3222 back to a flash bank.
3223 @comment In May 2009, those mappings may fail if any bank associated
3224 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
3225 A few commands use abstract addressing based on bank and sector numbers,
3226 and don't depend on searching the current target and its address space.
3227 Avoid confusing the two command models.
3230 Some flash chips implement software protection against accidental writes,
3231 since such buggy writes could in some cases ``brick'' a system.
3232 For such systems, erasing and writing may require sector protection to be
3234 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
3235 and AT91SAM7 on-chip flash.
3236 @xref{flash protect}.
3238 @anchor{flash erase_sector}
3239 @deffn Command {flash erase_sector} num first last
3240 Erase sectors in bank @var{num}, starting at sector @var{first}
3241 up to and including @var{last}.
3242 Sector numbering starts at 0.
3243 Providing a @var{last} sector of @option{last}
3244 specifies "to the end of the flash bank".
3245 The @var{num} parameter is a value shown by @command{flash banks}.
3248 @deffn Command {flash erase_address} address length
3249 Erase sectors starting at @var{address} for @var{length} bytes.
3250 The flash bank to use is inferred from the @var{address}, and
3251 the specified length must stay within that bank.
3252 As a special case, when @var{length} is zero and @var{address} is
3253 the start of the bank, the whole flash is erased.
3256 @deffn Command {flash fillw} address word length
3257 @deffnx Command {flash fillh} address halfword length
3258 @deffnx Command {flash fillb} address byte length
3259 Fills flash memory with the specified @var{word} (32 bits),
3260 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
3261 starting at @var{address} and continuing
3262 for @var{length} units (word/halfword/byte).
3263 No erasure is done before writing; when needed, that must be done
3264 before issuing this command.
3265 Writes are done in blocks of up to 1024 bytes, and each write is
3266 verified by reading back the data and comparing it to what was written.
3267 The flash bank to use is inferred from the @var{address} of
3268 each block, and the specified length must stay within that bank.
3270 @comment no current checks for errors if fill blocks touch multiple banks!
3272 @anchor{flash write_bank}
3273 @deffn Command {flash write_bank} num filename offset
3274 Write the binary @file{filename} to flash bank @var{num},
3275 starting at @var{offset} bytes from the beginning of the bank.
3276 The @var{num} parameter is a value shown by @command{flash banks}.
3279 @anchor{flash write_image}
3280 @deffn Command {flash write_image} [erase] filename [offset] [type]
3281 Write the image @file{filename} to the current target's flash bank(s).
3282 A relocation @var{offset} may be specified, in which case it is added
3283 to the base address for each section in the image.
3284 The file [@var{type}] can be specified
3285 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
3286 @option{elf} (ELF file), @option{s19} (Motorola s19).
3287 @option{mem}, or @option{builder}.
3288 The relevant flash sectors will be erased prior to programming
3289 if the @option{erase} parameter is given.
3290 The flash bank to use is inferred from the @var{address} of
3294 @section Other Flash commands
3295 @cindex flash protection
3297 @deffn Command {flash erase_check} num
3298 Check erase state of sectors in flash bank @var{num},
3299 and display that status.
3300 The @var{num} parameter is a value shown by @command{flash banks}.
3301 This is the only operation that
3302 updates the erase state information displayed by @option{flash info}. That means you have
3303 to issue a @command{flash erase_check} command after erasing or programming the device
3304 to get updated information.
3305 (Code execution may have invalidated any state records kept by OpenOCD.)
3308 @deffn Command {flash info} num
3309 Print info about flash bank @var{num}
3310 The @var{num} parameter is a value shown by @command{flash banks}.
3311 The information includes per-sector protect status.
3314 @anchor{flash protect}
3315 @deffn Command {flash protect} num first last (@option{on}|@option{off})
3316 Enable (@option{on}) or disable (@option{off}) protection of flash sectors
3317 in flash bank @var{num}, starting at sector @var{first}
3318 and continuing up to and including @var{last}.
3319 Providing a @var{last} sector of @option{last}
3320 specifies "to the end of the flash bank".
3321 The @var{num} parameter is a value shown by @command{flash banks}.
3324 @deffn Command {flash protect_check} num
3325 Check protection state of sectors in flash bank @var{num}.
3326 The @var{num} parameter is a value shown by @command{flash banks}.
3327 @comment @option{flash erase_sector} using the same syntax.
3330 @anchor{Flash Driver List}
3331 @section Flash Drivers, Options, and Commands
3332 As noted above, the @command{flash bank} command requires a driver name,
3333 and allows driver-specific options and behaviors.
3334 Some drivers also activate driver-specific commands.
3336 @subsection External Flash
3338 @deffn {Flash Driver} cfi
3339 @cindex Common Flash Interface
3341 The ``Common Flash Interface'' (CFI) is the main standard for
3342 external NOR flash chips, each of which connects to a
3343 specific external chip select on the CPU.
3344 Frequently the first such chip is used to boot the system.
3345 Your board's @code{reset-init} handler might need to
3346 configure additional chip selects using other commands (like: @command{mww} to
3347 configure a bus and its timings) , or
3348 perhaps configure a GPIO pin that controls the ``write protect'' pin
3350 The CFI driver can use a target-specific working area to significantly
3353 The CFI driver can accept the following optional parameters, in any order:
3356 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
3357 like AM29LV010 and similar types.
3358 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
3361 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
3362 wide on a sixteen bit bus:
3365 flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
3366 flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
3368 @c "cfi part_id" disabled
3371 @subsection Internal Flash (Microcontrollers)
3373 @deffn {Flash Driver} aduc702x
3374 The ADUC702x analog microcontrollers from Analog Devices
3375 include internal flash and use ARM7TDMI cores.
3376 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
3377 The setup command only requires the @var{target} argument
3378 since all devices in this family have the same memory layout.
3381 flash bank aduc702x 0 0 0 0 $_TARGETNAME
3385 @deffn {Flash Driver} at91sam3
3387 All members of the AT91SAM3 microcontroller family from
3388 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
3389 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
3390 that the driver was orginaly developed and tested using the
3391 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
3392 the family was cribbed from the data sheet. @emph{Note to future
3393 readers/updaters: Please remove this worrysome comment after other
3394 chips are confirmed.}
3396 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
3397 have one flash bank. In all cases the flash banks are at
3398 the following fixed locations:
3401 # Flash bank 0 - all chips
3402 flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
3403 # Flash bank 1 - only 256K chips
3404 flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
3407 Internally, the AT91SAM3 flash memory is organized as follows.
3408 Unlike the AT91SAM7 chips, these are not used as parameters
3409 to the @command{flash bank} command:
3412 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
3413 @item @emph{Bank Size:} 128K/64K Per flash bank
3414 @item @emph{Sectors:} 16 or 8 per bank
3415 @item @emph{SectorSize:} 8K Per Sector
3416 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
3419 The AT91SAM3 driver adds some additional commands:
3421 @deffn Command {at91sam3 gpnvm}
3422 @deffnx Command {at91sam3 gpnvm clear} number
3423 @deffnx Command {at91sam3 gpnvm set} number
3424 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
3425 With no parameters, @command{show} or @command{show all},
3426 shows the status of all GPNVM bits.
3427 With @command{show} @var{number}, displays that bit.
3429 With @command{set} @var{number} or @command{clear} @var{number},
3430 modifies that GPNVM bit.
3433 @deffn Command {at91sam3 info}
3434 This command attempts to display information about the AT91SAM3
3435 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
3436 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
3437 document id: doc6430A] and decodes the values. @emph{Second} it reads the
3438 various clock configuration registers and attempts to display how it
3439 believes the chip is configured. By default, the SLOWCLK is assumed to
3440 be 32768 Hz, see the command @command{at91sam3 slowclk}.
3443 @deffn Command {at91sam3 slowclk} [value]
3444 This command shows/sets the slow clock frequency used in the
3445 @command{at91sam3 info} command calculations above.
3449 @deffn {Flash Driver} at91sam7
3450 All members of the AT91SAM7 microcontroller family from Atmel include
3451 internal flash and use ARM7TDMI cores. The driver automatically
3452 recognizes a number of these chips using the chip identification
3453 register, and autoconfigures itself.
3456 flash bank at91sam7 0 0 0 0 $_TARGETNAME
3459 For chips which are not recognized by the controller driver, you must
3460 provide additional parameters in the following order:
3463 @item @var{chip_model} ... label used with @command{flash info}
3465 @item @var{sectors_per_bank}
3466 @item @var{pages_per_sector}
3467 @item @var{pages_size}
3468 @item @var{num_nvm_bits}
3469 @item @var{freq_khz} ... required if an external clock is provided,
3470 optional (but recommended) when the oscillator frequency is known
3473 It is recommended that you provide zeroes for all of those values
3474 except the clock frequency, so that everything except that frequency
3475 will be autoconfigured.
3476 Knowing the frequency helps ensure correct timings for flash access.
3478 The flash controller handles erases automatically on a page (128/256 byte)
3479 basis, so explicit erase commands are not necessary for flash programming.
3480 However, there is an ``EraseAll`` command that can erase an entire flash
3481 plane (of up to 256KB), and it will be used automatically when you issue
3482 @command{flash erase_sector} or @command{flash erase_address} commands.
3484 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
3485 Set or clear a ``General Purpose Non-Volatle Memory'' (GPNVM)
3486 bit for the processor. Each processor has a number of such bits,
3487 used for controlling features such as brownout detection (so they
3488 are not truly general purpose).
3490 This assumes that the first flash bank (number 0) is associated with
3491 the appropriate at91sam7 target.
3496 @deffn {Flash Driver} avr
3497 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
3498 @emph{The current implementation is incomplete.}
3499 @comment - defines mass_erase ... pointless given flash_erase_address
3502 @deffn {Flash Driver} ecosflash
3503 @emph{No idea what this is...}
3504 The @var{ecosflash} driver defines one mandatory parameter,
3505 the name of a modules of target code which is downloaded
3509 @deffn {Flash Driver} lpc2000
3510 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
3511 include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
3514 There are LPC2000 devices which are not supported by the @var{lpc2000}
3516 The LPC2888 is supported by the @var{lpc288x} driver.
3517 The LPC29xx family is supported by the @var{lpc2900} driver.
3520 The @var{lpc2000} driver defines two mandatory and one optional parameters,
3521 which must appear in the following order:
3524 @item @var{variant} ... required, may be
3525 @var{lpc2000_v1} (older LPC21xx and LPC22xx)
3526 @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
3527 or @var{lpc1700} (LPC175x and LPC176x)
3528 @item @var{clock_kHz} ... the frequency, in kiloHertz,
3529 at which the core is running
3530 @item @var{calc_checksum} ... optional (but you probably want to provide this!),
3531 telling the driver to calculate a valid checksum for the exception vector table.
3534 LPC flashes don't require the chip and bus width to be specified.
3537 flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
3538 lpc2000_v2 14765 calc_checksum
3541 @deffn {Command} {lpc2000 part_id} bank
3542 Displays the four byte part identifier associated with
3543 the specified flash @var{bank}.
3547 @deffn {Flash Driver} lpc288x
3548 The LPC2888 microcontroller from NXP needs slightly different flash
3549 support from its lpc2000 siblings.
3550 The @var{lpc288x} driver defines one mandatory parameter,
3551 the programming clock rate in Hz.
3552 LPC flashes don't require the chip and bus width to be specified.
3555 flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
3559 @deffn {Flash Driver} lpc2900
3560 This driver supports the LPC29xx ARM968E based microcontroller family
3563 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
3564 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
3565 sector layout are auto-configured by the driver.
3566 The driver has one additional mandatory parameter: The CPU clock rate
3567 (in kHz) at the time the flash operations will take place. Most of the time this
3568 will not be the crystal frequency, but a higher PLL frequency. The
3569 @code{reset-init} event handler in the board script is usually the place where
3572 The driver rejects flashless devices (currently the LPC2930).
3574 The EEPROM in LPC2900 devices is not mapped directly into the address space.
3575 It must be handled much more like NAND flash memory, and will therefore be
3576 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
3578 Sector protection in terms of the LPC2900 is handled transparently. Every time a
3579 sector needs to be erased or programmed, it is automatically unprotected.
3580 What is shown as protection status in the @code{flash info} command, is
3581 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
3582 sector from ever being erased or programmed again. As this is an irreversible
3583 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
3584 and not by the standard @code{flash protect} command.
3586 Example for a 125 MHz clock frequency:
3588 flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
3591 Some @code{lpc2900}-specific commands are defined. In the following command list,
3592 the @var{bank} parameter is the bank number as obtained by the
3593 @code{flash banks} command.
3595 @deffn Command {lpc2900 signature} bank
3596 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
3597 content. This is a hardware feature of the flash block, hence the calculation is
3598 very fast. You may use this to verify the content of a programmed device against
3603 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
3607 @deffn Command {lpc2900 read_custom} bank filename
3608 Reads the 912 bytes of customer information from the flash index sector, and
3609 saves it to a file in binary format.
3612 lpc2900 read_custom 0 /path_to/customer_info.bin
3616 The index sector of the flash is a @emph{write-only} sector. It cannot be
3617 erased! In order to guard against unintentional write access, all following
3618 commands need to be preceeded by a successful call to the @code{password}
3621 @deffn Command {lpc2900 password} bank password
3622 You need to use this command right before each of the following commands:
3623 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
3624 @code{lpc2900 secure_jtag}.
3626 The password string is fixed to "I_know_what_I_am_doing".
3629 lpc2900 password 0 I_know_what_I_am_doing
3630 Potentially dangerous operation allowed in next command!
3634 @deffn Command {lpc2900 write_custom} bank filename type
3635 Writes the content of the file into the customer info space of the flash index
3636 sector. The filetype can be specified with the @var{type} field. Possible values
3637 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
3638 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
3639 contain a single section, and the contained data length must be exactly
3641 @quotation Attention
3642 This cannot be reverted! Be careful!
3646 lpc2900 write_custom 0 /path_to/customer_info.bin bin
3650 @deffn Command {lpc2900 secure_sector} bank first last
3651 Secures the sector range from @var{first} to @var{last} (including) against
3652 further program and erase operations. The sector security will be effective
3653 after the next power cycle.
3654 @quotation Attention
3655 This cannot be reverted! Be careful!
3657 Secured sectors appear as @emph{protected} in the @code{flash info} command.
3660 lpc2900 secure_sector 0 1 1
3662 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
3663 # 0: 0x00000000 (0x2000 8kB) not protected
3664 # 1: 0x00002000 (0x2000 8kB) protected
3665 # 2: 0x00004000 (0x2000 8kB) not protected
3669 @deffn Command {lpc2900 secure_jtag} bank
3670 Irreversibly disable the JTAG port. The new JTAG security setting will be
3671 effective after the next power cycle.
3672 @quotation Attention
3673 This cannot be reverted! Be careful!
3677 lpc2900 secure_jtag 0
3682 @deffn {Flash Driver} ocl
3683 @emph{No idea what this is, other than using some arm7/arm9 core.}
3686 flash bank ocl 0 0 0 0 $_TARGETNAME
3690 @deffn {Flash Driver} pic32mx
3691 The PIC32MX microcontrollers are based on the MIPS 4K cores,
3692 and integrate flash memory.
3693 @emph{The current implementation is incomplete.}
3696 flash bank pix32mx 0 0 0 0 $_TARGETNAME
3699 @comment numerous *disabled* commands are defined:
3700 @comment - chip_erase ... pointless given flash_erase_address
3701 @comment - lock, unlock ... pointless given protect on/off (yes?)
3702 @comment - pgm_word ... shouldn't bank be deduced from address??
3703 Some pic32mx-specific commands are defined:
3704 @deffn Command {pic32mx pgm_word} address value bank
3705 Programs the specified 32-bit @var{value} at the given @var{address}
3706 in the specified chip @var{bank}.
3710 @deffn {Flash Driver} stellaris
3711 All members of the Stellaris LM3Sxxx microcontroller family from
3713 include internal flash and use ARM Cortex M3 cores.
3714 The driver automatically recognizes a number of these chips using
3715 the chip identification register, and autoconfigures itself.
3716 @footnote{Currently there is a @command{stellaris mass_erase} command.
3717 That seems pointless since the same effect can be had using the
3718 standard @command{flash erase_address} command.}
3721 flash bank stellaris 0 0 0 0 $_TARGETNAME
3725 @deffn {Flash Driver} stm32x
3726 All members of the STM32 microcontroller family from ST Microelectronics
3727 include internal flash and use ARM Cortex M3 cores.
3728 The driver automatically recognizes a number of these chips using
3729 the chip identification register, and autoconfigures itself.
3732 flash bank stm32x 0 0 0 0 $_TARGETNAME
3735 Some stm32x-specific commands
3736 @footnote{Currently there is a @command{stm32x mass_erase} command.
3737 That seems pointless since the same effect can be had using the
3738 standard @command{flash erase_address} command.}
3741 @deffn Command {stm32x lock} num
3742 Locks the entire stm32 device.
3743 The @var{num} parameter is a value shown by @command{flash banks}.
3746 @deffn Command {stm32x unlock} num
3747 Unlocks the entire stm32 device.
3748 The @var{num} parameter is a value shown by @command{flash banks}.
3751 @deffn Command {stm32x options_read} num
3752 Read and display the stm32 option bytes written by
3753 the @command{stm32x options_write} command.
3754 The @var{num} parameter is a value shown by @command{flash banks}.
3757 @deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
3758 Writes the stm32 option byte with the specified values.
3759 The @var{num} parameter is a value shown by @command{flash banks}.
3763 @deffn {Flash Driver} str7x
3764 All members of the STR7 microcontroller family from ST Microelectronics
3765 include internal flash and use ARM7TDMI cores.
3766 The @var{str7x} driver defines one mandatory parameter, @var{variant},
3767 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
3770 flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
3773 @deffn Command {str7x disable_jtag} bank
3774 Activate the Debug/Readout protection mechanism
3775 for the specified flash bank.
3779 @deffn {Flash Driver} str9x
3780 Most members of the STR9 microcontroller family from ST Microelectronics
3781 include internal flash and use ARM966E cores.
3782 The str9 needs the flash controller to be configured using
3783 the @command{str9x flash_config} command prior to Flash programming.
3786 flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
3787 str9x flash_config 0 4 2 0 0x80000
3790 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
3791 Configures the str9 flash controller.
3792 The @var{num} parameter is a value shown by @command{flash banks}.
3795 @item @var{bbsr} - Boot Bank Size register
3796 @item @var{nbbsr} - Non Boot Bank Size register
3797 @item @var{bbadr} - Boot Bank Start Address register
3798 @item @var{nbbadr} - Boot Bank Start Address register
3804 @deffn {Flash Driver} tms470
3805 Most members of the TMS470 microcontroller family from Texas Instruments
3806 include internal flash and use ARM7TDMI cores.
3807 This driver doesn't require the chip and bus width to be specified.
3809 Some tms470-specific commands are defined:
3811 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
3812 Saves programming keys in a register, to enable flash erase and write commands.
3815 @deffn Command {tms470 osc_mhz} clock_mhz
3816 Reports the clock speed, which is used to calculate timings.
3819 @deffn Command {tms470 plldis} (0|1)
3820 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
3825 @subsection str9xpec driver
3828 Here is some background info to help
3829 you better understand how this driver works. OpenOCD has two flash drivers for
3833 Standard driver @option{str9x} programmed via the str9 core. Normally used for
3834 flash programming as it is faster than the @option{str9xpec} driver.
3836 Direct programming @option{str9xpec} using the flash controller. This is an
3837 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
3838 core does not need to be running to program using this flash driver. Typical use
3839 for this driver is locking/unlocking the target and programming the option bytes.
3842 Before we run any commands using the @option{str9xpec} driver we must first disable
3843 the str9 core. This example assumes the @option{str9xpec} driver has been
3844 configured for flash bank 0.
3846 # assert srst, we do not want core running
3847 # while accessing str9xpec flash driver
3849 # turn off target polling
3852 str9xpec enable_turbo 0
3854 str9xpec options_read 0
3855 # re-enable str9 core
3856 str9xpec disable_turbo 0
3860 The above example will read the str9 option bytes.
3861 When performing a unlock remember that you will not be able to halt the str9 - it
3862 has been locked. Halting the core is not required for the @option{str9xpec} driver
3863 as mentioned above, just issue the commands above manually or from a telnet prompt.
3865 @deffn {Flash Driver} str9xpec
3866 Only use this driver for locking/unlocking the device or configuring the option bytes.
3867 Use the standard str9 driver for programming.
3868 Before using the flash commands the turbo mode must be enabled using the
3869 @command{str9xpec enable_turbo} command.
3871 Several str9xpec-specific commands are defined:
3873 @deffn Command {str9xpec disable_turbo} num
3874 Restore the str9 into JTAG chain.
3877 @deffn Command {str9xpec enable_turbo} num
3878 Enable turbo mode, will simply remove the str9 from the chain and talk
3879 directly to the embedded flash controller.
3882 @deffn Command {str9xpec lock} num
3883 Lock str9 device. The str9 will only respond to an unlock command that will
3887 @deffn Command {str9xpec part_id} num
3888 Prints the part identifier for bank @var{num}.
3891 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
3892 Configure str9 boot bank.
3895 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
3896 Configure str9 lvd source.
3899 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
3900 Configure str9 lvd threshold.
3903 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
3904 Configure str9 lvd reset warning source.
3907 @deffn Command {str9xpec options_read} num
3908 Read str9 option bytes.
3911 @deffn Command {str9xpec options_write} num
3912 Write str9 option bytes.
3915 @deffn Command {str9xpec unlock} num
3924 @subsection mFlash Configuration
3925 @cindex mFlash Configuration
3927 @deffn {Config Command} {mflash bank} soc base RST_pin target
3928 Configures a mflash for @var{soc} host bank at
3930 The pin number format depends on the host GPIO naming convention.
3931 Currently, the mflash driver supports s3c2440 and pxa270.
3933 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
3936 mflash bank s3c2440 0x10000000 1b 0
3939 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
3942 mflash bank pxa270 0x08000000 43 0
3946 @subsection mFlash commands
3947 @cindex mFlash commands
3949 @deffn Command {mflash config pll} frequency
3950 Configure mflash PLL.
3951 The @var{frequency} is the mflash input frequency, in Hz.
3952 Issuing this command will erase mflash's whole internal nand and write new pll.
3953 After this command, mflash needs power-on-reset for normal operation.
3954 If pll was newly configured, storage and boot(optional) info also need to be update.
3957 @deffn Command {mflash config boot}
3958 Configure bootable option.
3959 If bootable option is set, mflash offer the first 8 sectors
3963 @deffn Command {mflash config storage}
3964 Configure storage information.
3965 For the normal storage operation, this information must be
3969 @deffn Command {mflash dump} num filename offset size
3970 Dump @var{size} bytes, starting at @var{offset} bytes from the
3971 beginning of the bank @var{num}, to the file named @var{filename}.
3974 @deffn Command {mflash probe}
3978 @deffn Command {mflash write} num filename offset
3979 Write the binary file @var{filename} to mflash bank @var{num}, starting at
3980 @var{offset} bytes from the beginning of the bank.
3983 @node NAND Flash Commands
3984 @chapter NAND Flash Commands
3987 Compared to NOR or SPI flash, NAND devices are inexpensive
3988 and high density. Today's NAND chips, and multi-chip modules,
3989 commonly hold multiple GigaBytes of data.
3991 NAND chips consist of a number of ``erase blocks'' of a given
3992 size (such as 128 KBytes), each of which is divided into a
3993 number of pages (of perhaps 512 or 2048 bytes each). Each
3994 page of a NAND flash has an ``out of band'' (OOB) area to hold
3995 Error Correcting Code (ECC) and other metadata, usually 16 bytes
3996 of OOB for every 512 bytes of page data.
3998 One key characteristic of NAND flash is that its error rate
3999 is higher than that of NOR flash. In normal operation, that
4000 ECC is used to correct and detect errors. However, NAND
4001 blocks can also wear out and become unusable; those blocks
4002 are then marked "bad". NAND chips are even shipped from the
4003 manufacturer with a few bad blocks. The highest density chips
4004 use a technology (MLC) that wears out more quickly, so ECC
4005 support is increasingly important as a way to detect blocks
4006 that have begun to fail, and help to preserve data integrity
4007 with techniques such as wear leveling.
4009 Software is used to manage the ECC. Some controllers don't
4010 support ECC directly; in those cases, software ECC is used.
4011 Other controllers speed up the ECC calculations with hardware.
4012 Single-bit error correction hardware is routine. Controllers
4013 geared for newer MLC chips may correct 4 or more errors for
4014 every 512 bytes of data.
4016 You will need to make sure that any data you write using
4017 OpenOCD includes the apppropriate kind of ECC. For example,
4018 that may mean passing the @code{oob_softecc} flag when
4019 writing NAND data, or ensuring that the correct hardware
4022 The basic steps for using NAND devices include:
4024 @item Declare via the command @command{nand device}
4025 @* Do this in a board-specific configuration file,
4026 passing parameters as needed by the controller.
4027 @item Configure each device using @command{nand probe}.
4028 @* Do this only after the associated target is set up,
4029 such as in its reset-init script or in procures defined
4030 to access that device.
4031 @item Operate on the flash via @command{nand subcommand}
4032 @* Often commands to manipulate the flash are typed by a human, or run
4033 via a script in some automated way. Common task include writing a
4034 boot loader, operating system, or other data needed to initialize or
4038 @b{NOTE:} At the time this text was written, the largest NAND
4039 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
4040 This is because the variables used to hold offsets and lengths
4041 are only 32 bits wide.
4042 (Larger chips may work in some cases, unless an offset or length
4043 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
4044 Some larger devices will work, since they are actually multi-chip
4045 modules with two smaller chips and individual chipselect lines.
4047 @anchor{NAND Configuration}
4048 @section NAND Configuration Commands
4049 @cindex NAND configuration
4051 NAND chips must be declared in configuration scripts,
4052 plus some additional configuration that's done after
4053 OpenOCD has initialized.
4055 @deffn {Config Command} {nand device} controller target [configparams...]
4056 Declares a NAND device, which can be read and written to
4057 after it has been configured through @command{nand probe}.
4058 In OpenOCD, devices are single chips; this is unlike some
4059 operating systems, which may manage multiple chips as if
4060 they were a single (larger) device.
4061 In some cases, configuring a device will activate extra
4062 commands; see the controller-specific documentation.
4064 @b{NOTE:} This command is not available after OpenOCD
4065 initialization has completed. Use it in board specific
4066 configuration files, not interactively.
4069 @item @var{controller} ... identifies the controller driver
4070 associated with the NAND device being declared.
4071 @xref{NAND Driver List}.
4072 @item @var{target} ... names the target used when issuing
4073 commands to the NAND controller.
4074 @comment Actually, it's currently a controller-specific parameter...
4075 @item @var{configparams} ... controllers may support, or require,
4076 additional parameters. See the controller-specific documentation
4077 for more information.
4081 @deffn Command {nand list}
4082 Prints a summary of each device declared
4083 using @command{nand device}, numbered from zero.
4084 Note that un-probed devices show no details.
4087 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4088 blocksize: 131072, blocks: 8192
4089 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
4090 blocksize: 131072, blocks: 8192
4095 @deffn Command {nand probe} num
4096 Probes the specified device to determine key characteristics
4097 like its page and block sizes, and how many blocks it has.
4098 The @var{num} parameter is the value shown by @command{nand list}.
4099 You must (successfully) probe a device before you can use
4100 it with most other NAND commands.
4103 @section Erasing, Reading, Writing to NAND Flash
4105 @deffn Command {nand dump} num filename offset length [oob_option]
4106 @cindex NAND reading
4107 Reads binary data from the NAND device and writes it to the file,
4108 starting at the specified offset.
4109 The @var{num} parameter is the value shown by @command{nand list}.
4111 Use a complete path name for @var{filename}, so you don't depend
4112 on the directory used to start the OpenOCD server.
4114 The @var{offset} and @var{length} must be exact multiples of the
4115 device's page size. They describe a data region; the OOB data
4116 associated with each such page may also be accessed.
4118 @b{NOTE:} At the time this text was written, no error correction
4119 was done on the data that's read, unless raw access was disabled
4120 and the underlying NAND controller driver had a @code{read_page}
4121 method which handled that error correction.
4123 By default, only page data is saved to the specified file.
4124 Use an @var{oob_option} parameter to save OOB data:
4126 @item no oob_* parameter
4127 @*Output file holds only page data; OOB is discarded.
4128 @item @code{oob_raw}
4129 @*Output file interleaves page data and OOB data;
4130 the file will be longer than "length" by the size of the
4131 spare areas associated with each data page.
4132 Note that this kind of "raw" access is different from
4133 what's implied by @command{nand raw_access}, which just
4134 controls whether a hardware-aware access method is used.
4135 @item @code{oob_only}
4136 @*Output file has only raw OOB data, and will
4137 be smaller than "length" since it will contain only the
4138 spare areas associated with each data page.
4142 @deffn Command {nand erase} num [offset length]
4143 @cindex NAND erasing
4144 @cindex NAND programming
4145 Erases blocks on the specified NAND device, starting at the
4146 specified @var{offset} and continuing for @var{length} bytes.
4147 Both of those values must be exact multiples of the device's
4148 block size, and the region they specify must fit entirely in the chip.
4149 If those parameters are not specified,
4150 the whole NAND chip will be erased.
4151 The @var{num} parameter is the value shown by @command{nand list}.
4153 @b{NOTE:} This command will try to erase bad blocks, when told
4154 to do so, which will probably invalidate the manufacturer's bad
4156 For the remainder of the current server session, @command{nand info}
4157 will still report that the block ``is'' bad.
4160 @deffn Command {nand write} num filename offset [option...]
4161 @cindex NAND writing
4162 @cindex NAND programming
4163 Writes binary data from the file into the specified NAND device,
4164 starting at the specified offset. Those pages should already
4165 have been erased; you can't change zero bits to one bits.
4166 The @var{num} parameter is the value shown by @command{nand list}.
4168 Use a complete path name for @var{filename}, so you don't depend
4169 on the directory used to start the OpenOCD server.
4171 The @var{offset} must be an exact multiple of the device's page size.
4172 All data in the file will be written, assuming it doesn't run
4173 past the end of the device.
4174 Only full pages are written, and any extra space in the last
4175 page will be filled with 0xff bytes. (That includes OOB data,
4176 if that's being written.)
4178 @b{NOTE:} At the time this text was written, bad blocks are
4179 ignored. That is, this routine will not skip bad blocks,
4180 but will instead try to write them. This can cause problems.
4182 Provide at most one @var{option} parameter. With some
4183 NAND drivers, the meanings of these parameters may change
4184 if @command{nand raw_access} was used to disable hardware ECC.
4186 @item no oob_* parameter
4187 @*File has only page data, which is written.
4188 If raw acccess is in use, the OOB area will not be written.
4189 Otherwise, if the underlying NAND controller driver has
4190 a @code{write_page} routine, that routine may write the OOB
4191 with hardware-computed ECC data.
4192 @item @code{oob_only}
4193 @*File has only raw OOB data, which is written to the OOB area.
4194 Each page's data area stays untouched. @i{This can be a dangerous
4195 option}, since it can invalidate the ECC data.
4196 You may need to force raw access to use this mode.
4197 @item @code{oob_raw}
4198 @*File interleaves data and OOB data, both of which are written
4199 If raw access is enabled, the data is written first, then the
4201 Otherwise, if the underlying NAND controller driver has
4202 a @code{write_page} routine, that routine may modify the OOB
4203 before it's written, to include hardware-computed ECC data.
4204 @item @code{oob_softecc}
4205 @*File has only page data, which is written.
4206 The OOB area is filled with 0xff, except for a standard 1-bit
4207 software ECC code stored in conventional locations.
4208 You might need to force raw access to use this mode, to prevent
4209 the underlying driver from applying hardware ECC.
4210 @item @code{oob_softecc_kw}
4211 @*File has only page data, which is written.
4212 The OOB area is filled with 0xff, except for a 4-bit software ECC
4213 specific to the boot ROM in Marvell Kirkwood SoCs.
4214 You might need to force raw access to use this mode, to prevent
4215 the underlying driver from applying hardware ECC.
4219 @section Other NAND commands
4220 @cindex NAND other commands
4222 @deffn Command {nand check_bad_blocks} [offset length]
4223 Checks for manufacturer bad block markers on the specified NAND
4224 device. If no parameters are provided, checks the whole
4225 device; otherwise, starts at the specified @var{offset} and
4226 continues for @var{length} bytes.
4227 Both of those values must be exact multiples of the device's
4228 block size, and the region they specify must fit entirely in the chip.
4229 The @var{num} parameter is the value shown by @command{nand list}.
4231 @b{NOTE:} Before using this command you should force raw access
4232 with @command{nand raw_access enable} to ensure that the underlying
4233 driver will not try to apply hardware ECC.
4236 @deffn Command {nand info} num
4237 The @var{num} parameter is the value shown by @command{nand list}.
4238 This prints the one-line summary from "nand list", plus for
4239 devices which have been probed this also prints any known
4240 status for each block.
4243 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
4244 Sets or clears an flag affecting how page I/O is done.
4245 The @var{num} parameter is the value shown by @command{nand list}.
4247 This flag is cleared (disabled) by default, but changing that
4248 value won't affect all NAND devices. The key factor is whether
4249 the underlying driver provides @code{read_page} or @code{write_page}
4250 methods. If it doesn't provide those methods, the setting of
4251 this flag is irrelevant; all access is effectively ``raw''.
4253 When those methods exist, they are normally used when reading
4254 data (@command{nand dump} or reading bad block markers) or
4255 writing it (@command{nand write}). However, enabling
4256 raw access (setting the flag) prevents use of those methods,
4257 bypassing hardware ECC logic.
4258 @i{This can be a dangerous option}, since writing blocks
4259 with the wrong ECC data can cause them to be marked as bad.
4262 @anchor{NAND Driver List}
4263 @section NAND Drivers, Options, and Commands
4264 As noted above, the @command{nand device} command allows
4265 driver-specific options and behaviors.
4266 Some controllers also activate controller-specific commands.
4268 @deffn {NAND Driver} davinci
4269 This driver handles the NAND controllers found on DaVinci family
4270 chips from Texas Instruments.
4271 It takes three extra parameters:
4272 address of the NAND chip;
4273 hardware ECC mode to use (@option{hwecc1},
4274 @option{hwecc4}, @option{hwecc4_infix});
4275 address of the AEMIF controller on this processor.
4277 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
4279 All DaVinci processors support the single-bit ECC hardware,
4280 and newer ones also support the four-bit ECC hardware.
4281 The @code{write_page} and @code{read_page} methods are used
4282 to implement those ECC modes, unless they are disabled using
4283 the @command{nand raw_access} command.
4286 @deffn {NAND Driver} lpc3180
4287 These controllers require an extra @command{nand device}
4288 parameter: the clock rate used by the controller.
4289 @deffn Command {lpc3180 select} num [mlc|slc]
4290 Configures use of the MLC or SLC controller mode.
4291 MLC implies use of hardware ECC.
4292 The @var{num} parameter is the value shown by @command{nand list}.
4295 At this writing, this driver includes @code{write_page}
4296 and @code{read_page} methods. Using @command{nand raw_access}
4297 to disable those methods will prevent use of hardware ECC
4298 in the MLC controller mode, but won't change SLC behavior.
4300 @comment current lpc3180 code won't issue 5-byte address cycles
4302 @deffn {NAND Driver} orion
4303 These controllers require an extra @command{nand device}
4304 parameter: the address of the controller.
4306 nand device orion 0xd8000000
4308 These controllers don't define any specialized commands.
4309 At this writing, their drivers don't include @code{write_page}
4310 or @code{read_page} methods, so @command{nand raw_access} won't
4311 change any behavior.
4314 @deffn {NAND Driver} s3c2410
4315 @deffnx {NAND Driver} s3c2412
4316 @deffnx {NAND Driver} s3c2440
4317 @deffnx {NAND Driver} s3c2443
4318 These S3C24xx family controllers don't have any special
4319 @command{nand device} options, and don't define any
4320 specialized commands.
4321 At this writing, their drivers don't include @code{write_page}
4322 or @code{read_page} methods, so @command{nand raw_access} won't
4323 change any behavior.
4326 @node PLD/FPGA Commands
4327 @chapter PLD/FPGA Commands
4331 Programmable Logic Devices (PLDs) and the more flexible
4332 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
4333 OpenOCD can support programming them.
4334 Although PLDs are generally restrictive (cells are less functional, and
4335 there are no special purpose cells for memory or computational tasks),
4336 they share the same OpenOCD infrastructure.
4337 Accordingly, both are called PLDs here.
4339 @section PLD/FPGA Configuration and Commands
4341 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
4342 OpenOCD maintains a list of PLDs available for use in various commands.
4343 Also, each such PLD requires a driver.
4345 They are referenced by the number shown by the @command{pld devices} command,
4346 and new PLDs are defined by @command{pld device driver_name}.
4348 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
4349 Defines a new PLD device, supported by driver @var{driver_name},
4350 using the TAP named @var{tap_name}.
4351 The driver may make use of any @var{driver_options} to configure its
4355 @deffn {Command} {pld devices}
4356 Lists the PLDs and their numbers.
4359 @deffn {Command} {pld load} num filename
4360 Loads the file @file{filename} into the PLD identified by @var{num}.
4361 The file format must be inferred by the driver.
4364 @section PLD/FPGA Drivers, Options, and Commands
4366 Drivers may support PLD-specific options to the @command{pld device}
4367 definition command, and may also define commands usable only with
4368 that particular type of PLD.
4370 @deffn {FPGA Driver} virtex2
4371 Virtex-II is a family of FPGAs sold by Xilinx.
4372 It supports the IEEE 1532 standard for In-System Configuration (ISC).
4373 No driver-specific PLD definition options are used,
4374 and one driver-specific command is defined.
4376 @deffn {Command} {virtex2 read_stat} num
4377 Reads and displays the Virtex-II status register (STAT)
4382 @node General Commands
4383 @chapter General Commands
4386 The commands documented in this chapter here are common commands that
4387 you, as a human, may want to type and see the output of. Configuration type
4388 commands are documented elsewhere.
4392 @item @b{Source Of Commands}
4393 @* OpenOCD commands can occur in a configuration script (discussed
4394 elsewhere) or typed manually by a human or supplied programatically,
4395 or via one of several TCP/IP Ports.
4397 @item @b{From the human}
4398 @* A human should interact with the telnet interface (default port: 4444)
4399 or via GDB (default port 3333).
4401 To issue commands from within a GDB session, use the @option{monitor}
4402 command, e.g. use @option{monitor poll} to issue the @option{poll}
4403 command. All output is relayed through the GDB session.
4405 @item @b{Machine Interface}
4406 The Tcl interface's intent is to be a machine interface. The default Tcl
4411 @section Daemon Commands
4413 @deffn {Command} exit
4414 Exits the current telnet session.
4417 @c note EXTREMELY ANNOYING word wrap at column 75
4418 @c even when lines are e.g. 100+ columns ...
4419 @c coded in startup.tcl
4420 @deffn {Command} help [string]
4421 With no parameters, prints help text for all commands.
4422 Otherwise, prints each helptext containing @var{string}.
4423 Not every command provides helptext.
4426 @deffn Command sleep msec [@option{busy}]
4427 Wait for at least @var{msec} milliseconds before resuming.
4428 If @option{busy} is passed, busy-wait instead of sleeping.
4429 (This option is strongly discouraged.)
4430 Useful in connection with script files
4431 (@command{script} command and @command{target_name} configuration).
4434 @deffn Command shutdown
4435 Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
4438 @anchor{debug_level}
4439 @deffn Command debug_level [n]
4440 @cindex message level
4441 Display debug level.
4442 If @var{n} (from 0..3) is provided, then set it to that level.
4443 This affects the kind of messages sent to the server log.
4444 Level 0 is error messages only;
4445 level 1 adds warnings;
4446 level 2 adds informational messages;
4447 and level 3 adds debugging messages.
4448 The default is level 2, but that can be overridden on
4449 the command line along with the location of that log
4450 file (which is normally the server's standard output).
4454 @deffn Command fast (@option{enable}|@option{disable})
4456 Set default behaviour of OpenOCD to be "fast and dangerous".
4458 At this writing, this only affects the defaults for two ARM7/ARM9 parameters:
4459 fast memory access, and DCC downloads. Those parameters may still be
4460 individually overridden.
4462 The target specific "dangerous" optimisation tweaking options may come and go
4463 as more robust and user friendly ways are found to ensure maximum throughput
4464 and robustness with a minimum of configuration.
4466 Typically the "fast enable" is specified first on the command line:
4469 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
4473 @deffn Command echo message
4474 Logs a message at "user" priority.
4475 Output @var{message} to stdout.
4477 echo "Downloading kernel -- please wait"
4481 @deffn Command log_output [filename]
4482 Redirect logging to @var{filename};
4483 the initial log output channel is stderr.
4486 @anchor{Target State handling}
4487 @section Target State handling
4490 @cindex target initialization
4492 In this section ``target'' refers to a CPU configured as
4493 shown earlier (@pxref{CPU Configuration}).
4494 These commands, like many, implicitly refer to
4495 a current target which is used to perform the
4496 various operations. The current target may be changed
4497 by using @command{targets} command with the name of the
4498 target which should become current.
4500 @deffn Command reg [(number|name) [value]]
4501 Access a single register by @var{number} or by its @var{name}.
4503 @emph{With no arguments}:
4504 list all available registers for the current target,
4505 showing number, name, size, value, and cache status.
4507 @emph{With number/name}: display that register's value.
4509 @emph{With both number/name and value}: set register's value.
4511 Cores may have surprisingly many registers in their
4512 Debug and trace infrastructure:
4516 (0) r0 (/32): 0x0000D3C2 (dirty: 1, valid: 1)
4517 (1) r1 (/32): 0xFD61F31C (dirty: 0, valid: 1)
4518 (2) r2 (/32): 0x00022551 (dirty: 0, valid: 1)
4520 (164) ETM_CONTEXTID_COMPARATOR_MASK (/32): \
4521 0x00000000 (dirty: 0, valid: 0)
4526 @deffn Command halt [ms]
4527 @deffnx Command wait_halt [ms]
4528 The @command{halt} command first sends a halt request to the target,
4529 which @command{wait_halt} doesn't.
4530 Otherwise these behave the same: wait up to @var{ms} milliseconds,
4531 or 5 seconds if there is no parameter, for the target to halt
4532 (and enter debug mode).
4533 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
4536 On ARM cores, software using the @emph{wait for interrupt} operation
4537 often blocks the JTAG access needed by a @command{halt} command.
4538 This is because that operation also puts the core into a low
4539 power mode by gating the core clock;
4540 but the core clock is needed to detect JTAG clock transitions.
4542 One partial workaround uses adaptive clocking: when the core is
4543 interrupted the operation completes, then JTAG clocks are accepted
4544 at least until the interrupt handler completes.
4545 However, this workaround is often unusable since the processor, board,
4546 and JTAG adapter must all support adaptive JTAG clocking.
4547 Also, it can't work until an interrupt is issued.
4549 A more complete workaround is to not use that operation while you
4550 work with a JTAG debugger.
4551 Tasking environments generaly have idle loops where the body is the
4552 @emph{wait for interrupt} operation.
4553 (On older cores, it is a coprocessor action;
4554 newer cores have a @option{wfi} instruction.)
4555 Such loops can just remove that operation, at the cost of higher
4556 power consumption (because the CPU is needlessly clocked).
4561 @deffn Command resume [address]
4562 Resume the target at its current code position,
4563 or the optional @var{address} if it is provided.
4564 OpenOCD will wait 5 seconds for the target to resume.
4567 @deffn Command step [address]
4568 Single-step the target at its current code position,
4569 or the optional @var{address} if it is provided.
4572 @anchor{Reset Command}
4573 @deffn Command reset
4574 @deffnx Command {reset run}
4575 @deffnx Command {reset halt}
4576 @deffnx Command {reset init}
4577 Perform as hard a reset as possible, using SRST if possible.
4578 @emph{All defined targets will be reset, and target
4579 events will fire during the reset sequence.}
4581 The optional parameter specifies what should
4582 happen after the reset.
4583 If there is no parameter, a @command{reset run} is executed.
4584 The other options will not work on all systems.
4585 @xref{Reset Configuration}.
4588 @item @b{run} Let the target run
4589 @item @b{halt} Immediately halt the target
4590 @item @b{init} Immediately halt the target, and execute the reset-init script
4594 @deffn Command soft_reset_halt
4595 Requesting target halt and executing a soft reset. This is often used
4596 when a target cannot be reset and halted. The target, after reset is
4597 released begins to execute code. OpenOCD attempts to stop the CPU and
4598 then sets the program counter back to the reset vector. Unfortunately
4599 the code that was executed may have left the hardware in an unknown
4603 @section I/O Utilities
4605 These commands are available when
4606 OpenOCD is built with @option{--enable-ioutil}.
4607 They are mainly useful on embedded targets,
4609 Hosts with operating systems have complementary tools.
4611 @emph{Note:} there are several more such commands.
4613 @deffn Command append_file filename [string]*
4614 Appends the @var{string} parameters to
4615 the text file @file{filename}.
4616 Each string except the last one is followed by one space.
4617 The last string is followed by a newline.
4620 @deffn Command cat filename
4621 Reads and displays the text file @file{filename}.
4624 @deffn Command cp src_filename dest_filename
4625 Copies contents from the file @file{src_filename}
4626 into @file{dest_filename}.
4630 @emph{No description provided.}
4634 @emph{No description provided.}
4638 @emph{No description provided.}
4641 @deffn Command meminfo
4642 Display available RAM memory on OpenOCD host.
4643 Used in OpenOCD regression testing scripts.
4647 @emph{No description provided.}
4651 @emph{No description provided.}
4654 @deffn Command rm filename
4655 @c "rm" has both normal and Jim-level versions??
4656 Unlinks the file @file{filename}.
4659 @deffn Command trunc filename
4660 Removes all data in the file @file{filename}.
4663 @anchor{Memory access}
4664 @section Memory access commands
4665 @cindex memory access
4667 These commands allow accesses of a specific size to the memory
4668 system. Often these are used to configure the current target in some
4669 special way. For example - one may need to write certain values to the
4670 SDRAM controller to enable SDRAM.
4673 @item Use the @command{targets} (plural) command
4674 to change the current target.
4675 @item In system level scripts these commands are deprecated.
4676 Please use their TARGET object siblings to avoid making assumptions
4677 about what TAP is the current target, or about MMU configuration.
4680 @deffn Command mdw addr [count]
4681 @deffnx Command mdh addr [count]
4682 @deffnx Command mdb addr [count]
4683 Display contents of address @var{addr}, as
4684 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4685 or 8-bit bytes (@command{mdb}).
4686 If @var{count} is specified, displays that many units.
4687 (If you want to manipulate the data instead of displaying it,
4688 see the @code{mem2array} primitives.)
4691 @deffn Command mww addr word
4692 @deffnx Command mwh addr halfword
4693 @deffnx Command mwb addr byte
4694 Writes the specified @var{word} (32 bits),
4695 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4696 at the specified address @var{addr}.
4700 @anchor{Image access}
4701 @section Image loading commands
4702 @cindex image loading
4703 @cindex image dumping
4706 @deffn Command {dump_image} filename address size
4707 Dump @var{size} bytes of target memory starting at @var{address} to the
4708 binary file named @var{filename}.
4711 @deffn Command {fast_load}
4712 Loads an image stored in memory by @command{fast_load_image} to the
4713 current target. Must be preceeded by fast_load_image.
4716 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4717 Normally you should be using @command{load_image} or GDB load. However, for
4718 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
4719 host), storing the image in memory and uploading the image to the target
4720 can be a way to upload e.g. multiple debug sessions when the binary does not change.
4721 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
4722 memory, i.e. does not affect target. This approach is also useful when profiling
4723 target programming performance as I/O and target programming can easily be profiled
4728 @deffn Command {load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4729 Load image from file @var{filename} to target memory at @var{address}.
4730 The file format may optionally be specified
4731 (@option{bin}, @option{ihex}, or @option{elf})
4734 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
4735 Displays image section sizes and addresses
4736 as if @var{filename} were loaded into target memory
4737 starting at @var{address} (defaults to zero).
4738 The file format may optionally be specified
4739 (@option{bin}, @option{ihex}, or @option{elf})
4742 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
4743 Verify @var{filename} against target memory starting at @var{address}.
4744 The file format may optionally be specified
4745 (@option{bin}, @option{ihex}, or @option{elf})
4746 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
4750 @section Breakpoint and Watchpoint commands
4754 CPUs often make debug modules accessible through JTAG, with
4755 hardware support for a handful of code breakpoints and data
4757 In addition, CPUs almost always support software breakpoints.
4759 @deffn Command {bp} [address len [@option{hw}]]
4760 With no parameters, lists all active breakpoints.
4761 Else sets a breakpoint on code execution starting
4762 at @var{address} for @var{length} bytes.
4763 This is a software breakpoint, unless @option{hw} is specified
4764 in which case it will be a hardware breakpoint.
4766 (@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
4767 for similar mechanisms that do not consume hardware breakpoints.)
4770 @deffn Command {rbp} address
4771 Remove the breakpoint at @var{address}.
4774 @deffn Command {rwp} address
4775 Remove data watchpoint on @var{address}
4778 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
4779 With no parameters, lists all active watchpoints.
4780 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
4781 The watch point is an "access" watchpoint unless
4782 the @option{r} or @option{w} parameter is provided,
4783 defining it as respectively a read or write watchpoint.
4784 If a @var{value} is provided, that value is used when determining if
4785 the watchpoint should trigger. The value may be first be masked
4786 using @var{mask} to mark ``don't care'' fields.
4789 @section Misc Commands
4792 @deffn Command {profile} seconds filename
4793 Profiling samples the CPU's program counter as quickly as possible,
4794 which is useful for non-intrusive stochastic profiling.
4795 Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
4798 @deffn Command {version}
4799 Displays a string identifying the version of this OpenOCD server.
4802 @deffn Command {virt2phys} virtual_address
4803 Requests the current target to map the specified @var{virtual_address}
4804 to its corresponding physical address, and displays the result.
4807 @node Architecture and Core Commands
4808 @chapter Architecture and Core Commands
4809 @cindex Architecture Specific Commands
4810 @cindex Core Specific Commands
4812 Most CPUs have specialized JTAG operations to support debugging.
4813 OpenOCD packages most such operations in its standard command framework.
4814 Some of those operations don't fit well in that framework, so they are
4815 exposed here as architecture or implementation (core) specific commands.
4817 @anchor{ARM Hardware Tracing}
4818 @section ARM Hardware Tracing
4823 CPUs based on ARM cores may include standard tracing interfaces,
4824 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
4825 address and data bus trace records to a ``Trace Port''.
4829 Development-oriented boards will sometimes provide a high speed
4830 trace connector for collecting that data, when the particular CPU
4831 supports such an interface.
4832 (The standard connector is a 38-pin Mictor, with both JTAG
4833 and trace port support.)
4834 Those trace connectors are supported by higher end JTAG adapters
4835 and some logic analyzer modules; frequently those modules can
4836 buffer several megabytes of trace data.
4837 Configuring an ETM coupled to such an external trace port belongs
4838 in the board-specific configuration file.
4840 If the CPU doesn't provide an external interface, it probably
4841 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
4842 dedicated SRAM. 4KBytes is one common ETB size.
4843 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
4844 (target) configuration file, since it works the same on all boards.
4847 ETM support in OpenOCD doesn't seem to be widely used yet.
4850 ETM support may be buggy, and at least some @command{etm config}
4851 parameters should be detected by asking the ETM for them.
4852 It seems like a GDB hookup should be possible,
4853 as well as triggering trace on specific events
4854 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
4855 There should be GUI tools to manipulate saved trace data and help
4856 analyse it in conjunction with the source code.
4857 It's unclear how much of a common interface is shared
4858 with the current XScale trace support, or should be
4859 shared with eventual Nexus-style trace module support.
4860 At this writing (September 2009) only ARM7 and ARM9 support
4861 for ETM modules is available. The code should be able to
4862 work with some newer cores; but not all of them support
4863 this original style of JTAG access.
4866 @subsection ETM Configuration
4867 ETM setup is coupled with the trace port driver configuration.
4869 @deffn {Config Command} {etm config} target width mode clocking driver
4870 Declares the ETM associated with @var{target}, and associates it
4871 with a given trace port @var{driver}. @xref{Trace Port Drivers}.
4873 Several of the parameters must reflect the trace port configuration.
4874 The @var{width} must be either 4, 8, or 16.
4875 The @var{mode} must be @option{normal}, @option{multiplexted},
4876 or @option{demultiplexted}.
4877 The @var{clocking} must be @option{half} or @option{full}.
4880 You can see the ETM registers using the @command{reg} command.
4881 Not all possible registers are present in every ETM.
4882 Most of the registers are write-only, and are used to configure
4883 what CPU activities are traced.
4887 @deffn Command {etm info}
4888 Displays information about the current target's ETM.
4891 @deffn Command {etm status}
4892 Displays status of the current target's ETM:
4893 is the ETM idle, or is it collecting data?
4894 Did trace data overflow?
4898 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
4899 Displays what data that ETM will collect.
4900 If arguments are provided, first configures that data.
4901 When the configuration changes, tracing is stopped
4902 and any buffered trace data is invalidated.
4905 @item @var{type} ... one of
4906 @option{none} (save nothing),
4907 @option{data} (save data),
4908 @option{address} (save addresses),
4909 @option{all} (save data and addresses)
4910 @item @var{context_id_bits} ... 0, 8, 16, or 32
4911 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
4912 @item @var{branch_output} ... @option{enable} or @option{disable}
4916 @deffn Command {etm trigger_percent} percent
4917 @emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
4920 @subsection ETM Trace Operation
4922 After setting up the ETM, you can use it to collect data.
4923 That data can be exported to files for later analysis.
4924 It can also be parsed with OpenOCD, for basic sanity checking.
4926 To configure what is being traced, you will need to write
4927 various trace registers using @command{reg ETM_*} commands.
4928 For the definitions of these registers, read ARM publication
4929 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
4930 Be aware that most of the relevant registers are write-only,
4931 and that ETM resources are limited. There are only a handful
4932 of address comparators, data comparators, counters, and so on.
4934 Examples of scenarios you might arrange to trace include:
4937 @item Code flow within a function, @emph{excluding} subroutines
4938 it calls. Use address range comparators to enable tracing
4939 for instruction access within that function's body.
4940 @item Code flow within a function, @emph{including} subroutines
4941 it calls. Use the sequencer and address comparators to activate
4942 tracing on an ``entered function'' state, then deactivate it by
4943 exiting that state when the function's exit code is invoked.
4944 @item Code flow starting at the fifth invocation of a function,
4945 combining one of the above models with a counter.
4946 @item CPU data accesses to the registers for a particular device,
4947 using address range comparators and the ViewData logic.
4948 @item Such data accesses only during IRQ handling, combining the above
4949 model with sequencer triggers which on entry and exit to the IRQ handler.
4950 @item @emph{... more}
4953 At this writing, September 2009, there are no Tcl utility
4954 procedures to help set up any common tracing scenarios.
4956 @deffn Command {etm analyze}
4957 Reads trace data into memory, if it wasn't already present.
4958 Decodes and prints the data that was collected.
4961 @deffn Command {etm dump} filename
4962 Stores the captured trace data in @file{filename}.
4965 @deffn Command {etm image} filename [base_address] [type]
4966 Opens an image file.
4969 @deffn Command {etm load} filename
4970 Loads captured trace data from @file{filename}.
4973 @deffn Command {etm start}
4974 Starts trace data collection.
4977 @deffn Command {etm stop}
4978 Stops trace data collection.
4981 @anchor{Trace Port Drivers}
4982 @subsection Trace Port Drivers
4984 To use an ETM trace port it must be associated with a driver.
4986 @deffn {Trace Port Driver} dummy
4987 Use the @option{dummy} driver if you are configuring an ETM that's
4988 not connected to anything (on-chip ETB or off-chip trace connector).
4989 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
4990 any trace data collection.}
4991 @deffn {Config Command} {etm_dummy config} target
4992 Associates the ETM for @var{target} with a dummy driver.
4996 @deffn {Trace Port Driver} etb
4997 Use the @option{etb} driver if you are configuring an ETM
4998 to use on-chip ETB memory.
4999 @deffn {Config Command} {etb config} target etb_tap
5000 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
5001 You can see the ETB registers using the @command{reg} command.
5005 @deffn {Trace Port Driver} oocd_trace
5006 This driver isn't available unless OpenOCD was explicitly configured
5007 with the @option{--enable-oocd_trace} option. You probably don't want
5008 to configure it unless you've built the appropriate prototype hardware;
5009 it's @emph{proof-of-concept} software.
5011 Use the @option{oocd_trace} driver if you are configuring an ETM that's
5012 connected to an off-chip trace connector.
5014 @deffn {Config Command} {oocd_trace config} target tty
5015 Associates the ETM for @var{target} with a trace driver which
5016 collects data through the serial port @var{tty}.
5019 @deffn Command {oocd_trace resync}
5020 Re-synchronizes with the capture clock.
5023 @deffn Command {oocd_trace status}
5024 Reports whether the capture clock is locked or not.
5029 @section ARMv4 and ARMv5 Architecture
5033 These commands are specific to ARM architecture v4 and v5,
5034 including all ARM7 or ARM9 systems and Intel XScale.
5035 They are available in addition to other core-specific
5036 commands that may be available.
5038 @deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
5039 Displays the core_state, optionally changing it to process
5040 either @option{arm} or @option{thumb} instructions.
5041 The target may later be resumed in the currently set core_state.
5042 (Processors may also support the Jazelle state, but
5043 that is not currently supported in OpenOCD.)
5046 @deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
5048 Disassembles @var{count} instructions starting at @var{address}.
5049 If @var{count} is not specified, a single instruction is disassembled.
5050 If @option{thumb} is specified, or the low bit of the address is set,
5051 Thumb (16-bit) instructions are used;
5052 else ARM (32-bit) instructions are used.
5053 (Processors may also support the Jazelle state, but
5054 those instructions are not currently understood by OpenOCD.)
5057 @deffn Command {armv4_5 reg}
5058 Display a table of all banked core registers, fetching the current value from every
5059 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
5063 @subsection ARM7 and ARM9 specific commands
5067 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
5068 ARM9TDMI, ARM920T or ARM926EJ-S.
5069 They are available in addition to the ARMv4/5 commands,
5070 and any other core-specific commands that may be available.
5072 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
5073 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
5074 instead of breakpoints. This should be
5075 safe for all but ARM7TDMI--S cores (like Philips LPC).
5076 This feature is enabled by default on most ARM9 cores,
5077 including ARM9TDMI, ARM920T, and ARM926EJ-S.
5080 @deffn Command {arm7_9 dcc_downloads} (@option{enable}|@option{disable})
5082 Control the use of the debug communications channel (DCC) to write larger (>128 byte)
5083 amounts of memory. DCC downloads offer a huge speed increase, but might be
5084 unsafe, especially with targets running at very low speeds. This command was introduced
5085 with OpenOCD rev. 60, and requires a few bytes of working area.
5088 @anchor{arm7_9 fast_memory_access}
5089 @deffn Command {arm7_9 fast_memory_access} (@option{enable}|@option{disable})
5090 Enable or disable memory writes and reads that don't check completion of
5091 the operation. This provides a huge speed increase, especially with USB JTAG
5092 cables (FT2232), but might be unsafe if used with targets running at very low
5093 speeds, like the 32kHz startup clock of an AT91RM9200.
5096 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
5097 @emph{This is intended for use while debugging OpenOCD; you probably
5100 Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
5101 as used in the specified @var{mode}
5102 (where e.g. mode 16 is "user" and mode 19 is "supervisor";
5103 the M4..M0 bits of the PSR).
5104 Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
5105 Register 16 is the mode-specific SPSR,
5106 unless the specified mode is 0xffffffff (32-bit all-ones)
5107 in which case register 16 is the CPSR.
5108 The write goes directly to the CPU, bypassing the register cache.
5111 @deffn {Debug Command} {arm7_9 write_xpsr} word (@option{0}|@option{1})
5112 @emph{This is intended for use while debugging OpenOCD; you probably
5115 If the second parameter is zero, writes @var{word} to the
5116 Current Program Status register (CPSR).
5117 Else writes @var{word} to the current mode's Saved PSR (SPSR).
5118 In both cases, this bypasses the register cache.
5121 @deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (@option{0}|@option{1})
5122 @emph{This is intended for use while debugging OpenOCD; you probably
5125 Writes eight bits to the CPSR or SPSR,
5126 first rotating them by @math{2*rotate} bits,
5127 and bypassing the register cache.
5128 This has lower JTAG overhead than writing the entire CPSR or SPSR
5129 with @command{arm7_9 write_xpsr}.
5132 @subsection ARM720T specific commands
5135 These commands are available to ARM720T based CPUs,
5136 which are implementations of the ARMv4T architecture
5137 based on the ARM7TDMI-S integer core.
5138 They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
5140 @deffn Command {arm720t cp15} regnum [value]
5141 Display cp15 register @var{regnum};
5142 else if a @var{value} is provided, that value is written to that register.
5145 @deffn Command {arm720t mdw_phys} addr [count]
5146 @deffnx Command {arm720t mdh_phys} addr [count]
5147 @deffnx Command {arm720t mdb_phys} addr [count]
5148 Display contents of physical address @var{addr}, as
5149 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5150 or 8-bit bytes (@command{mdb_phys}).
5151 If @var{count} is specified, displays that many units.
5154 @deffn Command {arm720t mww_phys} addr word
5155 @deffnx Command {arm720t mwh_phys} addr halfword
5156 @deffnx Command {arm720t mwb_phys} addr byte
5157 Writes the specified @var{word} (32 bits),
5158 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5159 at the specified physical address @var{addr}.
5162 @deffn Command {arm720t virt2phys} va
5163 Translate a virtual address @var{va} to a physical address
5164 and display the result.
5167 @subsection ARM9 specific commands
5170 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
5172 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
5174 For historical reasons, one command shared by these cores starts
5175 with the @command{arm9tdmi} prefix.
5176 This is true even for ARM9E based processors, which implement the
5177 ARMv5TE architecture instead of ARMv4T.
5179 @c 9-june-2009: tried this on arm920t, it didn't work.
5180 @c no-params always lists nothing caught, and that's how it acts.
5182 @anchor{arm9tdmi vector_catch}
5183 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
5184 @cindex vector_catch
5185 Vector Catch hardware provides a sort of dedicated breakpoint
5186 for hardware events such as reset, interrupt, and abort.
5187 You can use this to conserve normal breakpoint resources,
5188 so long as you're not concerned with code that branches directly
5189 to those hardware vectors.
5191 This always finishes by listing the current configuration.
5192 If parameters are provided, it first reconfigures the
5193 vector catch hardware to intercept
5194 @option{all} of the hardware vectors,
5195 @option{none} of them,
5196 or a list with one or more of the following:
5197 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
5198 @option{irq} @option{fiq}.
5201 @subsection ARM920T specific commands
5204 These commands are available to ARM920T based CPUs,
5205 which are implementations of the ARMv4T architecture
5206 built using the ARM9TDMI integer core.
5207 They are available in addition to the ARMv4/5, ARM7/ARM9,
5208 and ARM9TDMI commands.
5210 @deffn Command {arm920t cache_info}
5211 Print information about the caches found. This allows to see whether your target
5212 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
5215 @deffn Command {arm920t cp15} regnum [value]
5216 Display cp15 register @var{regnum};
5217 else if a @var{value} is provided, that value is written to that register.
5220 @deffn Command {arm920t cp15i} opcode [value [address]]
5221 Interpreted access using cp15 @var{opcode}.
5222 If no @var{value} is provided, the result is displayed.
5223 Else if that value is written using the specified @var{address},
5224 or using zero if no other address is not provided.
5227 @deffn Command {arm920t mdw_phys} addr [count]
5228 @deffnx Command {arm920t mdh_phys} addr [count]
5229 @deffnx Command {arm920t mdb_phys} addr [count]
5230 Display contents of physical address @var{addr}, as
5231 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5232 or 8-bit bytes (@command{mdb_phys}).
5233 If @var{count} is specified, displays that many units.
5236 @deffn Command {arm920t mww_phys} addr word
5237 @deffnx Command {arm920t mwh_phys} addr halfword
5238 @deffnx Command {arm920t mwb_phys} addr byte
5239 Writes the specified @var{word} (32 bits),
5240 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5241 at the specified physical address @var{addr}.
5244 @deffn Command {arm920t read_cache} filename
5245 Dump the content of ICache and DCache to a file named @file{filename}.
5248 @deffn Command {arm920t read_mmu} filename
5249 Dump the content of the ITLB and DTLB to a file named @file{filename}.
5252 @deffn Command {arm920t virt2phys} va
5253 Translate a virtual address @var{va} to a physical address
5254 and display the result.
5257 @subsection ARM926ej-s specific commands
5260 These commands are available to ARM926ej-s based CPUs,
5261 which are implementations of the ARMv5TEJ architecture
5262 based on the ARM9EJ-S integer core.
5263 They are available in addition to the ARMv4/5, ARM7/ARM9,
5264 and ARM9TDMI commands.
5266 The Feroceon cores also support these commands, although
5267 they are not built from ARM926ej-s designs.
5269 @deffn Command {arm926ejs cache_info}
5270 Print information about the caches found.
5273 @deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
5274 Accesses cp15 register @var{regnum} using
5275 @var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
5276 If a @var{value} is provided, that value is written to that register.
5277 Else that register is read and displayed.
5280 @deffn Command {arm926ejs mdw_phys} addr [count]
5281 @deffnx Command {arm926ejs mdh_phys} addr [count]
5282 @deffnx Command {arm926ejs mdb_phys} addr [count]
5283 Display contents of physical address @var{addr}, as
5284 32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
5285 or 8-bit bytes (@command{mdb_phys}).
5286 If @var{count} is specified, displays that many units.
5289 @deffn Command {arm926ejs mww_phys} addr word
5290 @deffnx Command {arm926ejs mwh_phys} addr halfword
5291 @deffnx Command {arm926ejs mwb_phys} addr byte
5292 Writes the specified @var{word} (32 bits),
5293 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5294 at the specified physical address @var{addr}.
5297 @deffn Command {arm926ejs virt2phys} va
5298 Translate a virtual address @var{va} to a physical address
5299 and display the result.
5302 @subsection ARM966E specific commands
5305 These commands are available to ARM966 based CPUs,
5306 which are implementations of the ARMv5TE architecture.
5307 They are available in addition to the ARMv4/5, ARM7/ARM9,
5308 and ARM9TDMI commands.
5310 @deffn Command {arm966e cp15} regnum [value]
5311 Display cp15 register @var{regnum};
5312 else if a @var{value} is provided, that value is written to that register.
5315 @subsection XScale specific commands
5318 Some notes about the debug implementation on the XScale CPUs:
5320 The XScale CPU provides a special debug-only mini-instruction cache
5321 (mini-IC) in which exception vectors and target-resident debug handler
5322 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
5323 must point vector 0 (the reset vector) to the entry of the debug
5324 handler. However, this means that the complete first cacheline in the
5325 mini-IC is marked valid, which makes the CPU fetch all exception
5326 handlers from the mini-IC, ignoring the code in RAM.
5328 OpenOCD currently does not sync the mini-IC entries with the RAM
5329 contents (which would fail anyway while the target is running), so
5330 the user must provide appropriate values using the @code{xscale
5331 vector_table} command.
5333 It is recommended to place a pc-relative indirect branch in the vector
5334 table, and put the branch destination somewhere in memory. Doing so
5335 makes sure the code in the vector table stays constant regardless of
5336 code layout in memory:
5339 ldr pc,[pc,#0x100-8]
5340 ldr pc,[pc,#0x100-8]
5341 ldr pc,[pc,#0x100-8]
5342 ldr pc,[pc,#0x100-8]
5343 ldr pc,[pc,#0x100-8]
5344 ldr pc,[pc,#0x100-8]
5345 ldr pc,[pc,#0x100-8]
5346 ldr pc,[pc,#0x100-8]
5348 .long real_reset_vector
5349 .long real_ui_handler
5350 .long real_swi_handler
5352 .long real_data_abort
5353 .long 0 /* unused */
5354 .long real_irq_handler
5355 .long real_fiq_handler
5358 The debug handler must be placed somewhere in the address space using
5359 the @code{xscale debug_handler} command. The allowed locations for the
5360 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
5361 0xfffff800). The default value is 0xfe000800.
5364 These commands are available to XScale based CPUs,
5365 which are implementations of the ARMv5TE architecture.
5367 @deffn Command {xscale analyze_trace}
5368 Displays the contents of the trace buffer.
5371 @deffn Command {xscale cache_clean_address} address
5372 Changes the address used when cleaning the data cache.
5375 @deffn Command {xscale cache_info}
5376 Displays information about the CPU caches.
5379 @deffn Command {xscale cp15} regnum [value]
5380 Display cp15 register @var{regnum};
5381 else if a @var{value} is provided, that value is written to that register.
5384 @deffn Command {xscale debug_handler} target address
5385 Changes the address used for the specified target's debug handler.
5388 @deffn Command {xscale dcache} (@option{enable}|@option{disable})
5389 Enables or disable the CPU's data cache.
5392 @deffn Command {xscale dump_trace} filename
5393 Dumps the raw contents of the trace buffer to @file{filename}.
5396 @deffn Command {xscale icache} (@option{enable}|@option{disable})
5397 Enables or disable the CPU's instruction cache.
5400 @deffn Command {xscale mmu} (@option{enable}|@option{disable})
5401 Enables or disable the CPU's memory management unit.
5404 @deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
5405 Enables or disables the trace buffer,
5406 and controls how it is emptied.
5409 @deffn Command {xscale trace_image} filename [offset [type]]
5410 Opens a trace image from @file{filename}, optionally rebasing
5411 its segment addresses by @var{offset}.
5412 The image @var{type} may be one of
5413 @option{bin} (binary), @option{ihex} (Intel hex),
5414 @option{elf} (ELF file), @option{s19} (Motorola s19),
5415 @option{mem}, or @option{builder}.
5418 @anchor{xscale vector_catch}
5419 @deffn Command {xscale vector_catch} [mask]
5420 @cindex vector_catch
5421 Display a bitmask showing the hardware vectors to catch.
5422 If the optional parameter is provided, first set the bitmask to that value.
5424 The mask bits correspond with bit 16..23 in the DCSR:
5427 0x02 Trap Undefined Instructions
5428 0x04 Trap Software Interrupt
5429 0x08 Trap Prefetch Abort
5430 0x10 Trap Data Abort
5437 @anchor{xscale vector_table}
5438 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
5439 @cindex vector_table
5441 Set an entry in the mini-IC vector table. There are two tables: one for
5442 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
5443 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
5444 points to the debug handler entry and can not be overwritten.
5445 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
5447 Without arguments, the current settings are displayed.
5451 @section ARMv6 Architecture
5454 @subsection ARM11 specific commands
5457 @deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
5458 Write @var{value} to a coprocessor @var{pX} register
5459 passing parameters @var{CRn},
5460 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5461 and the MCR instruction.
5462 (The difference beween this and the MCR2 instruction is
5463 one bit in the encoding, effecively a fifth parameter.)
5466 @deffn Command {arm11 memwrite burst} [value]
5467 Displays the value of the memwrite burst-enable flag,
5468 which is enabled by default.
5469 If @var{value} is defined, first assigns that.
5472 @deffn Command {arm11 memwrite error_fatal} [value]
5473 Displays the value of the memwrite error_fatal flag,
5474 which is enabled by default.
5475 If @var{value} is defined, first assigns that.
5478 @deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
5479 Read a coprocessor @var{pX} register passing parameters @var{CRn},
5480 @var{CRm}, opcodes @var{opc1} and @var{opc2},
5481 and the MRC instruction.
5482 (The difference beween this and the MRC2 instruction is
5483 one bit in the encoding, effecively a fifth parameter.)
5484 Displays the result.
5487 @deffn Command {arm11 no_increment} [value]
5488 Displays the value of the flag controlling whether
5489 some read or write operations increment the pointer
5490 (the default behavior) or not (acting like a FIFO).
5491 If @var{value} is defined, first assigns that.
5494 @deffn Command {arm11 step_irq_enable} [value]
5495 Displays the value of the flag controlling whether
5496 IRQs are enabled during single stepping;
5497 they is disabled by default.
5498 If @var{value} is defined, first assigns that.
5501 @section ARMv7 Architecture
5504 @subsection ARMv7 Debug Access Port (DAP) specific commands
5505 @cindex Debug Access Port
5507 These commands are specific to ARM architecture v7 Debug Access Port (DAP),
5508 included on cortex-m3 and cortex-a8 systems.
5509 They are available in addition to other core-specific commands that may be available.
5511 @deffn Command {dap info} [num]
5512 Displays dap info for ap @var{num}, defaulting to the currently selected AP.
5515 @deffn Command {dap apsel} [num]
5516 Select AP @var{num}, defaulting to 0.
5519 @deffn Command {dap apid} [num]
5520 Displays id register from AP @var{num},
5521 defaulting to the currently selected AP.
5524 @deffn Command {dap baseaddr} [num]
5525 Displays debug base address from AP @var{num},
5526 defaulting to the currently selected AP.
5529 @deffn Command {dap memaccess} [value]
5530 Displays the number of extra tck for mem-ap memory bus access [0-255].
5531 If @var{value} is defined, first assigns that.
5534 @subsection ARMv7-A specific commands
5537 @deffn Command {armv7a disassemble} address [count [@option{thumb}]]
5539 Disassembles @var{count} instructions starting at @var{address}.
5540 If @var{count} is not specified, a single instruction is disassembled.
5541 If @option{thumb} is specified, or the low bit of the address is set,
5542 Thumb2 (mixed 16/32-bit) instructions are used;
5543 else ARM (32-bit) instructions are used.
5544 With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
5545 ThumbEE disassembly currently has no explicit support.
5546 (Processors may also support the Jazelle state, but
5547 those instructions are not currently understood by OpenOCD.)
5551 @subsection Cortex-M3 specific commands
5554 @deffn Command {cortex_m3 disassemble} address [count]
5556 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
5557 If @var{count} is not specified, a single instruction is disassembled.
5560 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
5561 Control masking (disabling) interrupts during target step/resume.
5564 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
5565 @cindex vector_catch
5566 Vector Catch hardware provides dedicated breakpoints
5567 for certain hardware events.
5569 Parameters request interception of
5570 @option{all} of these hardware event vectors,
5571 @option{none} of them,
5572 or one or more of the following:
5573 @option{hard_err} for a HardFault exception;
5574 @option{mm_err} for a MemManage exception;
5575 @option{bus_err} for a BusFault exception;
5578 @option{chk_err}, or
5579 @option{nocp_err} for various UsageFault exceptions; or
5581 If NVIC setup code does not enable them,
5582 MemManage, BusFault, and UsageFault exceptions
5583 are mapped to HardFault.
5584 UsageFault checks for
5585 divide-by-zero and unaligned access
5586 must also be explicitly enabled.
5588 This finishes by listing the current vector catch configuration.
5591 @anchor{Software Debug Messages and Tracing}
5592 @section Software Debug Messages and Tracing
5593 @cindex Linux-ARM DCC support
5597 OpenOCD can process certain requests from target software. Currently
5598 @command{target_request debugmsgs}
5599 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
5600 These messages are received as part of target polling, so
5601 you need to have @command{poll on} active to receive them.
5602 They are intrusive in that they will affect program execution
5603 times. If that is a problem, @pxref{ARM Hardware Tracing}.
5605 See @file{libdcc} in the contrib dir for more details.
5606 In addition to sending strings, characters, and
5607 arrays of various size integers from the target,
5608 @file{libdcc} also exports a software trace point mechanism.
5609 The target being debugged may
5610 issue trace messages which include a 24-bit @dfn{trace point} number.
5611 Trace point support includes two distinct mechanisms,
5612 each supported by a command:
5615 @item @emph{History} ... A circular buffer of trace points
5616 can be set up, and then displayed at any time.
5617 This tracks where code has been, which can be invaluable in
5618 finding out how some fault was triggered.
5620 The buffer may overflow, since it collects records continuously.
5621 It may be useful to use some of the 24 bits to represent a
5622 particular event, and other bits to hold data.
5624 @item @emph{Counting} ... An array of counters can be set up,
5625 and then displayed at any time.
5626 This can help establish code coverage and identify hot spots.
5628 The array of counters is directly indexed by the trace point
5629 number, so trace points with higher numbers are not counted.
5632 Linux-ARM kernels have a ``Kernel low-level debugging
5633 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
5634 depends on CONFIG_DEBUG_LL) which uses this mechanism to
5635 deliver messages before a serial console can be activated.
5636 This is not the same format used by @file{libdcc}.
5637 Other software, such as the U-Boot boot loader, sometimes
5638 does the same thing.
5640 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
5641 Displays current handling of target DCC message requests.
5642 These messages may be sent to the debugger while the target is running.
5643 The optional @option{enable} and @option{charmsg} parameters
5644 both enable the messages, while @option{disable} disables them.
5646 With @option{charmsg} the DCC words each contain one character,
5647 as used by Linux with CONFIG_DEBUG_ICEDCC;
5648 otherwise the libdcc format is used.
5651 @deffn Command {trace history} [@option{clear}|count]
5652 With no parameter, displays all the trace points that have triggered
5653 in the order they triggered.
5654 With the parameter @option{clear}, erases all current trace history records.
5655 With a @var{count} parameter, allocates space for that many
5659 @deffn Command {trace point} [@option{clear}|identifier]
5660 With no parameter, displays all trace point identifiers and how many times
5661 they have been triggered.
5662 With the parameter @option{clear}, erases all current trace point counters.
5663 With a numeric @var{identifier} parameter, creates a new a trace point counter
5664 and associates it with that identifier.
5666 @emph{Important:} The identifier and the trace point number
5667 are not related except by this command.
5668 These trace point numbers always start at zero (from server startup,
5669 or after @command{trace point clear}) and count up from there.
5674 @chapter JTAG Commands
5675 @cindex JTAG Commands
5676 Most general purpose JTAG commands have been presented earlier.
5677 (@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
5678 Lower level JTAG commands, as presented here,
5679 may be needed to work with targets which require special
5680 attention during operations such as reset or initialization.
5682 To use these commands you will need to understand some
5683 of the basics of JTAG, including:
5686 @item A JTAG scan chain consists of a sequence of individual TAP
5687 devices such as a CPUs.
5688 @item Control operations involve moving each TAP through the same
5689 standard state machine (in parallel)
5690 using their shared TMS and clock signals.
5691 @item Data transfer involves shifting data through the chain of
5692 instruction or data registers of each TAP, writing new register values
5693 while the reading previous ones.
5694 @item Data register sizes are a function of the instruction active in
5695 a given TAP, while instruction register sizes are fixed for each TAP.
5696 All TAPs support a BYPASS instruction with a single bit data register.
5697 @item The way OpenOCD differentiates between TAP devices is by
5698 shifting different instructions into (and out of) their instruction
5702 @section Low Level JTAG Commands
5704 These commands are used by developers who need to access
5705 JTAG instruction or data registers, possibly controlling
5706 the order of TAP state transitions.
5707 If you're not debugging OpenOCD internals, or bringing up a
5708 new JTAG adapter or a new type of TAP device (like a CPU or
5709 JTAG router), you probably won't need to use these commands.
5711 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
5712 Loads the data register of @var{tap} with a series of bit fields
5713 that specify the entire register.
5714 Each field is @var{numbits} bits long with
5715 a numeric @var{value} (hexadecimal encouraged).
5716 The return value holds the original value of each
5719 For example, a 38 bit number might be specified as one
5720 field of 32 bits then one of 6 bits.
5721 @emph{For portability, never pass fields which are more
5722 than 32 bits long. Many OpenOCD implementations do not
5723 support 64-bit (or larger) integer values.}
5725 All TAPs other than @var{tap} must be in BYPASS mode.
5726 The single bit in their data registers does not matter.
5728 When @var{tap_state} is specified, the JTAG state machine is left
5730 For example @sc{drpause} might be specified, so that more
5731 instructions can be issued before re-entering the @sc{run/idle} state.
5732 If the end state is not specified, the @sc{run/idle} state is entered.
5735 OpenOCD does not record information about data register lengths,
5736 so @emph{it is important that you get the bit field lengths right}.
5737 Remember that different JTAG instructions refer to different
5738 data registers, which may have different lengths.
5739 Moreover, those lengths may not be fixed;
5740 the SCAN_N instruction can change the length of
5741 the register accessed by the INTEST instruction
5742 (by connecting a different scan chain).
5746 @deffn Command {flush_count}
5747 Returns the number of times the JTAG queue has been flushed.
5748 This may be used for performance tuning.
5750 For example, flushing a queue over USB involves a
5751 minimum latency, often several milliseconds, which does
5752 not change with the amount of data which is written.
5753 You may be able to identify performance problems by finding
5754 tasks which waste bandwidth by flushing small transfers too often,
5755 instead of batching them into larger operations.
5758 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
5759 For each @var{tap} listed, loads the instruction register
5760 with its associated numeric @var{instruction}.
5761 (The number of bits in that instruction may be displayed
5762 using the @command{scan_chain} command.)
5763 For other TAPs, a BYPASS instruction is loaded.
5765 When @var{tap_state} is specified, the JTAG state machine is left
5767 For example @sc{irpause} might be specified, so the data register
5768 can be loaded before re-entering the @sc{run/idle} state.
5769 If the end state is not specified, the @sc{run/idle} state is entered.
5772 OpenOCD currently supports only a single field for instruction
5773 register values, unlike data register values.
5774 For TAPs where the instruction register length is more than 32 bits,
5775 portable scripts currently must issue only BYPASS instructions.
5779 @deffn Command {jtag_reset} trst srst
5780 Set values of reset signals.
5781 The @var{trst} and @var{srst} parameter values may be
5782 @option{0}, indicating that reset is inactive (pulled or driven high),
5783 or @option{1}, indicating it is active (pulled or driven low).
5784 The @command{reset_config} command should already have been used
5785 to configure how the board and JTAG adapter treat these two
5786 signals, and to say if either signal is even present.
5787 @xref{Reset Configuration}.
5790 @deffn Command {runtest} @var{num_cycles}
5791 Move to the @sc{run/idle} state, and execute at least
5792 @var{num_cycles} of the JTAG clock (TCK).
5793 Instructions often need some time
5794 to execute before they take effect.
5797 @c tms_sequence (short|long)
5798 @c ... temporary, debug-only, probably gone before 0.2 ships
5800 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
5801 Verify values captured during @sc{ircapture} and returned
5802 during IR scans. Default is enabled, but this can be
5803 overridden by @command{verify_jtag}.
5806 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
5807 Enables verification of DR and IR scans, to help detect
5808 programming errors. For IR scans, @command{verify_ircapture}
5809 must also be enabled.
5813 @section TAP state names
5814 @cindex TAP state names
5816 The @var{tap_state} names used by OpenOCD in the @command{drscan},
5817 and @command{irscan} commands are:
5820 @item @b{RESET} ... should act as if TRST were active
5821 @item @b{RUN/IDLE} ... don't assume this always means IDLE
5824 @item @b{DRSHIFT} ... TDI/TDO shifting through the data register
5826 @item @b{DRPAUSE} ... data register ready for update or more shifting
5831 @item @b{IRSHIFT} ... TDI/TDO shifting through the instruction register
5833 @item @b{IRPAUSE} ... instruction register ready for update or more shifting
5838 Note that only six of those states are fully ``stable'' in the
5839 face of TMS fixed (low except for @sc{reset})
5840 and a free-running JTAG clock. For all the
5841 others, the next TCK transition changes to a new state.
5844 @item From @sc{drshift} and @sc{irshift}, clock transitions will
5845 produce side effects by changing register contents. The values
5846 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
5847 may not be as expected.
5848 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
5849 choices after @command{drscan} or @command{irscan} commands,
5850 since they are free of JTAG side effects.
5851 However, @sc{run/idle} may have side effects that appear at other
5852 levels, such as advancing the ARM9E-S instruction pipeline.
5853 Consult the documentation for the TAP(s) you are working with.
5856 @node Boundary Scan Commands
5857 @chapter Boundary Scan Commands
5859 One of the original purposes of JTAG was to support
5860 boundary scan based hardware testing.
5861 Although its primary focus is to support On-Chip Debugging,
5862 OpenOCD also includes some boundary scan commands.
5864 @section SVF: Serial Vector Format
5865 @cindex Serial Vector Format
5868 The Serial Vector Format, better known as @dfn{SVF}, is a
5869 way to represent JTAG test patterns in text files.
5870 OpenOCD supports running such test files.
5872 @deffn Command {svf} filename [@option{quiet}]
5873 This issues a JTAG reset (Test-Logic-Reset) and then
5874 runs the SVF script from @file{filename}.
5875 Unless the @option{quiet} option is specified,
5876 each command is logged before it is executed.
5879 @section XSVF: Xilinx Serial Vector Format
5880 @cindex Xilinx Serial Vector Format
5883 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
5884 binary representation of SVF which is optimized for use with
5886 OpenOCD supports running such test files.
5888 @quotation Important
5889 Not all XSVF commands are supported.
5892 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
5893 This issues a JTAG reset (Test-Logic-Reset) and then
5894 runs the XSVF script from @file{filename}.
5895 When a @var{tapname} is specified, the commands are directed at
5897 When @option{virt2} is specified, the @sc{xruntest} command counts
5898 are interpreted as TCK cycles instead of microseconds.
5899 Unless the @option{quiet} option is specified,
5900 messages are logged for comments and some retries.
5906 If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
5907 be used to access files on PCs (either the developer's PC or some other PC).
5909 The way this works on the ZY1000 is to prefix a filename by
5910 "/tftp/ip/" and append the TFTP path on the TFTP
5911 server (tftpd). For example,
5914 load_image /tftp/10.0.0.96/c:\temp\abc.elf
5917 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
5918 if the file was hosted on the embedded host.
5920 In order to achieve decent performance, you must choose a TFTP server
5921 that supports a packet size bigger than the default packet size (512 bytes). There
5922 are numerous TFTP servers out there (free and commercial) and you will have to do
5923 a bit of googling to find something that fits your requirements.
5925 @node GDB and OpenOCD
5926 @chapter GDB and OpenOCD
5928 OpenOCD complies with the remote gdbserver protocol, and as such can be used
5929 to debug remote targets.
5931 @anchor{Connecting to GDB}
5932 @section Connecting to GDB
5933 @cindex Connecting to GDB
5934 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
5935 instance GDB 6.3 has a known bug that produces bogus memory access
5936 errors, which has since been fixed: look up 1836 in
5937 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
5939 OpenOCD can communicate with GDB in two ways:
5943 A socket (TCP/IP) connection is typically started as follows:
5945 target remote localhost:3333
5947 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
5949 A pipe connection is typically started as follows:
5951 target remote | openocd --pipe
5953 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
5954 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
5958 To list the available OpenOCD commands type @command{monitor help} on the
5961 OpenOCD supports the gdb @option{qSupported} packet, this enables information
5962 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
5963 packet size and the device's memory map.
5965 Previous versions of OpenOCD required the following GDB options to increase
5966 the packet size and speed up GDB communication:
5968 set remote memory-write-packet-size 1024
5969 set remote memory-write-packet-size fixed
5970 set remote memory-read-packet-size 1024
5971 set remote memory-read-packet-size fixed
5973 This is now handled in the @option{qSupported} PacketSize and should not be required.
5975 @section Programming using GDB
5976 @cindex Programming using GDB
5978 By default the target memory map is sent to GDB. This can be disabled by
5979 the following OpenOCD configuration option:
5981 gdb_memory_map disable
5983 For this to function correctly a valid flash configuration must also be set
5984 in OpenOCD. For faster performance you should also configure a valid
5987 Informing GDB of the memory map of the target will enable GDB to protect any
5988 flash areas of the target and use hardware breakpoints by default. This means
5989 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
5990 using a memory map. @xref{gdb_breakpoint_override}.
5992 To view the configured memory map in GDB, use the GDB command @option{info mem}
5993 All other unassigned addresses within GDB are treated as RAM.
5995 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
5996 This can be changed to the old behaviour by using the following GDB command
5998 set mem inaccessible-by-default off
6001 If @command{gdb_flash_program enable} is also used, GDB will be able to
6002 program any flash memory using the vFlash interface.
6004 GDB will look at the target memory map when a load command is given, if any
6005 areas to be programmed lie within the target flash area the vFlash packets
6008 If the target needs configuring before GDB programming, an event
6009 script can be executed:
6011 $_TARGETNAME configure -event EVENTNAME BODY
6014 To verify any flash programming the GDB command @option{compare-sections}
6017 @node Tcl Scripting API
6018 @chapter Tcl Scripting API
6019 @cindex Tcl Scripting API
6023 The commands are stateless. E.g. the telnet command line has a concept
6024 of currently active target, the Tcl API proc's take this sort of state
6025 information as an argument to each proc.
6027 There are three main types of return values: single value, name value
6028 pair list and lists.
6030 Name value pair. The proc 'foo' below returns a name/value pair
6036 > set foo(you) Oyvind
6037 > set foo(mouse) Micky
6038 > set foo(duck) Donald
6046 me Duane you Oyvind mouse Micky duck Donald
6048 Thus, to get the names of the associative array is easy:
6050 foreach { name value } [set foo] {
6051 puts "Name: $name, Value: $value"
6055 Lists returned must be relatively small. Otherwise a range
6056 should be passed in to the proc in question.
6058 @section Internal low-level Commands
6060 By low-level, the intent is a human would not directly use these commands.
6062 Low-level commands are (should be) prefixed with "ocd_", e.g.
6063 @command{ocd_flash_banks}
6064 is the low level API upon which @command{flash banks} is implemented.
6067 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6069 Read memory and return as a Tcl array for script processing
6070 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
6072 Convert a Tcl array to memory locations and write the values
6073 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
6075 Return information about the flash banks
6078 OpenOCD commands can consist of two words, e.g. "flash banks". The
6079 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
6080 called "flash_banks".
6082 @section OpenOCD specific Global Variables
6086 Real Tcl has ::tcl_platform(), and platform::identify, and many other
6087 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
6088 holds one of the following values:
6091 @item @b{winxx} Built using Microsoft Visual Studio
6092 @item @b{linux} Linux is the underlying operating sytem
6093 @item @b{darwin} Darwin (mac-os) is the underlying operating sytem.
6094 @item @b{cygwin} Running under Cygwin
6095 @item @b{mingw32} Running under MingW32
6096 @item @b{other} Unknown, none of the above.
6099 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
6102 We should add support for a variable like Tcl variable
6103 @code{tcl_platform(platform)}, it should be called
6104 @code{jim_platform} (because it
6105 is jim, not real tcl).
6109 @chapter Deprecated/Removed Commands
6110 @cindex Deprecated/Removed Commands
6111 Certain OpenOCD commands have been deprecated or
6112 removed during the various revisions.
6114 Upgrade your scripts as soon as possible.
6115 These descriptions for old commands may be removed
6116 a year after the command itself was removed.
6117 This means that in January 2010 this chapter may
6118 become much shorter.
6121 @item @b{arm7_9 fast_writes}
6122 @cindex arm7_9 fast_writes
6123 @*Use @command{arm7_9 fast_memory_access} instead.
6124 @xref{arm7_9 fast_memory_access}.
6127 @*An buggy old command that would not really work since background polling would wipe out the global endstate
6128 @item @b{arm7_9 force_hw_bkpts}
6129 @*Use @command{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
6130 for flash if the GDB memory map has been set up(default when flash is declared in
6131 target configuration). @xref{gdb_breakpoint_override}.
6132 @item @b{arm7_9 sw_bkpts}
6133 @*On by default. @xref{gdb_breakpoint_override}.
6134 @item @b{daemon_startup}
6135 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
6136 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
6137 and @option{target cortex_m3 little reset_halt 0}.
6138 @item @b{dump_binary}
6139 @*use @option{dump_image} command with same args. @xref{dump_image}.
6140 @item @b{flash erase}
6141 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
6142 @item @b{flash write}
6143 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6144 @item @b{flash write_binary}
6145 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
6146 @item @b{flash auto_erase}
6147 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
6149 @item @b{jtag_device}
6150 @*use the @command{jtag newtap} command, converting from positional syntax
6151 to named prefixes, and naming the TAP.
6153 Note that if you try to use the old command, a message will tell you the
6154 right new command to use; and that the fourth parameter in the old syntax
6155 was never actually used.
6157 OLD: jtag_device 8 0x01 0xe3 0xfe
6158 NEW: jtag newtap CHIPNAME TAPNAME \
6159 -irlen 8 -ircapture 0x01 -irmask 0xe3
6162 @item @b{jtag_speed} value
6163 @*@xref{JTAG Speed}.
6164 Usually, a value of zero means maximum
6165 speed. The actual effect of this option depends on the JTAG interface used.
6167 @item wiggler: maximum speed / @var{number}
6168 @item ft2232: 6MHz / (@var{number}+1)
6169 @item amt jtagaccel: 8 / 2**@var{number}
6170 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
6171 @item rlink: 24MHz / @var{number}, but only for certain values of @var{number}
6172 @comment end speed list.
6175 @item @b{load_binary}
6176 @*use @option{load_image} command with same args. @xref{load_image}.
6177 @item @b{run_and_halt_time}
6178 @*This command has been removed for simpler reset behaviour, it can be simulated with the
6185 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
6186 @*use the create subcommand of @option{target}.
6187 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
6188 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
6189 @item @b{working_area}
6190 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
6198 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
6200 @cindex adaptive clocking
6203 In digital circuit design it is often refered to as ``clock
6204 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
6205 operating at some speed, your target is operating at another. The two
6206 clocks are not synchronised, they are ``asynchronous''
6208 In order for the two to work together they must be synchronised. Otherwise
6209 the two systems will get out of sync with each other and nothing will
6210 work. There are 2 basic options:
6213 Use a special circuit.
6215 One clock must be some multiple slower than the other.
6218 @b{Does this really matter?} For some chips and some situations, this
6219 is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
6220 Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
6221 program/enable the oscillators and eventually the main clock. It is in
6222 those critical times you must slow the JTAG clock to sometimes 1 to
6225 Imagine debugging a 500MHz ARM926 hand held battery powered device
6226 that ``deep sleeps'' at 32kHz between every keystroke. It can be
6229 @b{Solution #1 - A special circuit}
6231 In order to make use of this, your JTAG dongle must support the RTCK
6232 feature. Not all dongles support this - keep reading!
6234 The RTCK signal often found in some ARM chips is used to help with
6235 this problem. ARM has a good description of the problem described at
6236 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
6237 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
6238 work? / how does adaptive clocking work?''.
6240 The nice thing about adaptive clocking is that ``battery powered hand
6241 held device example'' - the adaptiveness works perfectly all the
6242 time. One can set a break point or halt the system in the deep power
6243 down code, slow step out until the system speeds up.
6245 Note that adaptive clocking may also need to work at the board level,
6246 when a board-level scan chain has multiple chips.
6247 Parallel clock voting schemes are good way to implement this,
6248 both within and between chips, and can easily be implemented
6250 It's not difficult to have logic fan a module's input TCK signal out
6251 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
6252 back with the right polarity before changing the output RTCK signal.
6253 Texas Instruments makes some clock voting logic available
6254 for free (with no support) in VHDL form; see
6255 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
6257 @b{Solution #2 - Always works - but may be slower}
6259 Often this is a perfectly acceptable solution.
6261 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
6262 the target clock speed. But what that ``magic division'' is varies
6263 depending on the chips on your board.
6264 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
6265 ARM11 cores use an 8:1 division.
6266 @b{Xilinx rule of thumb} is 1/12 the clock speed.
6268 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
6270 You can still debug the 'low power' situations - you just need to
6271 manually adjust the clock speed at every step. While painful and
6272 tedious, it is not always practical.
6274 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
6275 have a special debug mode in your application that does a ``high power
6276 sleep''. If you are careful - 98% of your problems can be debugged
6279 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
6280 operation in your idle loops even if you don't otherwise change the CPU
6282 That operation gates the CPU clock, and thus the JTAG clock; which
6283 prevents JTAG access. One consequence is not being able to @command{halt}
6284 cores which are executing that @emph{wait for interrupt} operation.
6286 To set the JTAG frequency use the command:
6294 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
6296 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
6297 around Windows filenames.
6310 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
6312 Make sure you have Cygwin installed, or at least a version of OpenOCD that
6313 claims to come with all the necessary DLLs. When using Cygwin, try launching
6314 OpenOCD from the Cygwin shell.
6316 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
6317 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
6318 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
6320 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
6321 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
6322 software breakpoints consume one of the two available hardware breakpoints.
6324 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
6326 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
6327 clock at the time you're programming the flash. If you've specified the crystal's
6328 frequency, make sure the PLL is disabled. If you've specified the full core speed
6329 (e.g. 60MHz), make sure the PLL is enabled.
6331 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
6332 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
6333 out while waiting for end of scan, rtck was disabled".
6335 Make sure your PC's parallel port operates in EPP mode. You might have to try several
6336 settings in your PC BIOS (ECP, EPP, and different versions of those).
6338 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
6339 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
6340 memory read caused data abort".
6342 The errors are non-fatal, and are the result of GDB trying to trace stack frames
6343 beyond the last valid frame. It might be possible to prevent this by setting up
6344 a proper "initial" stack frame, if you happen to know what exactly has to
6345 be done, feel free to add this here.
6347 @b{Simple:} In your startup code - push 8 registers of zeros onto the
6348 stack before calling main(). What GDB is doing is ``climbing'' the run
6349 time stack by reading various values on the stack using the standard
6350 call frame for the target. GDB keeps going - until one of 2 things
6351 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
6352 stackframes have been processed. By pushing zeros on the stack, GDB
6355 @b{Debugging Interrupt Service Routines} - In your ISR before you call
6356 your C code, do the same - artifically push some zeros onto the stack,
6357 remember to pop them off when the ISR is done.
6359 @b{Also note:} If you have a multi-threaded operating system, they
6360 often do not @b{in the intrest of saving memory} waste these few
6364 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
6365 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
6367 This warning doesn't indicate any serious problem, as long as you don't want to
6368 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
6369 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
6370 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
6371 independently. With this setup, it's not possible to halt the core right out of
6372 reset, everything else should work fine.
6374 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
6375 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
6376 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
6377 quit with an error message. Is there a stability issue with OpenOCD?
6379 No, this is not a stability issue concerning OpenOCD. Most users have solved
6380 this issue by simply using a self-powered USB hub, which they connect their
6381 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
6382 supply stable enough for the Amontec JTAGkey to be operated.
6384 @b{Laptops running on battery have this problem too...}
6386 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
6387 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
6388 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
6389 What does that mean and what might be the reason for this?
6391 First of all, the reason might be the USB power supply. Try using a self-powered
6392 hub instead of a direct connection to your computer. Secondly, the error code 4
6393 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
6394 chip ran into some sort of error - this points us to a USB problem.
6396 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
6397 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
6398 What does that mean and what might be the reason for this?
6400 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
6401 has closed the connection to OpenOCD. This might be a GDB issue.
6403 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
6404 are described, there is a parameter for specifying the clock frequency
6405 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
6406 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
6407 specified in kilohertz. However, I do have a quartz crystal of a
6408 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
6409 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
6412 No. The clock frequency specified here must be given as an integral number.
6413 However, this clock frequency is used by the In-Application-Programming (IAP)
6414 routines of the LPC2000 family only, which seems to be very tolerant concerning
6415 the given clock frequency, so a slight difference between the specified clock
6416 frequency and the actual clock frequency will not cause any trouble.
6418 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
6420 Well, yes and no. Commands can be given in arbitrary order, yet the
6421 devices listed for the JTAG scan chain must be given in the right
6422 order (jtag newdevice), with the device closest to the TDO-Pin being
6423 listed first. In general, whenever objects of the same type exist
6424 which require an index number, then these objects must be given in the
6425 right order (jtag newtap, targets and flash banks - a target
6426 references a jtag newtap and a flash bank references a target).
6428 You can use the ``scan_chain'' command to verify and display the tap order.
6430 Also, some commands can't execute until after @command{init} has been
6431 processed. Such commands include @command{nand probe} and everything
6432 else that needs to write to controller registers, perhaps for setting
6433 up DRAM and loading it with code.
6435 @anchor{FAQ TAP Order}
6436 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
6439 Yes; whenever you have more than one, you must declare them in
6440 the same order used by the hardware.
6442 Many newer devices have multiple JTAG TAPs. For example: ST
6443 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
6444 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
6445 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
6446 connected to the boundary scan TAP, which then connects to the
6447 Cortex-M3 TAP, which then connects to the TDO pin.
6449 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
6450 (2) The boundary scan TAP. If your board includes an additional JTAG
6451 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
6452 place it before or after the STM32 chip in the chain. For example:
6455 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
6456 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
6457 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
6458 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
6459 @item Xilinx TDO Pin -> OpenOCD TDO (input)
6462 The ``jtag device'' commands would thus be in the order shown below. Note:
6465 @item jtag newtap Xilinx tap -irlen ...
6466 @item jtag newtap stm32 cpu -irlen ...
6467 @item jtag newtap stm32 bs -irlen ...
6468 @item # Create the debug target and say where it is
6469 @item target create stm32.cpu -chain-position stm32.cpu ...
6473 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
6474 log file, I can see these error messages: Error: arm7_9_common.c:561
6475 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
6481 @node Tcl Crash Course
6482 @chapter Tcl Crash Course
6485 Not everyone knows Tcl - this is not intended to be a replacement for
6486 learning Tcl, the intent of this chapter is to give you some idea of
6487 how the Tcl scripts work.
6489 This chapter is written with two audiences in mind. (1) OpenOCD users
6490 who need to understand a bit more of how JIM-Tcl works so they can do
6491 something useful, and (2) those that want to add a new command to
6494 @section Tcl Rule #1
6495 There is a famous joke, it goes like this:
6497 @item Rule #1: The wife is always correct
6498 @item Rule #2: If you think otherwise, See Rule #1
6501 The Tcl equal is this:
6504 @item Rule #1: Everything is a string
6505 @item Rule #2: If you think otherwise, See Rule #1
6508 As in the famous joke, the consequences of Rule #1 are profound. Once
6509 you understand Rule #1, you will understand Tcl.
6511 @section Tcl Rule #1b
6512 There is a second pair of rules.
6514 @item Rule #1: Control flow does not exist. Only commands
6515 @* For example: the classic FOR loop or IF statement is not a control
6516 flow item, they are commands, there is no such thing as control flow
6518 @item Rule #2: If you think otherwise, See Rule #1
6519 @* Actually what happens is this: There are commands that by
6520 convention, act like control flow key words in other languages. One of
6521 those commands is the word ``for'', another command is ``if''.
6524 @section Per Rule #1 - All Results are strings
6525 Every Tcl command results in a string. The word ``result'' is used
6526 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
6527 Everything is a string}
6529 @section Tcl Quoting Operators
6530 In life of a Tcl script, there are two important periods of time, the
6531 difference is subtle.
6534 @item Evaluation Time
6537 The two key items here are how ``quoted things'' work in Tcl. Tcl has
6538 three primary quoting constructs, the [square-brackets] the
6539 @{curly-braces@} and ``double-quotes''
6541 By now you should know $VARIABLES always start with a $DOLLAR
6542 sign. BTW: To set a variable, you actually use the command ``set'', as
6543 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
6544 = 1'' statement, but without the equal sign.
6547 @item @b{[square-brackets]}
6548 @* @b{[square-brackets]} are command substitutions. It operates much
6549 like Unix Shell `back-ticks`. The result of a [square-bracket]
6550 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
6551 string}. These two statements are roughly identical:
6555 echo "The Date is: $X"
6558 puts "The Date is: $X"
6560 @item @b{``double-quoted-things''}
6561 @* @b{``double-quoted-things''} are just simply quoted
6562 text. $VARIABLES and [square-brackets] are expanded in place - the
6563 result however is exactly 1 string. @i{Remember Rule #1 - Everything
6567 puts "It is now \"[date]\", $x is in 1 hour"
6569 @item @b{@{Curly-Braces@}}
6570 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
6571 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
6572 'single-quote' operators in BASH shell scripts, with the added
6573 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
6574 nested 3 times@}@}@} NOTE: [date] is a bad example;
6575 at this writing, Jim/OpenOCD does not have a date command.
6578 @section Consequences of Rule 1/2/3/4
6580 The consequences of Rule 1 are profound.
6582 @subsection Tokenisation & Execution.
6584 Of course, whitespace, blank lines and #comment lines are handled in
6587 As a script is parsed, each (multi) line in the script file is
6588 tokenised and according to the quoting rules. After tokenisation, that
6589 line is immedatly executed.
6591 Multi line statements end with one or more ``still-open''
6592 @{curly-braces@} which - eventually - closes a few lines later.
6594 @subsection Command Execution
6596 Remember earlier: There are no ``control flow''
6597 statements in Tcl. Instead there are COMMANDS that simply act like
6598 control flow operators.
6600 Commands are executed like this:
6603 @item Parse the next line into (argc) and (argv[]).
6604 @item Look up (argv[0]) in a table and call its function.
6605 @item Repeat until End Of File.
6608 It sort of works like this:
6611 ReadAndParse( &argc, &argv );
6613 cmdPtr = LookupCommand( argv[0] );
6615 (*cmdPtr->Execute)( argc, argv );
6619 When the command ``proc'' is parsed (which creates a procedure
6620 function) it gets 3 parameters on the command line. @b{1} the name of
6621 the proc (function), @b{2} the list of parameters, and @b{3} the body
6622 of the function. Not the choice of words: LIST and BODY. The PROC
6623 command stores these items in a table somewhere so it can be found by
6626 @subsection The FOR command
6628 The most interesting command to look at is the FOR command. In Tcl,
6629 the FOR command is normally implemented in C. Remember, FOR is a
6630 command just like any other command.
6632 When the ascii text containing the FOR command is parsed, the parser
6633 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
6637 @item The ascii text 'for'
6638 @item The start text
6639 @item The test expression
6644 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
6645 Remember @i{Rule #1 - Everything is a string.} The key point is this:
6646 Often many of those parameters are in @{curly-braces@} - thus the
6647 variables inside are not expanded or replaced until later.
6649 Remember that every Tcl command looks like the classic ``main( argc,
6650 argv )'' function in C. In JimTCL - they actually look like this:
6654 MyCommand( Jim_Interp *interp,
6656 Jim_Obj * const *argvs );
6659 Real Tcl is nearly identical. Although the newer versions have
6660 introduced a byte-code parser and intepreter, but at the core, it
6661 still operates in the same basic way.
6663 @subsection FOR command implementation
6665 To understand Tcl it is perhaps most helpful to see the FOR
6666 command. Remember, it is a COMMAND not a control flow structure.
6668 In Tcl there are two underlying C helper functions.
6670 Remember Rule #1 - You are a string.
6672 The @b{first} helper parses and executes commands found in an ascii
6673 string. Commands can be seperated by semicolons, or newlines. While
6674 parsing, variables are expanded via the quoting rules.
6676 The @b{second} helper evaluates an ascii string as a numerical
6677 expression and returns a value.
6679 Here is an example of how the @b{FOR} command could be
6680 implemented. The pseudo code below does not show error handling.
6682 void Execute_AsciiString( void *interp, const char *string );
6684 int Evaluate_AsciiExpression( void *interp, const char *string );
6687 MyForCommand( void *interp,
6692 SetResult( interp, "WRONG number of parameters");
6696 // argv[0] = the ascii string just like C
6698 // Execute the start statement.
6699 Execute_AsciiString( interp, argv[1] );
6703 i = Evaluate_AsciiExpression(interp, argv[2]);
6708 Execute_AsciiString( interp, argv[3] );
6710 // Execute the LOOP part
6711 Execute_AsciiString( interp, argv[4] );
6715 SetResult( interp, "" );
6720 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
6721 in the same basic way.
6723 @section OpenOCD Tcl Usage
6725 @subsection source and find commands
6726 @b{Where:} In many configuration files
6727 @* Example: @b{ source [find FILENAME] }
6728 @*Remember the parsing rules
6730 @item The FIND command is in square brackets.
6731 @* The FIND command is executed with the parameter FILENAME. It should
6732 find the full path to the named file. The RESULT is a string, which is
6733 substituted on the orginal command line.
6734 @item The command source is executed with the resulting filename.
6735 @* SOURCE reads a file and executes as a script.
6737 @subsection format command
6738 @b{Where:} Generally occurs in numerous places.
6739 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
6745 puts [format "The answer: %d" [expr $x * $y]]
6748 @item The SET command creates 2 variables, X and Y.
6749 @item The double [nested] EXPR command performs math
6750 @* The EXPR command produces numerical result as a string.
6752 @item The format command is executed, producing a single string
6753 @* Refer to Rule #1.
6754 @item The PUTS command outputs the text.
6756 @subsection Body or Inlined Text
6757 @b{Where:} Various TARGET scripts.
6760 proc someproc @{@} @{
6761 ... multiple lines of stuff ...
6763 $_TARGETNAME configure -event FOO someproc
6764 #2 Good - no variables
6765 $_TARGETNAME confgure -event foo "this ; that;"
6766 #3 Good Curly Braces
6767 $_TARGETNAME configure -event FOO @{
6770 #4 DANGER DANGER DANGER
6771 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
6774 @item The $_TARGETNAME is an OpenOCD variable convention.
6775 @*@b{$_TARGETNAME} represents the last target created, the value changes
6776 each time a new target is created. Remember the parsing rules. When
6777 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
6778 the name of the target which happens to be a TARGET (object)
6780 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
6781 @*There are 4 examples:
6783 @item The TCLBODY is a simple string that happens to be a proc name
6784 @item The TCLBODY is several simple commands seperated by semicolons
6785 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
6786 @item The TCLBODY is a string with variables that get expanded.
6789 In the end, when the target event FOO occurs the TCLBODY is
6790 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
6791 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
6793 Remember the parsing rules. In case #3, @{curly-braces@} mean the
6794 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
6795 and the text is evaluated. In case #4, they are replaced before the
6796 ``Target Object Command'' is executed. This occurs at the same time
6797 $_TARGETNAME is replaced. In case #4 the date will never
6798 change. @{BTW: [date] is a bad example; at this writing,
6799 Jim/OpenOCD does not have a date command@}
6801 @subsection Global Variables
6802 @b{Where:} You might discover this when writing your own procs @* In
6803 simple terms: Inside a PROC, if you need to access a global variable
6804 you must say so. See also ``upvar''. Example:
6806 proc myproc @{ @} @{
6807 set y 0 #Local variable Y
6808 global x #Global variable X
6809 puts [format "X=%d, Y=%d" $x $y]
6812 @section Other Tcl Hacks
6813 @b{Dynamic variable creation}
6815 # Dynamically create a bunch of variables.
6816 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
6818 set vn [format "BIT%d" $x]
6822 set $vn [expr (1 << $x)]
6825 @b{Dynamic proc/command creation}
6827 # One "X" function - 5 uart functions.
6828 foreach who @{A B C D E@}
6829 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
6833 @node Target Library
6834 @chapter Target Library
6835 @cindex Target Library
6837 OpenOCD comes with a target configuration script library. These scripts can be
6838 used as-is or serve as a starting point.
6840 The target library is published together with the OpenOCD executable and
6841 the path to the target library is in the OpenOCD script search path.
6842 Similarly there are example scripts for configuring the JTAG interface.
6844 The command line below uses the example parport configuration script
6845 that ship with OpenOCD, then configures the str710.cfg target and
6846 finally issues the init and reset commands. The communication speed
6847 is set to 10kHz for reset and 8MHz for post reset.
6850 openocd -f interface/parport.cfg -f target/str710.cfg \
6851 -c "init" -c "reset"
6854 To list the target scripts available:
6857 $ ls /usr/local/lib/openocd/target
6859 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
6860 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
6861 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
6862 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
6867 @node OpenOCD Concept Index
6868 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
6869 @comment case issue with ``Index.html'' and ``index.html''
6870 @comment Occurs when creating ``--html --no-split'' output
6871 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
6872 @unnumbered OpenOCD Concept Index
6876 @node Command and Driver Index
6877 @unnumbered Command and Driver Index