contrib/loaders/flash/msp432/msp432p401x.h

   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions
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   9 *  Redistributions of source code must retain the above copyright
  10 *  notice, this list of conditions and the following disclaimer.
  11 *
  12 *  Redistributions in binary form must reproduce the above copyright
  13 *  notice, this list of conditions and the following disclaimer in the
  14 *  documentation and/or other materials provided with the
  15 *  distribution.
  16 *
  17 *  Neither the name of Texas Instruments Incorporated nor the names of
  18 *  its contributors may be used to endorse or promote products derived
  19 *  from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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  33 ******************************************************************************/
  34
  35 #ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
  36 #define OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
  37
  38 #include <stdint.h>
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define __MCU_HAS_FLCTL__ /* Module FLCTL is available */
  45
  46 /* Device and peripheral memory map */
  47 #define FLASH_BASE  ((uint32_t)0x00000000)     /* Flash memory start address */
  48 #define SRAM_BASE   ((uint32_t)0x20000000)     /* SRAM memory start address */
  49 #define PERIPH_BASE ((uint32_t)0x40000000)     /* Peripherals start address */
  50 #define CS_BASE     (PERIPH_BASE + 0x00010400) /* Address of module CS regs. */
  51 #define DIO_BASE    (PERIPH_BASE + 0x00004C00) /* Address of module DIO regs. */
  52
  53 /* Register map for Clock Signal peripheral (CS) */
  54 struct cs {
  55         volatile uint32_t KEY;  /* Key Register */
  56         volatile uint32_t CTL0; /* Control 0 Register */
  57         volatile uint32_t CTL1; /* Control 1 Register */
  58         volatile uint32_t CTL2; /* Control 2 Register */
  59         volatile uint32_t CTL3; /* Control 3 Register */
  60 };
  61
  62 /* Register map for DIO port (odd interrupt) */
  63 struct dio_port_odd_int {
  64         volatile uint8_t IN;  /* Port Input */
  65         uint8_t RESERVED0;
  66         volatile uint8_t OUT; /* Port Output */
  67 };
  68
  69 /* Register map for DIO port (even interrupt) */
  70 struct dio_port_even_int {
  71         uint8_t RESERVED0;
  72         volatile uint8_t IN;  /* Port Input */
  73         uint8_t RESERVED1;
  74         volatile uint8_t OUT; /* Port Output */
  75 };
  76
  77 /* Peripheral declarations */
  78 #define CS ((struct cs *) CS_BASE)
  79 #define P3 ((struct dio_port_odd_int *) (DIO_BASE + 0x0020))
  80 #define P6 ((struct dio_port_even_int *) (DIO_BASE + 0x0040))
  81
  82 /* Peripheral bit definitions */
  83
  84 /* DCORSEL Bit Mask */
  85 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
  86 /* Nominal DCO Frequency Range (MHz): 2 to 4 */
  87 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
  88 /* Nominal DCO Frequency Range (MHz): 16 to 32 */
  89 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
  90 /* CS control key value */
  91 #define CS_KEY_VAL ((uint32_t)0x0000695A)
  92
  93 /* Protects Sector 0 from program or erase */
  94 #define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001)
  95 /* Protects Sector 1 from program or erase */
  96 #define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002)
  97
  98 #ifdef __cplusplus
  99 }
 100 #endif
 101
 102 #endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H */