stm32f2x: Fix left shift of negative value

[openocd.git] / tcl / target / klx.cfg

diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 0df6612f708d93a9919e6feabf669f0765c784f3..7dd0404f96bd3cc633fac71c456298c4e2fd8aed 100644 (file)
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -1,5 +1,6 @@
 #
-# Freescale Kinetis KL series devices
+# NXP (former Freescale) Kinetis KL series devices
+# Also used for Cortex-M0+ equipped members of KVx and KE1xZ series
 #
 
 source [find target/swj-dp.tcl]
@@ -31,11 +32,13 @@ target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-set _FLASHNAME $_CHIPNAME.flash
+set _FLASHNAME $_CHIPNAME.pflash
 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
+kinetis create_banks
 
 # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 1MHz for VLPR mode.
+# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
+# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
 adapter_khz 1000
 
 reset_config srst_nogate
@@ -51,10 +54,9 @@ if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }
 
-# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 24MHz for run mode; Table 17 of Sub-Family Data
-# Sheet rev4 lists 25MHz as the maximum frequency.
-# Uncoment only if VLPR mode is not used
-#$_TARGETNAME configure -event reset-init {
-#   adapter_khz 24000
-#}
+# Disable watchdog not to disturb OpenOCD algorithms running on MCU
+# (e.g. armv7m_checksum_memory() in verify_image)
+# Flash driver also disables watchdog before FTFA flash programming.
+$_TARGETNAME configure -event reset-init {
+   kinetis disable_wdog
+}