0, 1, 96, NULL, 0, NULL, 0
};
+void armv7a_show_fault_registers(target_t *target)
+{
+ uint32_t dfsr, ifsr, dfar, ifar;
+
+ /* get pointers to arch-specific information */
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ armv7a_common_t *armv7a = armv4_5->arch_info;
+
+ armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr);
+ armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr);
+ armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
+ armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
+
+ LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ ", DFAR: %8.8" PRIx32, dfsr, dfar);
+ LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ ", IFAR: %8.8" PRIx32, ifsr, ifar);
+
+}
+
int armv7a_arch_state(struct target_s *target)
{
static const char *state[] =
state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+ if (armv4_5->core_mode == ARMV7A_MODE_ABT)
+ armv7a_show_fault_registers(target);
+
return ERROR_OK;
}
swjdp_common_t *swjdp = &armv7a->swjdp_info;
uint32_t apsel;
- apsel = swjdp->apsel;
- if (argc > 0)
- apsel = strtoul(args[0], NULL, 0);
+ switch (argc) {
+ case 0:
+ apsel = swjdp->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, args[0], apsel);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
return dap_info_command(cmd_ctx, swjdp, apsel);
}
thumb = 1;
/* FALL THROUGH */
case 2:
- count = strtoul(args[1], NULL, 0);
+ COMMAND_PARSE_NUMBER(int, args[1], count);
/* FALL THROUGH */
case 1:
- address = strtoul(args[0], NULL, 0);
+ COMMAND_PARSE_NUMBER(u32, args[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(cmd_ctx, "Disassemble as Thumb");