2 # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
3 # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
4 # the same Flash/RAM/MMIO address space.
7 source [find target/swj-dp.tcl]
12 if { [info exists CHIPNAME] } {
13 set _CHIPNAME $CHIPNAME
19 set TARGET $_CHIPNAME.cpu
21 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
23 # Is CM0 Debugging enabled ?
25 if { [info exists ENABLE_CM0] } {
26 set _ENABLE_CM0 $ENABLE_CM0
31 # Is CM4 Debugging enabled ?
33 if { [info exists ENABLE_CM4] } {
34 set _ENABLE_CM4 $ENABLE_CM4
39 global _WORKAREASIZE_CM0
40 if { [info exists WORKAREASIZE_CM0] } {
41 set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
43 set _WORKAREASIZE_CM0 0x4000
46 global _WORKAREASIZE_CM4
47 if { [info exists WORKAREASIZE_CM4] } {
48 set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
50 set _WORKAREASIZE_CM4 0x4000
53 global _WORKAREAADDR_CM0
54 if { [info exists WORKAREAADDR_CM0] } {
55 set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
57 set _WORKAREAADDR_CM0 0x08000000
60 global _WORKAREAADDR_CM4
61 if { [info exists WORKAREAADDR_CM4] } {
62 set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
64 set _WORKAREAADDR_CM4 0x08000000
67 proc init_reset { mode } {
76 # Utility to make 'reset halt' work as reset;halt on a target
77 # It does not prevent running code after reset
78 proc psoc6_deassert_post { target } {
79 # PSoC6 cleared AP registers including TAR during reset
80 # Force examine to synchronize OpenOCD target status
84 if { $RESET_MODE ne "run" } {
87 set st [$target curstate]
88 if { $st eq "reset" } {
89 # we assume running state follows
90 # if reset accidentally halts, waiting is useless
91 catch { $target arp_waitstate running 100 }
92 set st [$target curstate]
94 if { $st eq "running" } {
95 echo "$target: Ran after reset and before halt..."
101 if { $_ENABLE_CM0 } {
102 target create ${TARGET}.cm0 cortex_m -chain-position $TARGET -ap-num 1 -coreid 0
103 ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
105 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
106 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0
107 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
108 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
109 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
110 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
112 ${TARGET}.cm0 cortex_m reset_config sysresetreq
113 ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
116 if { $_ENABLE_CM4 } {
117 target create ${TARGET}.cm4 cortex_m -chain-position $TARGET -ap-num 2 -coreid 1
118 ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
120 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
121 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4
122 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
123 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
124 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
125 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
127 ${TARGET}.cm4 cortex_m reset_config vectreset
128 ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
131 if { $_ENABLE_CM0 } {
132 # Use CM0+ by default on dual-core devices
133 targets ${TARGET}.cm0