1 # SPDX-License-Identifier: GPL-2.0-or-later
3 source [find target/atheros_ar9344.cfg]
5 reset_config trst_only separate
7 proc ar9344_40mhz_pll_init {} {
8 # QCA_PLL_SRIF_CPU_DPLL2_REG
9 mww 0xb81161C4 0x13210f00
10 # QCA_PLL_SRIF_CPU_DPLL3_REG
11 mww 0xb81161C8 0x03000000
12 # QCA_PLL_SRIF_DDR_DPLL2_REG
13 mww 0xb8116244 0x13210f00
14 # QCA_PLL_SRIF_DDR_DPLL3_REG
15 mww 0xb8116248 0x03000000
16 # QCA_PLL_SRIF_BB_DPLL_BASE_REG
17 mww 0xb8116188 0x03000000
19 # QCA_PLL_CPU_DDR_CLK_CTRL_REG
20 mww 0xb8050008 0x0130001C
21 mww 0xb8050008 0x0130001C
22 mww 0xb8050008 0x0130001C
24 # QCA_PLL_CPU_PLL_CFG_REG
25 mww 0xb8050000 0x40021380
26 # QCA_PLL_DDR_PLL_CFG_REG
27 mww 0xb8050004 0x40815800
28 # QCA_PLL_CPU_DDR_CLK_CTRL_REG
29 mww 0xb8050008 0x0130801C
31 # QCA_PLL_SRIF_CPU_DPLL2_REG
32 mww 0xb81161C4 0x10810F00
33 mww 0xb81161C0 0x41C00000
34 # QCA_PLL_SRIF_CPU_DPLL2_REG
35 mww 0xb81161C4 0xD0810F00
36 # QCA_PLL_SRIF_CPU_DPLL3_REG
37 mww 0xb81161C8 0x03000000
38 # QCA_PLL_SRIF_CPU_DPLL2_REG
39 mww 0xb81161C4 0xD0800F00
41 # QCA_PLL_SRIF_CPU_DPLL3_REG
42 mww 0xb81161C8 0x03000000
43 # QCA_PLL_SRIF_CPU_DPLL3_REG
44 mww 0xb81161C8 0x43000000
45 # QCA_PLL_SRIF_CPU_DPLL3_REG
46 mww 0xb81161C8 0x030003E8
48 # QCA_PLL_SRIF_DDR_DPLL2_REG
49 mww 0xb8116244 0x10810F00
50 mww 0xb8116240 0x41680000
51 # QCA_PLL_SRIF_DDR_DPLL2_REG
52 mww 0xb8116244 0xD0810F00
53 # QCA_PLL_SRIF_DDR_DPLL3_REG
54 mww 0xb8116248 0x03000000
55 # QCA_PLL_SRIF_DDR_DPLL2_REG
56 mww 0xb8116244 0xD0800F00
58 # QCA_PLL_SRIF_DDR_DPLL3_REG
59 mww 0xb8116248 0x03000000
60 # QCA_PLL_SRIF_DDR_DPLL3_REG
61 mww 0xb8116248 0x43000000
62 # QCA_PLL_SRIF_DDR_DPLL3_REG
63 mww 0xb8116248 0x03000718
65 # QCA_PLL_CPU_DDR_CLK_CTRL_REG
66 mww 0xb8050008 0x01308018
67 mww 0xb8050008 0x01308010
68 mww 0xb8050008 0x01308000
70 # QCA_PLL_DDR_PLL_DITHER_REG
71 mww 0xb8050044 0x78180200
72 # QCA_PLL_CPU_PLL_DITHER_REG
73 mww 0xb8050048 0x41C00000
77 proc ar9344_ddr_init {} {
78 # QCA_DDR_CTRL_CFG_REG
80 # QCA_DDR_RD_DATA_THIS_CYCLE_REG
83 mww 0xb80000C4 0x74444444
86 # QCA_AHB_MASTER_TOUT_MAX_REG
87 mww 0xb80000CC 0xFFFFF
90 mww 0xb8000000 0xC7D48CD0
92 mww 0xb8000004 0x9DD0E6A8
94 # QCA_DDR_DDR2_CFG_REG
97 mww 0xb8000004 0x9DD0E6A8
110 mww 0xb8000008 0x0133
124 mww 0xb800000C 0x0382
128 mww 0xb800000C 0x0402
132 # QCA_DDR_REFRESH_REG
133 mww 0xb8000014 0x4270
135 # QCA_DDR_TAP_CTRL_0_REG
137 # QCA_DDR_TAP_CTRL_1_REG
139 # QCA_DDR_TAP_CTRL_2_REG
141 # QCA_DDR_TAP_CTRL_3_REG
145 $_TARGETNAME configure -event reset-init {
147 # mww 0xb806001c 0x1000000
148 ar9344_40mhz_pll_init
159 set ram_boot_address 0xa0000000
160 $_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
162 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0