2 # https://www.dptechnics.com/en/products/dpt-board-v1.html
4 # JTAG is a 5 pin array located close to main module in following order:
9 # 5. GND The GND is located near letter G of word JTAG on board.
11 # Two RST pins are connected to:
13 # 2. GPIO11 this pin is located near letter R of word RST.
15 # To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
16 # with 10K resistor connected to V3.3 pin.
18 # This board is powered from micro USB connector. No real reset pin or button, for
19 # example RESET_L is available.
21 source [find target/atheros_ar9331.cfg]
23 $_TARGETNAME configure -event reset-init {
29 set ram_boot_address 0xa0000000
30 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
32 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
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