1 # The Cogent CSB732 board has a single i.MX35 chip
2 source [find target/imx35.cfg]
4 # Determined by trial and error
5 reset_config trst_and_srst combined
9 $_TARGETNAME configure -event gdb-attach { reset init }
10 $_TARGETNAME configure -event reset-init { csb732_init }
12 # Bare-bones initialization of core clocks and SDRAM
13 proc csb732_init { } {
15 # Disable fast writing only for init
16 memwrite burst disable
18 # All delay loops are omitted.
19 # We assume the interpreter latency is enough.
21 # Allow access to all coprocessors
22 mcr 15 0 15 1 0 0x2001
24 # Disable MMU, caches, write buffer
27 # Grant manager access to all domains
28 mcr 15 0 3 0 0 0xFFFFFFFF
30 # Set ARM clock to 532 MHz, AHB to 133 MHz
33 # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
34 mww 0x53F8001C 0xB2C01
36 set ESDMISC 0xB8001010
37 set ESDCFG0 0xB8001004
38 set ESDCTL0 0xB8001000
44 mww $ESDCFG0 0x007fff3f
47 mww $ESDCTL0 0x92120080
49 # Precharge all dummy write
52 # Enable CS) auto-refresh
53 mww $ESDCTL0 0xA2120080
55 # Refresh twice (dummy writes)
59 # Enable CS0 load mode register
60 mww $ESDCTL0 0xB2120080
66 mww $ESDCTL0 0x82226080
69 # Re-enable fast writing
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