jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / tcl / board / csb732.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2
3 # The Cogent CSB732 board has a single i.MX35 chip
4 source [find target/imx35.cfg]
5
6 # Determined by trial and error
7 reset_config trst_and_srst combined
8 adapter srst delay 200
9 jtag_ntrst_delay 200
10
11 $_TARGETNAME configure -event gdb-attach { reset init }
12 $_TARGETNAME configure -event reset-init { csb732_init }
13
14 # Bare-bones initialization of core clocks and SDRAM
15 proc csb732_init { } {
16
17 # Disable fast writing only for init
18 memwrite burst disable
19
20 # All delay loops are omitted.
21 # We assume the interpreter latency is enough.
22
23 # Allow access to all coprocessors
24 arm mcr 15 0 15 1 0 0x2001
25
26 # Disable MMU, caches, write buffer
27 arm mcr 15 0 1 0 0 0x78
28
29 # Grant manager access to all domains
30 arm mcr 15 0 3 0 0 0xFFFFFFFF
31
32 # Set ARM clock to 532 MHz, AHB to 133 MHz
33 mww 0x53F80004 0x1000
34
35 # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
36 mww 0x53F8001C 0xB2C01
37
38 set ESDMISC 0xB8001010
39 set ESDCFG0 0xB8001004
40 set ESDCTL0 0xB8001000
41
42 # Enable DDR
43 mww $ESDMISC 0x4
44
45 # Timing
46 mww $ESDCFG0 0x007fff3f
47
48 # CS0
49 mww $ESDCTL0 0x92120080
50
51 # Precharge all dummy write
52 mww 0x80000400 0
53
54 # Enable CS) auto-refresh
55 mww $ESDCTL0 0xA2120080
56
57 # Refresh twice (dummy writes)
58 mww 0x80000000 0
59 mww 0x80000000 0
60
61 # Enable CS0 load mode register
62 mww $ESDCTL0 0xB2120080
63
64 # Dummy writes
65 mwb 0x80000033 0x01
66 mwb 0x81000000 0x01
67
68 mww $ESDCTL0 0x82226080
69 mww 0x80000000 0
70
71 # Re-enable fast writing
72 memwrite burst enable
73 }

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