1 /***************************************************************************
2 * Copyright (C) 2013-2014 by Franck Jullien *
5 * Inspired from adv_jtag_bridge which is: *
6 * Copyright (C) 2008-2010 Nathan Yawn *
7 * nyawn@opencores.net *
9 * And the Mohor interface version of this file which is: *
10 * Copyright (C) 2011 by Julius Baxter *
11 * julius@opencores.org *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
36 #include "jsp_server.h"
38 #include <target/target.h>
39 #include <jtag/jtag.h>
41 #define JSP_BANNER "\n\r" \
42 "******************************\n\r" \
43 "** JTAG Serial Port **\n\r" \
44 "******************************\n\r" \
49 /* This an option to the adv debug unit.
50 * If this is defined, status bits will be skipped on burst
51 * reads and writes to improve download speeds.
52 * This option must match the RTL configured option.
54 #define ADBG_USE_HISPEED 1
56 /* This an option to the adv debug unit.
57 * If this is defined, the JTAG Serial Port Server is started.
58 * This option must match the RTL configured option.
60 #define ENABLE_JSP_SERVER 2
62 /* Define this if you intend to use the JSP in a system with multiple
63 * devices on the JTAG chain
65 #define ENABLE_JSP_MULTI 4
67 /* Definitions for the top-level debug unit. This really just consists
68 * of a single register, used to select the active debug module ("chain").
70 #define DBG_MODULE_SELECT_REG_SIZE 2
71 #define DBG_MAX_MODULES 4
79 /* CPU control register bits mask */
80 #define DBG_CPU_CR_STALL 0x01
81 #define DBG_CPU_CR_RESET 0x02
83 /* Polynomial for the CRC calculation
84 * Yes, it's backwards. Yes, this is on purpose.
85 * The hardware is designed this way to save on logic and routing,
86 * and it's really all the same to us here.
88 #define ADBG_CRC_POLY 0xedb88320
90 /* These are for the internal registers in the Wishbone module
91 * The first is the length of the index register,
92 * the indexes of the various registers are defined after that.
94 #define DBG_WB_REG_SEL_LEN 1
95 #define DBG_WB_REG_ERROR 0
97 /* Opcode definitions for the Wishbone module. */
98 #define DBG_WB_OPCODE_LEN 4
99 #define DBG_WB_CMD_NOP 0x0
100 #define DBG_WB_CMD_BWRITE8 0x1
101 #define DBG_WB_CMD_BWRITE16 0x2
102 #define DBG_WB_CMD_BWRITE32 0x3
103 #define DBG_WB_CMD_BREAD8 0x5
104 #define DBG_WB_CMD_BREAD16 0x6
105 #define DBG_WB_CMD_BREAD32 0x7
106 #define DBG_WB_CMD_IREG_WR 0x9
107 #define DBG_WB_CMD_IREG_SEL 0xd
109 /* Internal register definitions for the CPU0 module. */
110 #define DBG_CPU0_REG_SEL_LEN 1
111 #define DBG_CPU0_REG_STATUS 0
113 /* Opcode definitions for the first CPU module. */
114 #define DBG_CPU0_OPCODE_LEN 4
115 #define DBG_CPU0_CMD_NOP 0x0
116 #define DBG_CPU0_CMD_BWRITE32 0x3
117 #define DBG_CPU0_CMD_BREAD32 0x7
118 #define DBG_CPU0_CMD_IREG_WR 0x9
119 #define DBG_CPU0_CMD_IREG_SEL 0xd
121 /* Internal register definitions for the CPU1 module. */
122 #define DBG_CPU1_REG_SEL_LEN 1
123 #define DBG_CPU1_REG_STATUS 0
125 /* Opcode definitions for the second CPU module. */
126 #define DBG_CPU1_OPCODE_LEN 4
127 #define DBG_CPU1_CMD_NOP 0x0
128 #define DBG_CPU1_CMD_BWRITE32 0x3
129 #define DBG_CPU1_CMD_BREAD32 0x7
130 #define DBG_CPU1_CMD_IREG_WR 0x9
131 #define DBG_CPU1_CMD_IREG_SEL 0xd
133 #define MAX_READ_STATUS_WAIT 10
134 #define MAX_READ_BUSY_RETRY 2
135 #define MAX_READ_CRC_RETRY 2
136 #define MAX_WRITE_CRC_RETRY 2
137 #define BURST_READ_READY 1
138 #define MAX_BUS_ERRORS 2
140 #define MAX_BURST_SIZE (4 * 1024)
142 #define STATUS_BYTES 1
145 static struct or1k_du or1k_du_adv
;
147 static const char * const chain_name
[] = {"WISHBONE", "CPU0", "CPU1", "JSP"};
149 static uint32_t adbg_compute_crc(uint32_t crc
, uint32_t data_in
,
152 for (int i
= 0; i
< length_bits
; i
++) {
154 d
= ((data_in
>> i
) & 0x1) ? 0xffffffff : 0;
155 c
= (crc
& 0x1) ? 0xffffffff : 0;
157 crc
= crc
^ ((d
^ c
) & ADBG_CRC_POLY
);
163 static int find_status_bit(void *_buf
, int len
)
170 while (!(buf
[i
] & (1 << count
++)) && (i
< len
)) {
178 ret
= (i
* 8) + count
;
183 static int or1k_adv_jtag_init(struct or1k_jtag
*jtag_info
)
185 struct or1k_tap_ip
*tap_ip
= jtag_info
->tap_ip
;
187 int retval
= tap_ip
->init(jtag_info
);
188 if (retval
!= ERROR_OK
) {
189 LOG_ERROR("TAP initialization failed");
193 /* TAP is now configured to communicate with debug interface */
194 jtag_info
->or1k_jtag_inited
= 1;
196 /* TAP reset - not sure what state debug module chain is in now */
197 jtag_info
->or1k_jtag_module_selected
= DC_NONE
;
199 jtag_info
->current_reg_idx
= malloc(DBG_MAX_MODULES
* sizeof(uint8_t));
200 memset(jtag_info
->current_reg_idx
, 0, DBG_MAX_MODULES
* sizeof(uint8_t));
202 if (or1k_du_adv
.options
& ADBG_USE_HISPEED
)
203 LOG_INFO("adv debug unit is configured with option ADBG_USE_HISPEED");
205 if (or1k_du_adv
.options
& ENABLE_JSP_SERVER
) {
206 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
)
207 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_MULTI");
208 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_SERVER");
209 retval
= jsp_init(jtag_info
, JSP_BANNER
);
210 if (retval
!= ERROR_OK
) {
211 LOG_ERROR("Couldn't start the JSP server");
216 LOG_DEBUG("Init done");
222 /* Selects one of the modules in the debug unit
223 * (e.g. wishbone unit, CPU0, etc.)
225 static int adbg_select_module(struct or1k_jtag
*jtag_info
, int chain
)
227 if (jtag_info
->or1k_jtag_module_selected
== chain
)
230 /* MSB of the data out must be set to 1, indicating a module
233 uint8_t data
= chain
| (1 << DBG_MODULE_SELECT_REG_SIZE
);
235 LOG_DEBUG("Select module: %s", chain_name
[chain
]);
237 struct scan_field field
;
239 field
.num_bits
= (DBG_MODULE_SELECT_REG_SIZE
+ 1);
240 field
.out_value
= &data
;
241 field
.in_value
= NULL
;
242 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
244 int retval
= jtag_execute_queue();
245 if (retval
!= ERROR_OK
)
248 jtag_info
->or1k_jtag_module_selected
= chain
;
253 /* Set the index of the desired register in the currently selected module
254 * 1 bit module select command
258 static int adbg_select_ctrl_reg(struct or1k_jtag
*jtag_info
, uint8_t regidx
)
264 /* If this reg is already selected, don't do a JTAG transaction */
265 if (jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] == regidx
)
268 switch (jtag_info
->or1k_jtag_module_selected
) {
270 index_len
= DBG_WB_REG_SEL_LEN
;
271 opcode
= DBG_WB_CMD_IREG_SEL
;
272 opcode_len
= DBG_WB_OPCODE_LEN
;
275 index_len
= DBG_CPU0_REG_SEL_LEN
;
276 opcode
= DBG_CPU0_CMD_IREG_SEL
;
277 opcode_len
= DBG_CPU0_OPCODE_LEN
;
280 index_len
= DBG_CPU1_REG_SEL_LEN
;
281 opcode
= DBG_CPU1_CMD_IREG_SEL
;
282 opcode_len
= DBG_CPU1_OPCODE_LEN
;
285 LOG_ERROR("Illegal debug chain selected (%i) while selecting control register",
286 jtag_info
->or1k_jtag_module_selected
);
290 /* MSB must be 0 to access modules */
291 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
294 struct scan_field field
;
296 field
.num_bits
= (opcode_len
+ 1) + index_len
;
297 field
.out_value
= (uint8_t *)&data
;
298 field
.in_value
= NULL
;
299 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
301 int retval
= jtag_execute_queue();
302 if (retval
!= ERROR_OK
)
305 jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] = regidx
;
310 /* Write control register (internal to the debug unit) */
311 static int adbg_ctrl_write(struct or1k_jtag
*jtag_info
, uint8_t regidx
,
312 uint32_t *cmd_data
, int length_bits
)
318 LOG_DEBUG("Write control register %" PRId8
": 0x%08" PRIx32
, regidx
, cmd_data
[0]);
320 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
321 if (retval
!= ERROR_OK
) {
322 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
326 switch (jtag_info
->or1k_jtag_module_selected
) {
328 index_len
= DBG_WB_REG_SEL_LEN
;
329 opcode
= DBG_WB_CMD_IREG_WR
;
330 opcode_len
= DBG_WB_OPCODE_LEN
;
333 index_len
= DBG_CPU0_REG_SEL_LEN
;
334 opcode
= DBG_CPU0_CMD_IREG_WR
;
335 opcode_len
= DBG_CPU0_OPCODE_LEN
;
338 index_len
= DBG_CPU1_REG_SEL_LEN
;
339 opcode
= DBG_CPU1_CMD_IREG_WR
;
340 opcode_len
= DBG_CPU1_OPCODE_LEN
;
343 LOG_ERROR("Illegal debug chain selected (%i) while doing control write",
344 jtag_info
->or1k_jtag_module_selected
);
348 struct scan_field field
[2];
350 /* MSB must be 0 to access modules */
351 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
354 field
[0].num_bits
= length_bits
;
355 field
[0].out_value
= (uint8_t *)cmd_data
;
356 field
[0].in_value
= NULL
;
358 field
[1].num_bits
= (opcode_len
+ 1) + index_len
;
359 field
[1].out_value
= (uint8_t *)&data
;
360 field
[1].in_value
= NULL
;
362 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
364 return jtag_execute_queue();
367 /* Reads control register (internal to the debug unit) */
368 static int adbg_ctrl_read(struct or1k_jtag
*jtag_info
, uint32_t regidx
,
369 uint32_t *data
, int length_bits
)
372 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
373 if (retval
!= ERROR_OK
) {
374 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
381 /* There is no 'read' command, We write a NOP to read */
382 switch (jtag_info
->or1k_jtag_module_selected
) {
384 opcode
= DBG_WB_CMD_NOP
;
385 opcode_len
= DBG_WB_OPCODE_LEN
;
388 opcode
= DBG_CPU0_CMD_NOP
;
389 opcode_len
= DBG_CPU0_OPCODE_LEN
;
392 opcode
= DBG_CPU1_CMD_NOP
;
393 opcode_len
= DBG_CPU1_OPCODE_LEN
;
396 LOG_ERROR("Illegal debug chain selected (%i) while doing control read",
397 jtag_info
->or1k_jtag_module_selected
);
401 /* Zero MSB = op for module, not top-level debug unit */
402 uint32_t outdata
= opcode
& ~(0x1 << opcode_len
);
404 struct scan_field field
[2];
406 field
[0].num_bits
= length_bits
;
407 field
[0].out_value
= NULL
;
408 field
[0].in_value
= (uint8_t *)data
;
410 field
[1].num_bits
= opcode_len
+ 1;
411 field
[1].out_value
= (uint8_t *)&outdata
;
412 field
[1].in_value
= NULL
;
414 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
416 return jtag_execute_queue();
419 /* sends out a burst command to the selected module in the debug unit (MSB to LSB):
420 * 1-bit module command
423 * 16-bit length (of the burst, in words)
425 static int adbg_burst_command(struct or1k_jtag
*jtag_info
, uint32_t opcode
,
426 uint32_t address
, uint16_t length_words
)
430 /* Set up the data */
431 data
[0] = length_words
| (address
<< 16);
432 /* MSB must be 0 to access modules */
433 data
[1] = ((address
>> 16) | ((opcode
& 0xf) << 16)) & ~(0x1 << 20);
435 struct scan_field field
;
438 field
.out_value
= (uint8_t *)&data
[0];
439 field
.in_value
= NULL
;
441 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
443 return jtag_execute_queue();
446 static int adbg_wb_burst_read(struct or1k_jtag
*jtag_info
, int size
,
447 int count
, uint32_t start_address
, uint8_t *data
)
449 int retry_full_crc
= 0;
450 int retry_full_busy
= 0;
454 LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32
,
455 size
, count
, start_address
);
457 /* Select the appropriate opcode */
458 switch (jtag_info
->or1k_jtag_module_selected
) {
461 opcode
= DBG_WB_CMD_BREAD8
;
463 opcode
= DBG_WB_CMD_BREAD16
;
465 opcode
= DBG_WB_CMD_BREAD32
;
467 LOG_WARNING("Tried burst read with invalid word size (%d),"
468 "defaulting to 4-byte words", size
);
469 opcode
= DBG_WB_CMD_BREAD32
;
474 opcode
= DBG_CPU0_CMD_BREAD32
;
476 LOG_WARNING("Tried burst read with invalid word size (%d),"
477 "defaulting to 4-byte words", size
);
478 opcode
= DBG_CPU0_CMD_BREAD32
;
483 opcode
= DBG_CPU1_CMD_BREAD32
;
485 LOG_WARNING("Tried burst read with invalid word size (%d),"
486 "defaulting to 4-byte words", size
);
487 opcode
= DBG_CPU0_CMD_BREAD32
;
491 LOG_ERROR("Illegal debug chain selected (%i) while doing burst read",
492 jtag_info
->or1k_jtag_module_selected
);
496 int total_size_bytes
= count
* size
;
497 struct scan_field field
;
498 uint8_t *in_buffer
= malloc(total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
);
502 /* Send the BURST READ command, returns TAP to idle state */
503 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
504 if (retval
!= ERROR_OK
)
507 field
.num_bits
= (total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
) * 8;
508 field
.out_value
= NULL
;
509 field
.in_value
= in_buffer
;
511 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
513 retval
= jtag_execute_queue();
514 if (retval
!= ERROR_OK
)
517 /* Look for the start bit in the first (STATUS_BYTES * 8) bits */
518 int shift
= find_status_bit(in_buffer
, STATUS_BYTES
);
520 /* We expect the status bit to be in the first byte */
522 if (retry_full_busy
++ < MAX_READ_BUSY_RETRY
) {
523 LOG_WARNING("Burst read timed out");
524 goto retry_read_full
;
526 LOG_ERROR("Burst read failed");
532 buffer_shr(in_buffer
, total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
, shift
);
535 memcpy(data
, in_buffer
, total_size_bytes
);
536 memcpy(&crc_read
, &in_buffer
[total_size_bytes
], 4);
538 uint32_t crc_calc
= 0xffffffff;
539 for (int i
= 0; i
< total_size_bytes
; i
++)
540 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
542 if (crc_calc
!= crc_read
) {
543 LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32
", read CRC 0x%08" PRIx32
, crc_calc
, crc_read
);
544 if (retry_full_crc
++ < MAX_READ_CRC_RETRY
)
545 goto retry_read_full
;
547 LOG_ERROR("Burst read failed");
552 LOG_DEBUG("CRC OK!");
554 /* Now, read the error register, and retry/recompute as necessary */
555 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
556 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
558 uint32_t err_data
[2] = {0, 0};
560 int bus_error_retries
= 0;
562 /* First, just get 1 bit...read address only if necessary */
563 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
564 if (retval
!= ERROR_OK
)
567 /* Then we have a problem */
568 if (err_data
[0] & 0x1) {
570 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
571 if (retval
!= ERROR_OK
)
574 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
575 LOG_WARNING("WB bus error during burst read, address 0x%08" PRIx32
", retrying!", addr
);
578 if (bus_error_retries
> MAX_BUS_ERRORS
) {
579 LOG_ERROR("Max WB bus errors reached during burst read");
584 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
585 /* Write 1 bit, to reset the error register */
587 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
588 if (retval
!= ERROR_OK
)
591 goto retry_read_full
;
601 /* Set up and execute a burst write to a contiguous set of addresses */
602 static int adbg_wb_burst_write(struct or1k_jtag
*jtag_info
, const uint8_t *data
, int size
,
603 int count
, unsigned long start_address
)
605 int retry_full_crc
= 0;
609 LOG_DEBUG("Doing burst write, word size %d, word count %d,"
610 "start address 0x%08lx", size
, count
, start_address
);
612 /* Select the appropriate opcode */
613 switch (jtag_info
->or1k_jtag_module_selected
) {
616 opcode
= DBG_WB_CMD_BWRITE8
;
618 opcode
= DBG_WB_CMD_BWRITE16
;
620 opcode
= DBG_WB_CMD_BWRITE32
;
622 LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
623 "defaulting to 4-byte words", size
);
624 opcode
= DBG_WB_CMD_BWRITE32
;
629 opcode
= DBG_CPU0_CMD_BWRITE32
;
631 LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
632 "defaulting to 4-byte words", size
);
633 opcode
= DBG_CPU0_CMD_BWRITE32
;
638 opcode
= DBG_CPU1_CMD_BWRITE32
;
640 LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
641 "defaulting to 4-byte words", size
);
642 opcode
= DBG_CPU0_CMD_BWRITE32
;
646 LOG_ERROR("Illegal debug chain selected (%i) while doing burst write",
647 jtag_info
->or1k_jtag_module_selected
);
653 /* Send the BURST WRITE command, returns TAP to idle state */
654 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
655 if (retval
!= ERROR_OK
)
658 struct scan_field field
[3];
660 /* Write a start bit so it knows when to start counting */
662 field
[0].num_bits
= 1;
663 field
[0].out_value
= &value
;
664 field
[0].in_value
= NULL
;
666 uint32_t crc_calc
= 0xffffffff;
667 for (int i
= 0; i
< (count
* size
); i
++)
668 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
670 field
[1].num_bits
= count
* size
* 8;
671 field
[1].out_value
= data
;
672 field
[1].in_value
= NULL
;
674 field
[2].num_bits
= 32;
675 field
[2].out_value
= (uint8_t *)&crc_calc
;
676 field
[2].in_value
= NULL
;
678 jtag_add_dr_scan(jtag_info
->tap
, 3, field
, TAP_DRSHIFT
);
680 /* Read the 'CRC match' bit, and go to idle */
681 field
[0].num_bits
= 1;
682 field
[0].out_value
= NULL
;
683 field
[0].in_value
= &value
;
684 jtag_add_dr_scan(jtag_info
->tap
, 1, field
, TAP_IDLE
);
686 retval
= jtag_execute_queue();
687 if (retval
!= ERROR_OK
)
691 LOG_WARNING("CRC ERROR! match bit after write is %" PRIi8
" (computed CRC 0x%08" PRIx32
")", value
, crc_calc
);
692 if (retry_full_crc
++ < MAX_WRITE_CRC_RETRY
)
693 goto retry_full_write
;
697 LOG_DEBUG("CRC OK!\n");
699 /* Now, read the error register, and retry/recompute as necessary */
700 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
701 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
703 int bus_error_retries
= 0;
704 uint32_t err_data
[2] = {0, 0};
706 /* First, just get 1 bit...read address only if necessary */
707 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
708 if (retval
!= ERROR_OK
)
711 /* Then we have a problem */
712 if (err_data
[0] & 0x1) {
714 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
715 if (retval
!= ERROR_OK
)
718 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
719 LOG_WARNING("WB bus error during burst write, address 0x%08" PRIx32
", retrying!", addr
);
722 if (bus_error_retries
> MAX_BUS_ERRORS
) {
723 LOG_ERROR("Max WB bus errors reached during burst read");
728 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
729 /* Write 1 bit, to reset the error register */
731 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
732 if (retval
!= ERROR_OK
)
735 goto retry_full_write
;
742 /* Currently hard set in functions to 32-bits */
743 static int or1k_adv_jtag_read_cpu(struct or1k_jtag
*jtag_info
,
744 uint32_t addr
, int count
, uint32_t *value
)
747 if (!jtag_info
->or1k_jtag_inited
) {
748 retval
= or1k_adv_jtag_init(jtag_info
);
749 if (retval
!= ERROR_OK
)
753 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
754 if (retval
!= ERROR_OK
)
757 return adbg_wb_burst_read(jtag_info
, 4, count
, addr
, (uint8_t *)value
);
760 static int or1k_adv_jtag_write_cpu(struct or1k_jtag
*jtag_info
,
761 uint32_t addr
, int count
, const uint32_t *value
)
764 if (!jtag_info
->or1k_jtag_inited
) {
765 retval
= or1k_adv_jtag_init(jtag_info
);
766 if (retval
!= ERROR_OK
)
770 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
771 if (retval
!= ERROR_OK
)
774 return adbg_wb_burst_write(jtag_info
, (uint8_t *)value
, 4, count
, addr
);
777 static int or1k_adv_cpu_stall(struct or1k_jtag
*jtag_info
, int action
)
780 if (!jtag_info
->or1k_jtag_inited
) {
781 retval
= or1k_adv_jtag_init(jtag_info
);
782 if (retval
!= ERROR_OK
)
786 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
787 if (retval
!= ERROR_OK
)
791 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
792 if (retval
!= ERROR_OK
)
795 if (action
== CPU_STALL
)
796 cpu_cr
|= DBG_CPU_CR_STALL
;
798 cpu_cr
&= ~DBG_CPU_CR_STALL
;
800 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
801 if (retval
!= ERROR_OK
)
804 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
807 static int or1k_adv_is_cpu_running(struct or1k_jtag
*jtag_info
, int *running
)
810 if (!jtag_info
->or1k_jtag_inited
) {
811 retval
= or1k_adv_jtag_init(jtag_info
);
812 if (retval
!= ERROR_OK
)
816 int current
= jtag_info
->or1k_jtag_module_selected
;
818 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
819 if (retval
!= ERROR_OK
)
823 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
824 if (retval
!= ERROR_OK
)
827 if (cpu_cr
& DBG_CPU_CR_STALL
)
832 if (current
!= DC_NONE
) {
833 retval
= adbg_select_module(jtag_info
, current
);
834 if (retval
!= ERROR_OK
)
841 static int or1k_adv_cpu_reset(struct or1k_jtag
*jtag_info
, int action
)
844 if (!jtag_info
->or1k_jtag_inited
) {
845 retval
= or1k_adv_jtag_init(jtag_info
);
846 if (retval
!= ERROR_OK
)
850 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
851 if (retval
!= ERROR_OK
)
855 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
856 if (retval
!= ERROR_OK
)
859 if (action
== CPU_RESET
)
860 cpu_cr
|= DBG_CPU_CR_RESET
;
862 cpu_cr
&= ~DBG_CPU_CR_RESET
;
864 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
865 if (retval
!= ERROR_OK
)
868 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
871 static int or1k_adv_jtag_read_memory(struct or1k_jtag
*jtag_info
,
872 uint32_t addr
, uint32_t size
, int count
, uint8_t *buffer
)
874 LOG_DEBUG("Reading WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
877 if (!jtag_info
->or1k_jtag_inited
) {
878 retval
= or1k_adv_jtag_init(jtag_info
);
879 if (retval
!= ERROR_OK
)
883 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
884 if (retval
!= ERROR_OK
)
887 int block_count_left
= count
;
888 uint32_t block_count_address
= addr
;
889 uint8_t *block_count_buffer
= buffer
;
891 while (block_count_left
) {
893 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
894 MAX_BURST_SIZE
: block_count_left
;
896 retval
= adbg_wb_burst_read(jtag_info
, size
, blocks_this_round
,
897 block_count_address
, block_count_buffer
);
898 if (retval
!= ERROR_OK
)
901 block_count_left
-= blocks_this_round
;
902 block_count_address
+= size
* MAX_BURST_SIZE
;
903 block_count_buffer
+= size
* MAX_BURST_SIZE
;
906 /* The adv_debug_if always return words and half words in
907 * little-endian order no matter what the target endian is.
908 * So if the target endian is big, change the order.
911 struct target
*target
= jtag_info
->target
;
912 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
915 buf_bswap32(buffer
, buffer
, size
* count
);
918 buf_bswap16(buffer
, buffer
, size
* count
);
926 static int or1k_adv_jtag_write_memory(struct or1k_jtag
*jtag_info
,
927 uint32_t addr
, uint32_t size
, int count
, const uint8_t *buffer
)
929 LOG_DEBUG("Writing WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
932 if (!jtag_info
->or1k_jtag_inited
) {
933 retval
= or1k_adv_jtag_init(jtag_info
);
934 if (retval
!= ERROR_OK
)
938 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
939 if (retval
!= ERROR_OK
)
942 /* The adv_debug_if wants words and half words in little-endian
943 * order no matter what the target endian is. So if the target
944 * endian is big, change the order.
948 struct target
*target
= jtag_info
->target
;
949 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
950 t
= malloc(count
* size
* sizeof(uint8_t));
952 LOG_ERROR("Out of memory");
958 buf_bswap32(t
, buffer
, size
* count
);
961 buf_bswap16(t
, buffer
, size
* count
);
967 int block_count_left
= count
;
968 uint32_t block_count_address
= addr
;
969 uint8_t *block_count_buffer
= (uint8_t *)buffer
;
971 while (block_count_left
) {
973 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
974 MAX_BURST_SIZE
: block_count_left
;
976 retval
= adbg_wb_burst_write(jtag_info
, block_count_buffer
,
977 size
, blocks_this_round
,
978 block_count_address
);
979 if (retval
!= ERROR_OK
) {
985 block_count_left
-= blocks_this_round
;
986 block_count_address
+= size
* MAX_BURST_SIZE
;
987 block_count_buffer
+= size
* MAX_BURST_SIZE
;
996 int or1k_adv_jtag_jsp_xfer(struct or1k_jtag
*jtag_info
,
997 int *out_len
, unsigned char *out_buffer
,
998 int *in_len
, unsigned char *in_buffer
)
1000 LOG_DEBUG("JSP transfert");
1003 if (!jtag_info
->or1k_jtag_inited
)
1006 retval
= adbg_select_module(jtag_info
, DC_JSP
);
1007 if (retval
!= ERROR_OK
)
1010 /* return nb char xmit */
1015 xmitsize
= *out_len
;
1017 uint8_t out_data
[10];
1018 uint8_t in_data
[10];
1019 struct scan_field field
;
1020 int startbit
, stopbit
, wrapbit
;
1022 memset(out_data
, 0, 10);
1024 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
) {
1027 wrapbit
= (xmitsize
>> 3) & 0x1;
1028 out_data
[0] = (xmitsize
<< 5) | 0x1; /* set the start bit */
1031 /* don't copy off the end of the input array */
1032 for (i
= 0; i
< xmitsize
; i
++) {
1033 out_data
[i
+ 1] = (out_buffer
[i
] << 1) | wrapbit
;
1034 wrapbit
= (out_buffer
[i
] >> 7) & 0x1;
1038 out_data
[i
+ 1] = wrapbit
;
1040 out_data
[9] = wrapbit
;
1042 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1043 * won't treat the burst as a 'module select' command.
1045 stopbit
= !!(out_data
[9] & 0x01);
1049 /* First byte out has write count in upper nibble */
1050 out_data
[0] = 0x0 | (xmitsize
<< 4);
1052 memcpy(&out_data
[1], out_buffer
, xmitsize
);
1054 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1055 * won't treat the burst as a 'module select' command.
1057 stopbit
= !!(out_data
[8] & 0x80);
1060 field
.num_bits
= 72 + startbit
+ stopbit
;
1061 field
.out_value
= out_data
;
1062 field
.in_value
= in_data
;
1064 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
1066 retval
= jtag_execute_queue();
1067 if (retval
!= ERROR_OK
)
1070 /* bytes available is in the upper nibble */
1071 *in_len
= (in_data
[0] >> 4) & 0xF;
1072 memcpy(in_buffer
, &in_data
[1], *in_len
);
1074 int bytes_free
= in_data
[0] & 0x0F;
1075 *out_len
= (bytes_free
< xmitsize
) ? bytes_free
: xmitsize
;
1080 static struct or1k_du or1k_du_adv
= {
1082 .options
= NO_OPTION
,
1083 .or1k_jtag_init
= or1k_adv_jtag_init
,
1085 .or1k_is_cpu_running
= or1k_adv_is_cpu_running
,
1086 .or1k_cpu_stall
= or1k_adv_cpu_stall
,
1087 .or1k_cpu_reset
= or1k_adv_cpu_reset
,
1089 .or1k_jtag_read_cpu
= or1k_adv_jtag_read_cpu
,
1090 .or1k_jtag_write_cpu
= or1k_adv_jtag_write_cpu
,
1092 .or1k_jtag_read_memory
= or1k_adv_jtag_read_memory
,
1093 .or1k_jtag_write_memory
= or1k_adv_jtag_write_memory
1096 int or1k_du_adv_register(void)
1098 list_add_tail(&or1k_du_adv
.list
, &du_list
);
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