Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / openrisc / or1k_du_adv.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013-2014 by Franck Jullien *
5 * elec4fun@gmail.com *
6 * *
7 * Inspired from adv_jtag_bridge which is: *
8 * Copyright (C) 2008-2010 Nathan Yawn *
9 * nyawn@opencores.net *
10 * *
11 * And the Mohor interface version of this file which is: *
12 * Copyright (C) 2011 by Julius Baxter *
13 * julius@opencores.org *
14 ***************************************************************************/
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "or1k_tap.h"
21 #include "or1k.h"
22 #include "or1k_du.h"
23 #include "jsp_server.h"
24
25 #include <helper/crc32.h>
26 #include <jtag/jtag.h>
27 #include <target/target.h>
28
29 #define JSP_BANNER "\n\r" \
30 "******************************\n\r" \
31 "** JTAG Serial Port **\n\r" \
32 "******************************\n\r" \
33 "\n\r"
34
35 #define NO_OPTION 0
36
37 /* This an option to the adv debug unit.
38 * If this is defined, status bits will be skipped on burst
39 * reads and writes to improve download speeds.
40 * This option must match the RTL configured option.
41 */
42 #define ADBG_USE_HISPEED 1
43
44 /* This an option to the adv debug unit.
45 * If this is defined, the JTAG Serial Port Server is started.
46 * This option must match the RTL configured option.
47 */
48 #define ENABLE_JSP_SERVER 2
49
50 /* Define this if you intend to use the JSP in a system with multiple
51 * devices on the JTAG chain
52 */
53 #define ENABLE_JSP_MULTI 4
54
55 /* Definitions for the top-level debug unit. This really just consists
56 * of a single register, used to select the active debug module ("chain").
57 */
58 #define DBG_MODULE_SELECT_REG_SIZE 2
59 #define DBG_MAX_MODULES 4
60
61 #define DC_NONE -1
62 #define DC_WISHBONE 0
63 #define DC_CPU0 1
64 #define DC_CPU1 2
65 #define DC_JSP 3
66
67 /* CPU control register bits mask */
68 #define DBG_CPU_CR_STALL 0x01
69 #define DBG_CPU_CR_RESET 0x02
70
71 /* These are for the internal registers in the Wishbone module
72 * The first is the length of the index register,
73 * the indexes of the various registers are defined after that.
74 */
75 #define DBG_WB_REG_SEL_LEN 1
76 #define DBG_WB_REG_ERROR 0
77
78 /* Opcode definitions for the Wishbone module. */
79 #define DBG_WB_OPCODE_LEN 4
80 #define DBG_WB_CMD_NOP 0x0
81 #define DBG_WB_CMD_BWRITE8 0x1
82 #define DBG_WB_CMD_BWRITE16 0x2
83 #define DBG_WB_CMD_BWRITE32 0x3
84 #define DBG_WB_CMD_BREAD8 0x5
85 #define DBG_WB_CMD_BREAD16 0x6
86 #define DBG_WB_CMD_BREAD32 0x7
87 #define DBG_WB_CMD_IREG_WR 0x9
88 #define DBG_WB_CMD_IREG_SEL 0xd
89
90 /* Internal register definitions for the CPU0 module. */
91 #define DBG_CPU0_REG_SEL_LEN 1
92 #define DBG_CPU0_REG_STATUS 0
93
94 /* Opcode definitions for the first CPU module. */
95 #define DBG_CPU0_OPCODE_LEN 4
96 #define DBG_CPU0_CMD_NOP 0x0
97 #define DBG_CPU0_CMD_BWRITE32 0x3
98 #define DBG_CPU0_CMD_BREAD32 0x7
99 #define DBG_CPU0_CMD_IREG_WR 0x9
100 #define DBG_CPU0_CMD_IREG_SEL 0xd
101
102 /* Internal register definitions for the CPU1 module. */
103 #define DBG_CPU1_REG_SEL_LEN 1
104 #define DBG_CPU1_REG_STATUS 0
105
106 /* Opcode definitions for the second CPU module. */
107 #define DBG_CPU1_OPCODE_LEN 4
108 #define DBG_CPU1_CMD_NOP 0x0
109 #define DBG_CPU1_CMD_BWRITE32 0x3
110 #define DBG_CPU1_CMD_BREAD32 0x7
111 #define DBG_CPU1_CMD_IREG_WR 0x9
112 #define DBG_CPU1_CMD_IREG_SEL 0xd
113
114 #define MAX_READ_STATUS_WAIT 10
115 #define MAX_READ_BUSY_RETRY 2
116 #define MAX_READ_CRC_RETRY 2
117 #define MAX_WRITE_CRC_RETRY 2
118 #define BURST_READ_READY 1
119 #define MAX_BUS_ERRORS 2
120
121 #define MAX_BURST_SIZE (4 * 1024)
122
123 #define STATUS_BYTES 1
124 #define CRC_LEN 4
125
126 static struct or1k_du or1k_du_adv;
127
128 static const char * const chain_name[] = {"WISHBONE", "CPU0", "CPU1", "JSP"};
129
130 static int find_status_bit(void *_buf, int len)
131 {
132 int i = 0;
133 int count = 0;
134 int ret = -1;
135 uint8_t *buf = _buf;
136
137 while (!(buf[i] & (1 << count++)) && (i < len)) {
138 if (count == 8) {
139 count = 0;
140 i++;
141 }
142 }
143
144 if (i < len)
145 ret = (i * 8) + count;
146
147 return ret;
148 }
149
150 static int or1k_adv_jtag_init(struct or1k_jtag *jtag_info)
151 {
152 struct or1k_tap_ip *tap_ip = jtag_info->tap_ip;
153
154 int retval = tap_ip->init(jtag_info);
155 if (retval != ERROR_OK) {
156 LOG_ERROR("TAP initialization failed");
157 return retval;
158 }
159
160 /* TAP is now configured to communicate with debug interface */
161 jtag_info->or1k_jtag_inited = 1;
162
163 /* TAP reset - not sure what state debug module chain is in now */
164 jtag_info->or1k_jtag_module_selected = DC_NONE;
165
166 jtag_info->current_reg_idx = malloc(DBG_MAX_MODULES * sizeof(uint8_t));
167 memset(jtag_info->current_reg_idx, 0, DBG_MAX_MODULES * sizeof(uint8_t));
168
169 if (or1k_du_adv.options & ADBG_USE_HISPEED)
170 LOG_INFO("adv debug unit is configured with option ADBG_USE_HISPEED");
171
172 if (or1k_du_adv.options & ENABLE_JSP_SERVER) {
173 if (or1k_du_adv.options & ENABLE_JSP_MULTI)
174 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_MULTI");
175 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_SERVER");
176 retval = jsp_init(jtag_info, JSP_BANNER);
177 if (retval != ERROR_OK) {
178 LOG_ERROR("Couldn't start the JSP server");
179 return retval;
180 }
181 }
182
183 LOG_DEBUG("Init done");
184
185 return ERROR_OK;
186
187 }
188
189 /* Selects one of the modules in the debug unit
190 * (e.g. wishbone unit, CPU0, etc.)
191 */
192 static int adbg_select_module(struct or1k_jtag *jtag_info, int chain)
193 {
194 if (jtag_info->or1k_jtag_module_selected == chain)
195 return ERROR_OK;
196
197 /* MSB of the data out must be set to 1, indicating a module
198 * select command
199 */
200 uint8_t data = chain | (1 << DBG_MODULE_SELECT_REG_SIZE);
201
202 LOG_DEBUG("Select module: %s", chain_name[chain]);
203
204 struct scan_field field;
205
206 field.num_bits = (DBG_MODULE_SELECT_REG_SIZE + 1);
207 field.out_value = &data;
208 field.in_value = NULL;
209 jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
210
211 int retval = jtag_execute_queue();
212 if (retval != ERROR_OK)
213 return retval;
214
215 jtag_info->or1k_jtag_module_selected = chain;
216
217 return ERROR_OK;
218 }
219
220 /* Set the index of the desired register in the currently selected module
221 * 1 bit module select command
222 * 4 bits opcode
223 * n bits index
224 */
225 static int adbg_select_ctrl_reg(struct or1k_jtag *jtag_info, uint8_t regidx)
226 {
227 int index_len;
228 uint32_t opcode;
229 uint32_t opcode_len;
230
231 /* If this reg is already selected, don't do a JTAG transaction */
232 if (jtag_info->current_reg_idx[jtag_info->or1k_jtag_module_selected] == regidx)
233 return ERROR_OK;
234
235 switch (jtag_info->or1k_jtag_module_selected) {
236 case DC_WISHBONE:
237 index_len = DBG_WB_REG_SEL_LEN;
238 opcode = DBG_WB_CMD_IREG_SEL;
239 opcode_len = DBG_WB_OPCODE_LEN;
240 break;
241 case DC_CPU0:
242 index_len = DBG_CPU0_REG_SEL_LEN;
243 opcode = DBG_CPU0_CMD_IREG_SEL;
244 opcode_len = DBG_CPU0_OPCODE_LEN;
245 break;
246 case DC_CPU1:
247 index_len = DBG_CPU1_REG_SEL_LEN;
248 opcode = DBG_CPU1_CMD_IREG_SEL;
249 opcode_len = DBG_CPU1_OPCODE_LEN;
250 break;
251 default:
252 LOG_ERROR("Illegal debug chain selected (%i) while selecting control register",
253 jtag_info->or1k_jtag_module_selected);
254 return ERROR_FAIL;
255 }
256
257 /* MSB must be 0 to access modules */
258 uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
259 data |= regidx;
260
261 struct scan_field field;
262
263 field.num_bits = (opcode_len + 1) + index_len;
264 field.out_value = (uint8_t *)&data;
265 field.in_value = NULL;
266 jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
267
268 int retval = jtag_execute_queue();
269 if (retval != ERROR_OK)
270 return retval;
271
272 jtag_info->current_reg_idx[jtag_info->or1k_jtag_module_selected] = regidx;
273
274 return ERROR_OK;
275 }
276
277 /* Write control register (internal to the debug unit) */
278 static int adbg_ctrl_write(struct or1k_jtag *jtag_info, uint8_t regidx,
279 uint32_t *cmd_data, int length_bits)
280 {
281 int index_len;
282 uint32_t opcode;
283 uint32_t opcode_len;
284
285 LOG_DEBUG("Write control register %" PRId8 ": 0x%08" PRIx32, regidx, cmd_data[0]);
286
287 int retval = adbg_select_ctrl_reg(jtag_info, regidx);
288 if (retval != ERROR_OK) {
289 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
290 return retval;
291 }
292
293 switch (jtag_info->or1k_jtag_module_selected) {
294 case DC_WISHBONE:
295 index_len = DBG_WB_REG_SEL_LEN;
296 opcode = DBG_WB_CMD_IREG_WR;
297 opcode_len = DBG_WB_OPCODE_LEN;
298 break;
299 case DC_CPU0:
300 index_len = DBG_CPU0_REG_SEL_LEN;
301 opcode = DBG_CPU0_CMD_IREG_WR;
302 opcode_len = DBG_CPU0_OPCODE_LEN;
303 break;
304 case DC_CPU1:
305 index_len = DBG_CPU1_REG_SEL_LEN;
306 opcode = DBG_CPU1_CMD_IREG_WR;
307 opcode_len = DBG_CPU1_OPCODE_LEN;
308 break;
309 default:
310 LOG_ERROR("Illegal debug chain selected (%i) while doing control write",
311 jtag_info->or1k_jtag_module_selected);
312 return ERROR_FAIL;
313 }
314
315 struct scan_field field[2];
316
317 /* MSB must be 0 to access modules */
318 uint32_t data = (opcode & ~(1 << opcode_len)) << index_len;
319 data |= regidx;
320
321 field[0].num_bits = length_bits;
322 field[0].out_value = (uint8_t *)cmd_data;
323 field[0].in_value = NULL;
324
325 field[1].num_bits = (opcode_len + 1) + index_len;
326 field[1].out_value = (uint8_t *)&data;
327 field[1].in_value = NULL;
328
329 jtag_add_dr_scan(jtag_info->tap, 2, field, TAP_IDLE);
330
331 return jtag_execute_queue();
332 }
333
334 /* Reads control register (internal to the debug unit) */
335 static int adbg_ctrl_read(struct or1k_jtag *jtag_info, uint32_t regidx,
336 uint32_t *data, int length_bits)
337 {
338
339 int retval = adbg_select_ctrl_reg(jtag_info, regidx);
340 if (retval != ERROR_OK) {
341 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
342 return retval;
343 }
344
345 int opcode_len;
346 uint32_t opcode;
347
348 /* There is no 'read' command, We write a NOP to read */
349 switch (jtag_info->or1k_jtag_module_selected) {
350 case DC_WISHBONE:
351 opcode = DBG_WB_CMD_NOP;
352 opcode_len = DBG_WB_OPCODE_LEN;
353 break;
354 case DC_CPU0:
355 opcode = DBG_CPU0_CMD_NOP;
356 opcode_len = DBG_CPU0_OPCODE_LEN;
357 break;
358 case DC_CPU1:
359 opcode = DBG_CPU1_CMD_NOP;
360 opcode_len = DBG_CPU1_OPCODE_LEN;
361 break;
362 default:
363 LOG_ERROR("Illegal debug chain selected (%i) while doing control read",
364 jtag_info->or1k_jtag_module_selected);
365 return ERROR_FAIL;
366 }
367
368 /* Zero MSB = op for module, not top-level debug unit */
369 uint32_t outdata = opcode & ~(0x1 << opcode_len);
370
371 struct scan_field field[2];
372
373 field[0].num_bits = length_bits;
374 field[0].out_value = NULL;
375 field[0].in_value = (uint8_t *)data;
376
377 field[1].num_bits = opcode_len + 1;
378 field[1].out_value = (uint8_t *)&outdata;
379 field[1].in_value = NULL;
380
381 jtag_add_dr_scan(jtag_info->tap, 2, field, TAP_IDLE);
382
383 return jtag_execute_queue();
384 }
385
386 /* sends out a burst command to the selected module in the debug unit (MSB to LSB):
387 * 1-bit module command
388 * 4-bit opcode
389 * 32-bit address
390 * 16-bit length (of the burst, in words)
391 */
392 static int adbg_burst_command(struct or1k_jtag *jtag_info, uint32_t opcode,
393 uint32_t address, uint16_t length_words)
394 {
395 uint32_t data[2];
396
397 /* Set up the data */
398 data[0] = length_words | (address << 16);
399 /* MSB must be 0 to access modules */
400 data[1] = ((address >> 16) | ((opcode & 0xf) << 16)) & ~(0x1 << 20);
401
402 struct scan_field field;
403
404 field.num_bits = 53;
405 field.out_value = (uint8_t *)&data[0];
406 field.in_value = NULL;
407
408 jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
409
410 return jtag_execute_queue();
411 }
412
413 static int adbg_wb_burst_read(struct or1k_jtag *jtag_info, int size,
414 int count, uint32_t start_address, uint8_t *data)
415 {
416 int retry_full_crc = 0;
417 int retry_full_busy = 0;
418 int retval;
419 uint8_t opcode;
420
421 LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32,
422 size, count, start_address);
423
424 /* Select the appropriate opcode */
425 switch (jtag_info->or1k_jtag_module_selected) {
426 case DC_WISHBONE:
427 if (size == 1)
428 opcode = DBG_WB_CMD_BREAD8;
429 else if (size == 2)
430 opcode = DBG_WB_CMD_BREAD16;
431 else if (size == 4)
432 opcode = DBG_WB_CMD_BREAD32;
433 else {
434 LOG_WARNING("Tried burst read with invalid word size (%d),"
435 "defaulting to 4-byte words", size);
436 opcode = DBG_WB_CMD_BREAD32;
437 }
438 break;
439 case DC_CPU0:
440 if (size == 4)
441 opcode = DBG_CPU0_CMD_BREAD32;
442 else {
443 LOG_WARNING("Tried burst read with invalid word size (%d),"
444 "defaulting to 4-byte words", size);
445 opcode = DBG_CPU0_CMD_BREAD32;
446 }
447 break;
448 case DC_CPU1:
449 if (size == 4)
450 opcode = DBG_CPU1_CMD_BREAD32;
451 else {
452 LOG_WARNING("Tried burst read with invalid word size (%d),"
453 "defaulting to 4-byte words", size);
454 opcode = DBG_CPU0_CMD_BREAD32;
455 }
456 break;
457 default:
458 LOG_ERROR("Illegal debug chain selected (%i) while doing burst read",
459 jtag_info->or1k_jtag_module_selected);
460 return ERROR_FAIL;
461 }
462
463 int total_size_bytes = count * size;
464 struct scan_field field;
465 uint8_t *in_buffer = malloc(total_size_bytes + CRC_LEN + STATUS_BYTES);
466
467 retry_read_full:
468
469 /* Send the BURST READ command, returns TAP to idle state */
470 retval = adbg_burst_command(jtag_info, opcode, start_address, count);
471 if (retval != ERROR_OK)
472 goto out;
473
474 field.num_bits = (total_size_bytes + CRC_LEN + STATUS_BYTES) * 8;
475 field.out_value = NULL;
476 field.in_value = in_buffer;
477
478 jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
479
480 retval = jtag_execute_queue();
481 if (retval != ERROR_OK)
482 goto out;
483
484 /* Look for the start bit in the first (STATUS_BYTES * 8) bits */
485 int shift = find_status_bit(in_buffer, STATUS_BYTES);
486
487 /* We expect the status bit to be in the first byte */
488 if (shift < 0) {
489 if (retry_full_busy++ < MAX_READ_BUSY_RETRY) {
490 LOG_WARNING("Burst read timed out");
491 goto retry_read_full;
492 } else {
493 LOG_ERROR("Burst read failed");
494 retval = ERROR_FAIL;
495 goto out;
496 }
497 }
498
499 buffer_shr(in_buffer, total_size_bytes + CRC_LEN + STATUS_BYTES, shift);
500
501 uint32_t crc_read;
502 memcpy(data, in_buffer, total_size_bytes);
503 memcpy(&crc_read, &in_buffer[total_size_bytes], 4);
504
505 uint32_t crc_calc = crc32_le(CRC32_POLY_LE, 0xffffffff, data,
506 total_size_bytes);
507
508 if (crc_calc != crc_read) {
509 LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32 ", read CRC 0x%08" PRIx32, crc_calc, crc_read);
510 if (retry_full_crc++ < MAX_READ_CRC_RETRY)
511 goto retry_read_full;
512 else {
513 LOG_ERROR("Burst read failed");
514 retval = ERROR_FAIL;
515 goto out;
516 }
517 } else
518 LOG_DEBUG("CRC OK!");
519
520 /* Now, read the error register, and retry/recompute as necessary */
521 if (jtag_info->or1k_jtag_module_selected == DC_WISHBONE &&
522 !(or1k_du_adv.options & ADBG_USE_HISPEED)) {
523
524 uint32_t err_data[2] = {0, 0};
525 uint32_t addr;
526 int bus_error_retries = 0;
527
528 /* First, just get 1 bit...read address only if necessary */
529 retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
530 if (retval != ERROR_OK)
531 goto out;
532
533 /* Then we have a problem */
534 if (err_data[0] & 0x1) {
535
536 retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 33);
537 if (retval != ERROR_OK)
538 goto out;
539
540 addr = (err_data[0] >> 1) | (err_data[1] << 31);
541 LOG_WARNING("WB bus error during burst read, address 0x%08" PRIx32 ", retrying!", addr);
542
543 bus_error_retries++;
544 if (bus_error_retries > MAX_BUS_ERRORS) {
545 LOG_ERROR("Max WB bus errors reached during burst read");
546 retval = ERROR_FAIL;
547 goto out;
548 }
549
550 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
551 /* Write 1 bit, to reset the error register */
552 err_data[0] = 1;
553 retval = adbg_ctrl_write(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
554 if (retval != ERROR_OK)
555 goto out;
556
557 goto retry_read_full;
558 }
559 }
560
561 out:
562 free(in_buffer);
563
564 return retval;
565 }
566
567 /* Set up and execute a burst write to a contiguous set of addresses */
568 static int adbg_wb_burst_write(struct or1k_jtag *jtag_info, const uint8_t *data, int size,
569 int count, unsigned long start_address)
570 {
571 int retry_full_crc = 0;
572 int retval;
573 uint8_t opcode;
574
575 LOG_DEBUG("Doing burst write, word size %d, word count %d,"
576 "start address 0x%08lx", size, count, start_address);
577
578 /* Select the appropriate opcode */
579 switch (jtag_info->or1k_jtag_module_selected) {
580 case DC_WISHBONE:
581 if (size == 1)
582 opcode = DBG_WB_CMD_BWRITE8;
583 else if (size == 2)
584 opcode = DBG_WB_CMD_BWRITE16;
585 else if (size == 4)
586 opcode = DBG_WB_CMD_BWRITE32;
587 else {
588 LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
589 "defaulting to 4-byte words", size);
590 opcode = DBG_WB_CMD_BWRITE32;
591 }
592 break;
593 case DC_CPU0:
594 if (size == 4)
595 opcode = DBG_CPU0_CMD_BWRITE32;
596 else {
597 LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
598 "defaulting to 4-byte words", size);
599 opcode = DBG_CPU0_CMD_BWRITE32;
600 }
601 break;
602 case DC_CPU1:
603 if (size == 4)
604 opcode = DBG_CPU1_CMD_BWRITE32;
605 else {
606 LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
607 "defaulting to 4-byte words", size);
608 opcode = DBG_CPU0_CMD_BWRITE32;
609 }
610 break;
611 default:
612 LOG_ERROR("Illegal debug chain selected (%i) while doing burst write",
613 jtag_info->or1k_jtag_module_selected);
614 return ERROR_FAIL;
615 }
616
617 retry_full_write:
618
619 /* Send the BURST WRITE command, returns TAP to idle state */
620 retval = adbg_burst_command(jtag_info, opcode, start_address, count);
621 if (retval != ERROR_OK)
622 return retval;
623
624 struct scan_field field[3];
625
626 /* Write a start bit so it knows when to start counting */
627 uint8_t value = 1;
628 field[0].num_bits = 1;
629 field[0].out_value = &value;
630 field[0].in_value = NULL;
631
632 uint32_t crc_calc = crc32_le(CRC32_POLY_LE, 0xffffffff, data,
633 count * size);
634
635 field[1].num_bits = count * size * 8;
636 field[1].out_value = data;
637 field[1].in_value = NULL;
638
639 field[2].num_bits = 32;
640 field[2].out_value = (uint8_t *)&crc_calc;
641 field[2].in_value = NULL;
642
643 jtag_add_dr_scan(jtag_info->tap, 3, field, TAP_DRSHIFT);
644
645 /* Read the 'CRC match' bit, and go to idle */
646 field[0].num_bits = 1;
647 field[0].out_value = NULL;
648 field[0].in_value = &value;
649 jtag_add_dr_scan(jtag_info->tap, 1, field, TAP_IDLE);
650
651 retval = jtag_execute_queue();
652 if (retval != ERROR_OK)
653 return retval;
654
655 if (!value) {
656 LOG_WARNING("CRC ERROR! match bit after write is %" PRIi8 " (computed CRC 0x%08" PRIx32 ")", value, crc_calc);
657 if (retry_full_crc++ < MAX_WRITE_CRC_RETRY)
658 goto retry_full_write;
659 else
660 return ERROR_FAIL;
661 } else
662 LOG_DEBUG("CRC OK!\n");
663
664 /* Now, read the error register, and retry/recompute as necessary */
665 if (jtag_info->or1k_jtag_module_selected == DC_WISHBONE &&
666 !(or1k_du_adv.options & ADBG_USE_HISPEED)) {
667 uint32_t addr;
668 int bus_error_retries = 0;
669 uint32_t err_data[2] = {0, 0};
670
671 /* First, just get 1 bit...read address only if necessary */
672 retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
673 if (retval != ERROR_OK)
674 return retval;
675
676 /* Then we have a problem */
677 if (err_data[0] & 0x1) {
678
679 retval = adbg_ctrl_read(jtag_info, DBG_WB_REG_ERROR, err_data, 33);
680 if (retval != ERROR_OK)
681 return retval;
682
683 addr = (err_data[0] >> 1) | (err_data[1] << 31);
684 LOG_WARNING("WB bus error during burst write, address 0x%08" PRIx32 ", retrying!", addr);
685
686 bus_error_retries++;
687 if (bus_error_retries > MAX_BUS_ERRORS) {
688 LOG_ERROR("Max WB bus errors reached during burst read");
689 retval = ERROR_FAIL;
690 return retval;
691 }
692
693 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
694 /* Write 1 bit, to reset the error register */
695 err_data[0] = 1;
696 retval = adbg_ctrl_write(jtag_info, DBG_WB_REG_ERROR, err_data, 1);
697 if (retval != ERROR_OK)
698 return retval;
699
700 goto retry_full_write;
701 }
702 }
703
704 return ERROR_OK;
705 }
706
707 /* Currently hard set in functions to 32-bits */
708 static int or1k_adv_jtag_read_cpu(struct or1k_jtag *jtag_info,
709 uint32_t addr, int count, uint32_t *value)
710 {
711 int retval;
712 if (!jtag_info->or1k_jtag_inited) {
713 retval = or1k_adv_jtag_init(jtag_info);
714 if (retval != ERROR_OK)
715 return retval;
716 }
717
718 retval = adbg_select_module(jtag_info, DC_CPU0);
719 if (retval != ERROR_OK)
720 return retval;
721
722 return adbg_wb_burst_read(jtag_info, 4, count, addr, (uint8_t *)value);
723 }
724
725 static int or1k_adv_jtag_write_cpu(struct or1k_jtag *jtag_info,
726 uint32_t addr, int count, const uint32_t *value)
727 {
728 int retval;
729 if (!jtag_info->or1k_jtag_inited) {
730 retval = or1k_adv_jtag_init(jtag_info);
731 if (retval != ERROR_OK)
732 return retval;
733 }
734
735 retval = adbg_select_module(jtag_info, DC_CPU0);
736 if (retval != ERROR_OK)
737 return retval;
738
739 return adbg_wb_burst_write(jtag_info, (uint8_t *)value, 4, count, addr);
740 }
741
742 static int or1k_adv_cpu_stall(struct or1k_jtag *jtag_info, int action)
743 {
744 int retval;
745 if (!jtag_info->or1k_jtag_inited) {
746 retval = or1k_adv_jtag_init(jtag_info);
747 if (retval != ERROR_OK)
748 return retval;
749 }
750
751 retval = adbg_select_module(jtag_info, DC_CPU0);
752 if (retval != ERROR_OK)
753 return retval;
754
755 uint32_t cpu_cr;
756 retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
757 if (retval != ERROR_OK)
758 return retval;
759
760 if (action == CPU_STALL)
761 cpu_cr |= DBG_CPU_CR_STALL;
762 else
763 cpu_cr &= ~DBG_CPU_CR_STALL;
764
765 retval = adbg_select_module(jtag_info, DC_CPU0);
766 if (retval != ERROR_OK)
767 return retval;
768
769 return adbg_ctrl_write(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
770 }
771
772 static int or1k_adv_is_cpu_running(struct or1k_jtag *jtag_info, int *running)
773 {
774 int retval;
775 if (!jtag_info->or1k_jtag_inited) {
776 retval = or1k_adv_jtag_init(jtag_info);
777 if (retval != ERROR_OK)
778 return retval;
779 }
780
781 int current = jtag_info->or1k_jtag_module_selected;
782
783 retval = adbg_select_module(jtag_info, DC_CPU0);
784 if (retval != ERROR_OK)
785 return retval;
786
787 uint32_t cpu_cr = 0;
788 retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
789 if (retval != ERROR_OK)
790 return retval;
791
792 if (cpu_cr & DBG_CPU_CR_STALL)
793 *running = 0;
794 else
795 *running = 1;
796
797 if (current != DC_NONE) {
798 retval = adbg_select_module(jtag_info, current);
799 if (retval != ERROR_OK)
800 return retval;
801 }
802
803 return ERROR_OK;
804 }
805
806 static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
807 {
808 int retval;
809 if (!jtag_info->or1k_jtag_inited) {
810 retval = or1k_adv_jtag_init(jtag_info);
811 if (retval != ERROR_OK)
812 return retval;
813 }
814
815 retval = adbg_select_module(jtag_info, DC_CPU0);
816 if (retval != ERROR_OK)
817 return retval;
818
819 uint32_t cpu_cr;
820 retval = adbg_ctrl_read(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
821 if (retval != ERROR_OK)
822 return retval;
823
824 if (action == CPU_RESET)
825 cpu_cr |= DBG_CPU_CR_RESET;
826 else
827 cpu_cr &= ~DBG_CPU_CR_RESET;
828
829 retval = adbg_select_module(jtag_info, DC_CPU0);
830 if (retval != ERROR_OK)
831 return retval;
832
833 return adbg_ctrl_write(jtag_info, DBG_CPU0_REG_STATUS, &cpu_cr, 2);
834 }
835
836 static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
837 uint32_t addr, uint32_t size, int count, uint8_t *buffer)
838 {
839 LOG_DEBUG("Reading WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
840
841 int retval;
842 if (!jtag_info->or1k_jtag_inited) {
843 retval = or1k_adv_jtag_init(jtag_info);
844 if (retval != ERROR_OK)
845 return retval;
846 }
847
848 retval = adbg_select_module(jtag_info, DC_WISHBONE);
849 if (retval != ERROR_OK)
850 return retval;
851
852 int block_count_left = count;
853 uint32_t block_count_address = addr;
854 uint8_t *block_count_buffer = buffer;
855
856 while (block_count_left) {
857
858 int blocks_this_round = (block_count_left > MAX_BURST_SIZE) ?
859 MAX_BURST_SIZE : block_count_left;
860
861 retval = adbg_wb_burst_read(jtag_info, size, blocks_this_round,
862 block_count_address, block_count_buffer);
863 if (retval != ERROR_OK)
864 return retval;
865
866 block_count_left -= blocks_this_round;
867 block_count_address += size * MAX_BURST_SIZE;
868 block_count_buffer += size * MAX_BURST_SIZE;
869 }
870
871 /* The adv_debug_if always return words and half words in
872 * little-endian order no matter what the target endian is.
873 * So if the target endian is big, change the order.
874 */
875
876 struct target *target = jtag_info->target;
877 if ((target->endianness == TARGET_BIG_ENDIAN) && (size != 1)) {
878 switch (size) {
879 case 4:
880 buf_bswap32(buffer, buffer, size * count);
881 break;
882 case 2:
883 buf_bswap16(buffer, buffer, size * count);
884 break;
885 }
886 }
887
888 return ERROR_OK;
889 }
890
891 static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
892 uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
893 {
894 LOG_DEBUG("Writing WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
895
896 int retval;
897 if (!jtag_info->or1k_jtag_inited) {
898 retval = or1k_adv_jtag_init(jtag_info);
899 if (retval != ERROR_OK)
900 return retval;
901 }
902
903 retval = adbg_select_module(jtag_info, DC_WISHBONE);
904 if (retval != ERROR_OK)
905 return retval;
906
907 /* The adv_debug_if wants words and half words in little-endian
908 * order no matter what the target endian is. So if the target
909 * endian is big, change the order.
910 */
911
912 void *t = NULL;
913 struct target *target = jtag_info->target;
914 if ((target->endianness == TARGET_BIG_ENDIAN) && (size != 1)) {
915 t = calloc(count * size, sizeof(uint8_t));
916 if (!t) {
917 LOG_ERROR("Out of memory");
918 return ERROR_FAIL;
919 }
920
921 switch (size) {
922 case 4:
923 buf_bswap32(t, buffer, size * count);
924 break;
925 case 2:
926 buf_bswap16(t, buffer, size * count);
927 break;
928 default:
929 free(t);
930 return ERROR_TARGET_FAILURE;
931 }
932 buffer = t;
933 }
934
935 int block_count_left = count;
936 uint32_t block_count_address = addr;
937 uint8_t *block_count_buffer = (uint8_t *)buffer;
938
939 while (block_count_left) {
940
941 int blocks_this_round = (block_count_left > MAX_BURST_SIZE) ?
942 MAX_BURST_SIZE : block_count_left;
943
944 retval = adbg_wb_burst_write(jtag_info, block_count_buffer,
945 size, blocks_this_round,
946 block_count_address);
947 if (retval != ERROR_OK) {
948 free(t);
949 return retval;
950 }
951
952 block_count_left -= blocks_this_round;
953 block_count_address += size * MAX_BURST_SIZE;
954 block_count_buffer += size * MAX_BURST_SIZE;
955 }
956
957 free(t);
958 return ERROR_OK;
959 }
960
961 int or1k_adv_jtag_jsp_xfer(struct or1k_jtag *jtag_info,
962 int *out_len, unsigned char *out_buffer,
963 int *in_len, unsigned char *in_buffer)
964 {
965 LOG_DEBUG("JSP transfer");
966
967 int retval;
968 if (!jtag_info->or1k_jtag_inited)
969 return ERROR_OK;
970
971 retval = adbg_select_module(jtag_info, DC_JSP);
972 if (retval != ERROR_OK)
973 return retval;
974
975 /* return nb char xmit */
976 int xmitsize;
977 if (*out_len > 8)
978 xmitsize = 8;
979 else
980 xmitsize = *out_len;
981
982 uint8_t out_data[10];
983 uint8_t in_data[10];
984 struct scan_field field;
985 int startbit, stopbit, wrapbit;
986
987 memset(out_data, 0, 10);
988
989 if (or1k_du_adv.options & ENABLE_JSP_MULTI) {
990
991 startbit = 1;
992 wrapbit = (xmitsize >> 3) & 0x1;
993 out_data[0] = (xmitsize << 5) | 0x1; /* set the start bit */
994
995 int i;
996 /* don't copy off the end of the input array */
997 for (i = 0; i < xmitsize; i++) {
998 out_data[i + 1] = (out_buffer[i] << 1) | wrapbit;
999 wrapbit = (out_buffer[i] >> 7) & 0x1;
1000 }
1001
1002 if (i < 8)
1003 out_data[i + 1] = wrapbit;
1004 else
1005 out_data[9] = wrapbit;
1006
1007 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1008 * won't treat the burst as a 'module select' command.
1009 */
1010 stopbit = !!(out_data[9] & 0x01);
1011
1012 } else {
1013 startbit = 0;
1014 /* First byte out has write count in upper nibble */
1015 out_data[0] = 0x0 | (xmitsize << 4);
1016 if (xmitsize > 0)
1017 memcpy(&out_data[1], out_buffer, xmitsize);
1018
1019 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1020 * won't treat the burst as a 'module select' command.
1021 */
1022 stopbit = !!(out_data[8] & 0x80);
1023 }
1024
1025 field.num_bits = 72 + startbit + stopbit;
1026 field.out_value = out_data;
1027 field.in_value = in_data;
1028
1029 jtag_add_dr_scan(jtag_info->tap, 1, &field, TAP_IDLE);
1030
1031 retval = jtag_execute_queue();
1032 if (retval != ERROR_OK)
1033 return retval;
1034
1035 /* bytes available is in the upper nibble */
1036 *in_len = (in_data[0] >> 4) & 0xF;
1037 memcpy(in_buffer, &in_data[1], *in_len);
1038
1039 int bytes_free = in_data[0] & 0x0F;
1040 *out_len = (bytes_free < xmitsize) ? bytes_free : xmitsize;
1041
1042 return ERROR_OK;
1043 }
1044
1045 static struct or1k_du or1k_du_adv = {
1046 .name = "adv",
1047 .options = NO_OPTION,
1048 .or1k_jtag_init = or1k_adv_jtag_init,
1049
1050 .or1k_is_cpu_running = or1k_adv_is_cpu_running,
1051 .or1k_cpu_stall = or1k_adv_cpu_stall,
1052 .or1k_cpu_reset = or1k_adv_cpu_reset,
1053
1054 .or1k_jtag_read_cpu = or1k_adv_jtag_read_cpu,
1055 .or1k_jtag_write_cpu = or1k_adv_jtag_write_cpu,
1056
1057 .or1k_jtag_read_memory = or1k_adv_jtag_read_memory,
1058 .or1k_jtag_write_memory = or1k_adv_jtag_write_memory
1059 };
1060
1061 int or1k_du_adv_register(void)
1062 {
1063 list_add_tail(&or1k_du_adv.list, &du_list);
1064 return 0;
1065 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)