1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target
*target
,
56 uint32_t num
, uint32_t value
);
57 static void cortex_m_dwt_free(struct target
*target
);
59 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
60 uint32_t *value
, int regnum
)
62 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target
->dbg_msg_enabled
) {
69 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
70 if (retval
!= ERROR_OK
)
74 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
75 if (retval
!= ERROR_OK
)
78 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
79 if (retval
!= ERROR_OK
)
82 if (target
->dbg_msg_enabled
) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
92 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
93 uint32_t value
, int regnum
)
95 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target
->dbg_msg_enabled
) {
102 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
103 if (retval
!= ERROR_OK
)
107 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
108 if (retval
!= ERROR_OK
)
111 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
112 if (retval
!= ERROR_OK
)
115 if (target
->dbg_msg_enabled
) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
125 static int cortex_m_write_debug_halt_mask(struct target
*target
,
126 uint32_t mask_on
, uint32_t mask_off
)
128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
131 /* mask off status bits */
132 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
133 /* create new register mask */
134 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
136 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
139 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
141 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
142 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
143 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
148 static int cortex_m_set_maskints_for_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 switch (cortex_m
->isrmasking_mode
) {
152 case CORTEX_M_ISRMASK_AUTO
:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target
, false);
156 case CORTEX_M_ISRMASK_OFF
:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target
, false);
160 case CORTEX_M_ISRMASK_ON
:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target
, true);
164 case CORTEX_M_ISRMASK_STEPONLY
:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
172 static int cortex_m_set_maskints_for_run(struct target
*target
)
174 switch (target_to_cm(target
)->isrmasking_mode
) {
175 case CORTEX_M_ISRMASK_AUTO
:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target
, false);
179 case CORTEX_M_ISRMASK_OFF
:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target
, false);
183 case CORTEX_M_ISRMASK_ON
:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target
, true);
187 case CORTEX_M_ISRMASK_STEPONLY
:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target
, false);
194 static int cortex_m_set_maskints_for_step(struct target
*target
)
196 switch (target_to_cm(target
)->isrmasking_mode
) {
197 case CORTEX_M_ISRMASK_AUTO
:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target
, true);
201 case CORTEX_M_ISRMASK_OFF
:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target
, false);
205 case CORTEX_M_ISRMASK_ON
:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target
, true);
209 case CORTEX_M_ISRMASK_STEPONLY
:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target
, true);
216 static int cortex_m_clear_halt(struct target
*target
)
218 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
219 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
225 /* Read Debug Fault Status Register */
226 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
227 if (retval
!= ERROR_OK
)
230 /* Clear Debug Fault Status */
231 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
232 if (retval
!= ERROR_OK
)
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
239 static int cortex_m_single_step_core(struct target
*target
)
241 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
242 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
249 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
250 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
251 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
252 if (retval
!= ERROR_OK
)
255 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
256 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
257 if (retval
!= ERROR_OK
)
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target
);
267 static int cortex_m_enable_fpb(struct target
*target
)
269 int retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 /* check the fpb is actually enabled */
275 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
276 if (retval
!= ERROR_OK
)
285 static int cortex_m_endreset_event(struct target
*target
)
290 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
291 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
292 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
293 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
294 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
298 if (retval
!= ERROR_OK
)
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
302 /* this register is used for emulated dcc channel */
303 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
304 if (retval
!= ERROR_OK
)
307 /* Enable debug requests */
308 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
309 if (retval
!= ERROR_OK
)
311 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
312 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
313 if (retval
!= ERROR_OK
)
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target
);
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
327 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
328 if (retval
!= ERROR_OK
)
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
336 retval
= cortex_m_enable_fpb(target
);
337 if (retval
!= ERROR_OK
) {
338 LOG_ERROR("Failed to enable the FPB");
342 cortex_m
->fpb_enabled
= true;
344 /* Restore FPB registers */
345 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
346 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
347 if (retval
!= ERROR_OK
)
351 /* Restore DWT registers */
352 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
353 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
355 if (retval
!= ERROR_OK
)
357 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
359 if (retval
!= ERROR_OK
)
361 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
362 dwt_list
[i
].function
);
363 if (retval
!= ERROR_OK
)
366 retval
= dap_run(swjdp
);
367 if (retval
!= ERROR_OK
)
370 register_cache_invalidate(armv7m
->arm
.core_cache
);
372 /* make sure we have latest dhcsr flags */
373 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
378 static int cortex_m_examine_debug_reason(struct target
*target
)
380 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
385 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
386 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
387 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
388 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
389 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
390 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
391 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
392 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
393 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
394 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
395 else /* EXTERNAL, HALTED */
396 target
->debug_reason
= DBG_REASON_UNDEFINED
;
402 static int cortex_m_examine_exception_reason(struct target
*target
)
404 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
405 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
406 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
409 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
410 if (retval
!= ERROR_OK
)
412 switch (armv7m
->exception_number
) {
415 case 3: /* Hard Fault */
416 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
417 if (retval
!= ERROR_OK
)
419 if (except_sr
& 0x40000000) {
420 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
421 if (retval
!= ERROR_OK
)
425 case 4: /* Memory Management */
426 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
427 if (retval
!= ERROR_OK
)
429 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
430 if (retval
!= ERROR_OK
)
433 case 5: /* Bus Fault */
434 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
435 if (retval
!= ERROR_OK
)
437 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
438 if (retval
!= ERROR_OK
)
441 case 6: /* Usage Fault */
442 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
443 if (retval
!= ERROR_OK
)
446 case 11: /* SVCall */
448 case 12: /* Debug Monitor */
449 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
450 if (retval
!= ERROR_OK
)
453 case 14: /* PendSV */
455 case 15: /* SysTick */
461 retval
= dap_run(swjdp
);
462 if (retval
== ERROR_OK
)
463 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
464 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
465 armv7m_exception_string(armv7m
->exception_number
),
466 shcsr
, except_sr
, cfsr
, except_ar
);
470 static int cortex_m_debug_entry(struct target
*target
)
475 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
476 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
477 struct arm
*arm
= &armv7m
->arm
;
482 /* Do this really early to minimize the window where the MASKINTS erratum
483 * can pile up pending interrupts. */
484 cortex_m_set_maskints_for_halt(target
);
486 cortex_m_clear_halt(target
);
487 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
488 if (retval
!= ERROR_OK
)
491 retval
= armv7m
->examine_debug_reason(target
);
492 if (retval
!= ERROR_OK
)
495 /* Examine target state and mode
496 * First load register accessible through core debug port */
497 int num_regs
= arm
->core_cache
->num_regs
;
499 for (i
= 0; i
< num_regs
; i
++) {
500 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
502 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
506 xPSR
= buf_get_u32(r
->value
, 0, 32);
508 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
511 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
514 /* Are we in an exception handler */
516 armv7m
->exception_number
= (xPSR
& 0x1FF);
518 arm
->core_mode
= ARM_MODE_HANDLER
;
519 arm
->map
= armv7m_msp_reg_map
;
521 unsigned control
= buf_get_u32(arm
->core_cache
522 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
524 /* is this thread privileged? */
525 arm
->core_mode
= control
& 1
526 ? ARM_MODE_USER_THREAD
529 /* which stack is it using? */
531 arm
->map
= armv7m_psp_reg_map
;
533 arm
->map
= armv7m_msp_reg_map
;
535 armv7m
->exception_number
= 0;
538 if (armv7m
->exception_number
)
539 cortex_m_examine_exception_reason(target
);
541 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
542 arm_mode_name(arm
->core_mode
),
543 buf_get_u32(arm
->pc
->value
, 0, 32),
544 target_state_name(target
));
546 if (armv7m
->post_debug_entry
) {
547 retval
= armv7m
->post_debug_entry(target
);
548 if (retval
!= ERROR_OK
)
555 static int cortex_m_poll(struct target
*target
)
557 int detected_failure
= ERROR_OK
;
558 int retval
= ERROR_OK
;
559 enum target_state prev_target_state
= target
->state
;
560 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
561 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
563 /* Read from Debug Halting Control and Status Register */
564 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
565 if (retval
!= ERROR_OK
) {
566 target
->state
= TARGET_UNKNOWN
;
570 /* Recover from lockup. See ARMv7-M architecture spec,
571 * section B1.5.15 "Unrecoverable exception cases".
573 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
574 LOG_ERROR("%s -- clearing lockup after double fault",
575 target_name(target
));
576 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
577 target
->debug_reason
= DBG_REASON_DBGRQ
;
579 /* We have to execute the rest (the "finally" equivalent, but
580 * still throw this exception again).
582 detected_failure
= ERROR_FAIL
;
584 /* refresh status bits */
585 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
586 if (retval
!= ERROR_OK
)
590 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
591 if (target
->state
!= TARGET_RESET
) {
592 target
->state
= TARGET_RESET
;
593 LOG_INFO("%s: external reset detected", target_name(target
));
598 if (target
->state
== TARGET_RESET
) {
599 /* Cannot switch context while running so endreset is
600 * called with target->state == TARGET_RESET
602 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
603 cortex_m
->dcb_dhcsr
);
604 retval
= cortex_m_endreset_event(target
);
605 if (retval
!= ERROR_OK
) {
606 target
->state
= TARGET_UNKNOWN
;
609 target
->state
= TARGET_RUNNING
;
610 prev_target_state
= TARGET_RUNNING
;
613 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
614 target
->state
= TARGET_HALTED
;
616 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
617 retval
= cortex_m_debug_entry(target
);
618 if (retval
!= ERROR_OK
)
621 if (arm_semihosting(target
, &retval
) != 0)
624 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
626 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
628 retval
= cortex_m_debug_entry(target
);
629 if (retval
!= ERROR_OK
)
632 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
636 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
637 * How best to model low power modes?
640 if (target
->state
== TARGET_UNKNOWN
) {
641 /* check if processor is retiring instructions */
642 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
643 target
->state
= TARGET_RUNNING
;
648 /* Check that target is truly halted, since the target could be resumed externally */
649 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
650 /* registers are now invalid */
651 register_cache_invalidate(armv7m
->arm
.core_cache
);
653 target
->state
= TARGET_RUNNING
;
654 LOG_WARNING("%s: external resume detected", target_name(target
));
655 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
659 /* Did we detect a failure condition that we cleared? */
660 if (detected_failure
!= ERROR_OK
)
661 retval
= detected_failure
;
665 static int cortex_m_halt(struct target
*target
)
667 LOG_DEBUG("target->state: %s",
668 target_state_name(target
));
670 if (target
->state
== TARGET_HALTED
) {
671 LOG_DEBUG("target was already halted");
675 if (target
->state
== TARGET_UNKNOWN
)
676 LOG_WARNING("target was in unknown state when halt was requested");
678 if (target
->state
== TARGET_RESET
) {
679 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
680 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
681 return ERROR_TARGET_FAILURE
;
683 /* we came here in a reset_halt or reset_init sequence
684 * debug entry was already prepared in cortex_m3_assert_reset()
686 target
->debug_reason
= DBG_REASON_DBGRQ
;
692 /* Write to Debug Halting Control and Status Register */
693 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
695 /* Do this really early to minimize the window where the MASKINTS erratum
696 * can pile up pending interrupts. */
697 cortex_m_set_maskints_for_halt(target
);
699 target
->debug_reason
= DBG_REASON_DBGRQ
;
704 static int cortex_m_soft_reset_halt(struct target
*target
)
706 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
707 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
708 uint32_t dcb_dhcsr
= 0;
709 int retval
, timeout
= 0;
711 /* soft_reset_halt is deprecated on cortex_m as the same functionality
712 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
713 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
714 * core, not the peripherals */
715 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
717 /* Enter debug state on reset; restore DEMCR in endreset_event() */
718 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
719 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
720 if (retval
!= ERROR_OK
)
723 /* Request a core-only reset */
724 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
725 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
726 if (retval
!= ERROR_OK
)
728 target
->state
= TARGET_RESET
;
730 /* registers are now invalid */
731 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
733 while (timeout
< 100) {
734 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
735 if (retval
== ERROR_OK
) {
736 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
737 &cortex_m
->nvic_dfsr
);
738 if (retval
!= ERROR_OK
)
740 if ((dcb_dhcsr
& S_HALT
)
741 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
742 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
744 (unsigned) dcb_dhcsr
,
745 (unsigned) cortex_m
->nvic_dfsr
);
746 cortex_m_poll(target
);
747 /* FIXME restore user's vector catch config */
750 LOG_DEBUG("waiting for system reset-halt, "
751 "DHCSR 0x%08x, %d ms",
752 (unsigned) dcb_dhcsr
, timeout
);
761 void cortex_m_enable_breakpoints(struct target
*target
)
763 struct breakpoint
*breakpoint
= target
->breakpoints
;
765 /* set any pending breakpoints */
767 if (!breakpoint
->set
)
768 cortex_m_set_breakpoint(target
, breakpoint
);
769 breakpoint
= breakpoint
->next
;
773 static int cortex_m_resume(struct target
*target
, int current
,
774 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
776 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
777 struct breakpoint
*breakpoint
= NULL
;
781 if (target
->state
!= TARGET_HALTED
) {
782 LOG_WARNING("target not halted");
783 return ERROR_TARGET_NOT_HALTED
;
786 if (!debug_execution
) {
787 target_free_all_working_areas(target
);
788 cortex_m_enable_breakpoints(target
);
789 cortex_m_enable_watchpoints(target
);
792 if (debug_execution
) {
793 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
795 /* Disable interrupts */
796 /* We disable interrupts in the PRIMASK register instead of
797 * masking with C_MASKINTS. This is probably the same issue
798 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
799 * in parallel with disabled interrupts can cause local faults
802 * REVISIT this clearly breaks non-debug execution, since the
803 * PRIMASK register state isn't saved/restored... workaround
804 * by never resuming app code after debug execution.
806 buf_set_u32(r
->value
, 0, 1, 1);
810 /* Make sure we are in Thumb mode */
811 r
= armv7m
->arm
.cpsr
;
812 buf_set_u32(r
->value
, 24, 1, 1);
817 /* current = 1: continue on current pc, otherwise continue at <address> */
820 buf_set_u32(r
->value
, 0, 32, address
);
825 /* if we halted last time due to a bkpt instruction
826 * then we have to manually step over it, otherwise
827 * the core will break again */
829 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
831 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
833 resume_pc
= buf_get_u32(r
->value
, 0, 32);
835 armv7m_restore_context(target
);
837 /* the front-end may request us not to handle breakpoints */
838 if (handle_breakpoints
) {
839 /* Single step past breakpoint at current address */
840 breakpoint
= breakpoint_find(target
, resume_pc
);
842 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
844 breakpoint
->unique_id
);
845 cortex_m_unset_breakpoint(target
, breakpoint
);
846 cortex_m_single_step_core(target
);
847 cortex_m_set_breakpoint(target
, breakpoint
);
852 cortex_m_set_maskints_for_run(target
);
853 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
855 target
->debug_reason
= DBG_REASON_NOTHALTED
;
857 /* registers are now invalid */
858 register_cache_invalidate(armv7m
->arm
.core_cache
);
860 if (!debug_execution
) {
861 target
->state
= TARGET_RUNNING
;
862 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
863 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
865 target
->state
= TARGET_DEBUG_RUNNING
;
866 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
867 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
873 /* int irqstepcount = 0; */
874 static int cortex_m_step(struct target
*target
, int current
,
875 target_addr_t address
, int handle_breakpoints
)
877 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
878 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
879 struct breakpoint
*breakpoint
= NULL
;
880 struct reg
*pc
= armv7m
->arm
.pc
;
881 bool bkpt_inst_found
= false;
883 bool isr_timed_out
= false;
885 if (target
->state
!= TARGET_HALTED
) {
886 LOG_WARNING("target not halted");
887 return ERROR_TARGET_NOT_HALTED
;
890 /* current = 1: continue on current pc, otherwise continue at <address> */
892 buf_set_u32(pc
->value
, 0, 32, address
);
894 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
896 /* the front-end may request us not to handle breakpoints */
897 if (handle_breakpoints
) {
898 breakpoint
= breakpoint_find(target
, pc_value
);
900 cortex_m_unset_breakpoint(target
, breakpoint
);
903 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
905 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
907 armv7m_restore_context(target
);
909 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
911 /* if no bkpt instruction is found at pc then we can perform
912 * a normal step, otherwise we have to manually step over the bkpt
913 * instruction - as such simulate a step */
914 if (bkpt_inst_found
== false) {
915 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
)) {
916 /* Automatic ISR masking mode off: Just step over the next
917 * instruction, with interrupts on or off as appropriate. */
918 cortex_m_set_maskints_for_step(target
);
919 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
921 /* Process interrupts during stepping in a way they don't interfere
926 * Set a temporary break point at the current pc and let the core run
927 * with interrupts enabled. Pending interrupts get served and we run
928 * into the breakpoint again afterwards. Then we step over the next
929 * instruction with interrupts disabled.
931 * If the pending interrupts don't complete within time, we leave the
932 * core running. This may happen if the interrupts trigger faster
933 * than the core can process them or the handler doesn't return.
935 * If no more breakpoints are available we simply do a step with
936 * interrupts enabled.
942 * If a break point is already set on the lower half word then a break point on
943 * the upper half word will not break again when the core is restarted. So we
944 * just step over the instruction with interrupts disabled.
946 * The documentation has no information about this, it was found by observation
947 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
948 * suffer from this problem.
950 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
951 * address has it always cleared. The former is done to indicate thumb mode
955 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
956 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
957 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
958 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
959 /* Re-enable interrupts if appropriate */
960 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
961 cortex_m_set_maskints_for_halt(target
);
965 /* Set a temporary break point */
967 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
969 enum breakpoint_type type
= BKPT_HARD
;
970 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
971 /* FPB rev.1 cannot handle such addr, try BKPT instr */
974 retval
= breakpoint_add(target
, pc_value
, 2, type
);
977 bool tmp_bp_set
= (retval
== ERROR_OK
);
979 /* No more breakpoints left, just do a step */
981 cortex_m_set_maskints_for_step(target
);
982 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
983 /* Re-enable interrupts if appropriate */
984 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
985 cortex_m_set_maskints_for_halt(target
);
988 LOG_DEBUG("Starting core to serve pending interrupts");
989 int64_t t_start
= timeval_ms();
990 cortex_m_set_maskints_for_run(target
);
991 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
993 /* Wait for pending handlers to complete or timeout */
995 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
997 &cortex_m
->dcb_dhcsr
);
998 if (retval
!= ERROR_OK
) {
999 target
->state
= TARGET_UNKNOWN
;
1002 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1003 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1005 /* only remove breakpoint if we created it */
1007 cortex_m_unset_breakpoint(target
, breakpoint
);
1009 /* Remove the temporary breakpoint */
1010 breakpoint_remove(target
, pc_value
);
1013 if (isr_timed_out
) {
1014 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1015 "leaving target running");
1017 /* Step over next instruction with interrupts disabled */
1018 cortex_m_set_maskints_for_step(target
);
1019 cortex_m_write_debug_halt_mask(target
,
1020 C_HALT
| C_MASKINTS
,
1022 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1023 /* Re-enable interrupts if appropriate */
1024 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1025 cortex_m_set_maskints_for_halt(target
);
1032 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1033 if (retval
!= ERROR_OK
)
1036 /* registers are now invalid */
1037 register_cache_invalidate(armv7m
->arm
.core_cache
);
1040 cortex_m_set_breakpoint(target
, breakpoint
);
1042 if (isr_timed_out
) {
1043 /* Leave the core running. The user has to stop execution manually. */
1044 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1045 target
->state
= TARGET_RUNNING
;
1049 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1050 " nvic_icsr = 0x%" PRIx32
,
1051 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1053 retval
= cortex_m_debug_entry(target
);
1054 if (retval
!= ERROR_OK
)
1056 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1058 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1059 " nvic_icsr = 0x%" PRIx32
,
1060 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1065 static int cortex_m_assert_reset(struct target
*target
)
1067 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1068 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1069 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1071 LOG_DEBUG("target->state: %s",
1072 target_state_name(target
));
1074 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1076 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1077 /* allow scripts to override the reset event */
1079 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1080 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1081 target
->state
= TARGET_RESET
;
1086 /* some cores support connecting while srst is asserted
1087 * use that mode is it has been configured */
1089 bool srst_asserted
= false;
1091 if (!target_was_examined(target
)) {
1092 if (jtag_reset_config
& RESET_HAS_SRST
) {
1093 adapter_assert_reset();
1094 if (target
->reset_halt
)
1095 LOG_ERROR("Target not examined, will not halt after reset!");
1098 LOG_ERROR("Target not examined, reset NOT asserted!");
1103 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1104 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1105 adapter_assert_reset();
1106 srst_asserted
= true;
1109 /* Enable debug requests */
1111 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1112 /* Store important errors instead of failing and proceed to reset assert */
1114 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1115 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1117 /* If the processor is sleeping in a WFI or WFE instruction, the
1118 * C_HALT bit must be asserted to regain control */
1119 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1120 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1122 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1123 /* Ignore less important errors */
1125 if (!target
->reset_halt
) {
1126 /* Set/Clear C_MASKINTS in a separate operation */
1127 cortex_m_set_maskints_for_run(target
);
1129 /* clear any debug flags before resuming */
1130 cortex_m_clear_halt(target
);
1132 /* clear C_HALT in dhcsr reg */
1133 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1135 /* Halt in debug on reset; endreset_event() restores DEMCR.
1137 * REVISIT catching BUSERR presumably helps to defend against
1138 * bad vector table entries. Should this include MMERR or
1142 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1143 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1144 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1145 LOG_INFO("AP write error, reset will not halt");
1148 if (jtag_reset_config
& RESET_HAS_SRST
) {
1149 /* default to asserting srst */
1151 adapter_assert_reset();
1153 /* srst is asserted, ignore AP access errors */
1156 /* Use a standard Cortex-M3 software reset mechanism.
1157 * We default to using VECRESET as it is supported on all current cores
1158 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1159 * This has the disadvantage of not resetting the peripherals, so a
1160 * reset-init event handler is needed to perform any peripheral resets.
1162 if (!cortex_m
->vectreset_supported
1163 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1164 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1165 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1166 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1169 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1170 ? "SYSRESETREQ" : "VECTRESET");
1172 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1173 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1174 "handler to reset any peripherals or configure hardware srst support.");
1178 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1179 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1180 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1181 if (retval3
!= ERROR_OK
)
1182 LOG_DEBUG("Ignoring AP write error right after reset");
1184 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1185 if (retval3
!= ERROR_OK
)
1186 LOG_ERROR("DP initialisation failed");
1189 /* I do not know why this is necessary, but it
1190 * fixes strange effects (step/resume cause NMI
1191 * after reset) on LM3S6918 -- Michael Schwingen
1194 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1198 target
->state
= TARGET_RESET
;
1199 jtag_add_sleep(50000);
1201 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1203 /* now return stored error code if any */
1204 if (retval
!= ERROR_OK
)
1207 if (target
->reset_halt
) {
1208 retval
= target_halt(target
);
1209 if (retval
!= ERROR_OK
)
1216 static int cortex_m_deassert_reset(struct target
*target
)
1218 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1220 LOG_DEBUG("target->state: %s",
1221 target_state_name(target
));
1223 /* deassert reset lines */
1224 adapter_deassert_reset();
1226 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1228 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1229 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1230 target_was_examined(target
)) {
1231 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1232 if (retval
!= ERROR_OK
) {
1233 LOG_ERROR("DP initialisation failed");
1241 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1245 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1246 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1248 if (breakpoint
->set
) {
1249 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1253 if (breakpoint
->type
== BKPT_HARD
) {
1254 uint32_t fpcr_value
;
1255 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1257 if (fp_num
>= cortex_m
->fp_num_code
) {
1258 LOG_ERROR("Can not find free FPB Comparator!");
1259 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1261 breakpoint
->set
= fp_num
+ 1;
1262 fpcr_value
= breakpoint
->address
| 1;
1263 if (cortex_m
->fp_rev
== 0) {
1264 if (breakpoint
->address
> 0x1FFFFFFF) {
1265 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1269 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1270 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1271 } else if (cortex_m
->fp_rev
> 1) {
1272 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1275 comparator_list
[fp_num
].used
= true;
1276 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1277 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1278 comparator_list
[fp_num
].fpcr_value
);
1279 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1281 comparator_list
[fp_num
].fpcr_value
);
1282 if (!cortex_m
->fpb_enabled
) {
1283 LOG_DEBUG("FPB wasn't enabled, do it now");
1284 retval
= cortex_m_enable_fpb(target
);
1285 if (retval
!= ERROR_OK
) {
1286 LOG_ERROR("Failed to enable the FPB");
1290 cortex_m
->fpb_enabled
= true;
1292 } else if (breakpoint
->type
== BKPT_SOFT
) {
1295 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1296 * semihosting; don't use that. Otherwise the BKPT
1297 * parameter is arbitrary.
1299 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1300 retval
= target_read_memory(target
,
1301 breakpoint
->address
& 0xFFFFFFFE,
1302 breakpoint
->length
, 1,
1303 breakpoint
->orig_instr
);
1304 if (retval
!= ERROR_OK
)
1306 retval
= target_write_memory(target
,
1307 breakpoint
->address
& 0xFFFFFFFE,
1308 breakpoint
->length
, 1,
1310 if (retval
!= ERROR_OK
)
1312 breakpoint
->set
= true;
1315 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1316 breakpoint
->unique_id
,
1317 (int)(breakpoint
->type
),
1318 breakpoint
->address
,
1325 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1328 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1329 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1331 if (!breakpoint
->set
) {
1332 LOG_WARNING("breakpoint not set");
1336 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1337 breakpoint
->unique_id
,
1338 (int)(breakpoint
->type
),
1339 breakpoint
->address
,
1343 if (breakpoint
->type
== BKPT_HARD
) {
1344 int fp_num
= breakpoint
->set
- 1;
1345 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1346 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1349 comparator_list
[fp_num
].used
= false;
1350 comparator_list
[fp_num
].fpcr_value
= 0;
1351 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1352 comparator_list
[fp_num
].fpcr_value
);
1354 /* restore original instruction (kept in target endianness) */
1355 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1356 breakpoint
->length
, 1,
1357 breakpoint
->orig_instr
);
1358 if (retval
!= ERROR_OK
)
1361 breakpoint
->set
= false;
1366 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1368 if (breakpoint
->length
== 3) {
1369 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1370 breakpoint
->length
= 2;
1373 if ((breakpoint
->length
!= 2)) {
1374 LOG_INFO("only breakpoints of two bytes length supported");
1375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1378 return cortex_m_set_breakpoint(target
, breakpoint
);
1381 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1383 if (!breakpoint
->set
)
1386 return cortex_m_unset_breakpoint(target
, breakpoint
);
1389 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1392 uint32_t mask
, temp
;
1393 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1395 /* watchpoint params were validated earlier */
1397 temp
= watchpoint
->length
;
1404 /* REVISIT Don't fully trust these "not used" records ... users
1405 * may set up breakpoints by hand, e.g. dual-address data value
1406 * watchpoint using comparator #1; comparator #0 matching cycle
1407 * count; send data trace info through ITM and TPIU; etc
1409 struct cortex_m_dwt_comparator
*comparator
;
1411 for (comparator
= cortex_m
->dwt_comparator_list
;
1412 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1413 comparator
++, dwt_num
++)
1415 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1416 LOG_ERROR("Can not find free DWT Comparator");
1419 comparator
->used
= true;
1420 watchpoint
->set
= dwt_num
+ 1;
1422 comparator
->comp
= watchpoint
->address
;
1423 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1426 comparator
->mask
= mask
;
1427 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1430 switch (watchpoint
->rw
) {
1432 comparator
->function
= 5;
1435 comparator
->function
= 6;
1438 comparator
->function
= 7;
1441 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1442 comparator
->function
);
1444 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1445 watchpoint
->unique_id
, dwt_num
,
1446 (unsigned) comparator
->comp
,
1447 (unsigned) comparator
->mask
,
1448 (unsigned) comparator
->function
);
1452 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1454 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1455 struct cortex_m_dwt_comparator
*comparator
;
1458 if (!watchpoint
->set
) {
1459 LOG_WARNING("watchpoint (wpid: %d) not set",
1460 watchpoint
->unique_id
);
1464 dwt_num
= watchpoint
->set
- 1;
1466 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1467 watchpoint
->unique_id
, dwt_num
,
1468 (unsigned) watchpoint
->address
);
1470 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1471 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1475 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1476 comparator
->used
= false;
1477 comparator
->function
= 0;
1478 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1479 comparator
->function
);
1481 watchpoint
->set
= false;
1486 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1488 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1490 if (cortex_m
->dwt_comp_available
< 1) {
1491 LOG_DEBUG("no comparators?");
1492 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1495 /* hardware doesn't support data value masking */
1496 if (watchpoint
->mask
!= ~(uint32_t)0) {
1497 LOG_DEBUG("watchpoint value masks not supported");
1498 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1501 /* hardware allows address masks of up to 32K */
1504 for (mask
= 0; mask
< 16; mask
++) {
1505 if ((1u << mask
) == watchpoint
->length
)
1509 LOG_DEBUG("unsupported watchpoint length");
1510 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1512 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1513 LOG_DEBUG("watchpoint address is unaligned");
1514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1517 /* Caller doesn't seem to be able to describe watching for data
1518 * values of zero; that flags "no value".
1520 * REVISIT This DWT may well be able to watch for specific data
1521 * values. Requires comparator #1 to set DATAVMATCH and match
1522 * the data, and another comparator (DATAVADDR0) matching addr.
1524 if (watchpoint
->value
) {
1525 LOG_DEBUG("data value watchpoint not YET supported");
1526 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1529 cortex_m
->dwt_comp_available
--;
1530 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1535 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1537 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1539 /* REVISIT why check? DWT can be updated with core running ... */
1540 if (target
->state
!= TARGET_HALTED
) {
1541 LOG_WARNING("target not halted");
1542 return ERROR_TARGET_NOT_HALTED
;
1545 if (watchpoint
->set
)
1546 cortex_m_unset_watchpoint(target
, watchpoint
);
1548 cortex_m
->dwt_comp_available
++;
1549 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1554 void cortex_m_enable_watchpoints(struct target
*target
)
1556 struct watchpoint
*watchpoint
= target
->watchpoints
;
1558 /* set any pending watchpoints */
1559 while (watchpoint
) {
1560 if (!watchpoint
->set
)
1561 cortex_m_set_watchpoint(target
, watchpoint
);
1562 watchpoint
= watchpoint
->next
;
1566 static int cortex_m_load_core_reg_u32(struct target
*target
,
1567 uint32_t num
, uint32_t *value
)
1571 /* NOTE: we "know" here that the register identifiers used
1572 * in the v7m header match the Cortex-M3 Debug Core Register
1573 * Selector values for R0..R15, xPSR, MSP, and PSP.
1577 /* read a normal core register */
1578 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1580 if (retval
!= ERROR_OK
) {
1581 LOG_ERROR("JTAG failure %i", retval
);
1582 return ERROR_JTAG_DEVICE_ERROR
;
1584 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1588 /* Floating-point Status and Registers */
1589 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1590 if (retval
!= ERROR_OK
)
1592 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1593 if (retval
!= ERROR_OK
)
1595 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1598 case ARMV7M_S0
... ARMV7M_S31
:
1599 /* Floating-point Status and Registers */
1600 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1601 if (retval
!= ERROR_OK
)
1603 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1604 if (retval
!= ERROR_OK
)
1606 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1607 (int)(num
- ARMV7M_S0
), *value
);
1610 case ARMV7M_PRIMASK
:
1611 case ARMV7M_BASEPRI
:
1612 case ARMV7M_FAULTMASK
:
1613 case ARMV7M_CONTROL
:
1614 /* Cortex-M3 packages these four registers as bitfields
1615 * in one Debug Core register. So say r0 and r2 docs;
1616 * it was removed from r1 docs, but still works.
1618 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1621 case ARMV7M_PRIMASK
:
1622 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1625 case ARMV7M_BASEPRI
:
1626 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1629 case ARMV7M_FAULTMASK
:
1630 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1633 case ARMV7M_CONTROL
:
1634 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1638 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1642 return ERROR_COMMAND_SYNTAX_ERROR
;
1648 static int cortex_m_store_core_reg_u32(struct target
*target
,
1649 uint32_t num
, uint32_t value
)
1653 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1655 /* NOTE: we "know" here that the register identifiers used
1656 * in the v7m header match the Cortex-M3 Debug Core Register
1657 * Selector values for R0..R15, xPSR, MSP, and PSP.
1661 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1662 if (retval
!= ERROR_OK
) {
1665 LOG_ERROR("JTAG failure");
1666 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1667 r
->dirty
= r
->valid
;
1668 return ERROR_JTAG_DEVICE_ERROR
;
1670 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1674 /* Floating-point Status and Registers */
1675 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1676 if (retval
!= ERROR_OK
)
1678 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1679 if (retval
!= ERROR_OK
)
1681 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1684 case ARMV7M_S0
... ARMV7M_S31
:
1685 /* Floating-point Status and Registers */
1686 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1687 if (retval
!= ERROR_OK
)
1689 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1690 if (retval
!= ERROR_OK
)
1692 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1693 (int)(num
- ARMV7M_S0
), value
);
1696 case ARMV7M_PRIMASK
:
1697 case ARMV7M_BASEPRI
:
1698 case ARMV7M_FAULTMASK
:
1699 case ARMV7M_CONTROL
:
1700 /* Cortex-M3 packages these four registers as bitfields
1701 * in one Debug Core register. So say r0 and r2 docs;
1702 * it was removed from r1 docs, but still works.
1704 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1707 case ARMV7M_PRIMASK
:
1708 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1711 case ARMV7M_BASEPRI
:
1712 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1715 case ARMV7M_FAULTMASK
:
1716 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1719 case ARMV7M_CONTROL
:
1720 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1724 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1726 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1730 return ERROR_COMMAND_SYNTAX_ERROR
;
1736 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1737 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1739 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1741 if (armv7m
->arm
.is_armv6m
) {
1742 /* armv6m does not handle unaligned memory access */
1743 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1744 return ERROR_TARGET_UNALIGNED_ACCESS
;
1747 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1750 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1751 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1753 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1755 if (armv7m
->arm
.is_armv6m
) {
1756 /* armv6m does not handle unaligned memory access */
1757 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1758 return ERROR_TARGET_UNALIGNED_ACCESS
;
1761 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1764 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1765 struct target
*target
)
1767 armv7m_build_reg_cache(target
);
1768 arm_semihosting_init(target
);
1772 void cortex_m_deinit_target(struct target
*target
)
1774 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1776 free(cortex_m
->fp_comparator_list
);
1778 cortex_m_dwt_free(target
);
1779 armv7m_free_reg_cache(target
);
1781 free(target
->private_config
);
1785 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1786 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1788 struct timeval timeout
, now
;
1789 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1791 bool use_pcsr
= false;
1792 int retval
= ERROR_OK
;
1795 gettimeofday(&timeout
, NULL
);
1796 timeval_add_time(&timeout
, seconds
, 0);
1798 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1799 if (retval
!= ERROR_OK
) {
1800 LOG_ERROR("Error while reading PCSR");
1804 if (reg_value
!= 0) {
1806 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1808 LOG_INFO("Starting profiling. Halting and resuming the"
1809 " target as often as we can...");
1810 reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1813 /* Make sure the target is running */
1814 target_poll(target
);
1815 if (target
->state
== TARGET_HALTED
)
1816 retval
= target_resume(target
, 1, 0, 0, 0);
1818 if (retval
!= ERROR_OK
) {
1819 LOG_ERROR("Error while resuming target");
1823 uint32_t sample_count
= 0;
1827 if (armv7m
&& armv7m
->debug_ap
) {
1828 uint32_t read_count
= max_num_samples
- sample_count
;
1829 if (read_count
> 1024)
1832 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1833 (void *)&samples
[sample_count
],
1834 4, read_count
, DWT_PCSR
);
1835 sample_count
+= read_count
;
1837 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1840 target_poll(target
);
1841 if (target
->state
== TARGET_HALTED
) {
1842 reg_value
= buf_get_u32(reg
->value
, 0, 32);
1843 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1844 retval
= target_resume(target
, 1, 0, 0, 0);
1845 samples
[sample_count
++] = reg_value
;
1846 target_poll(target
);
1847 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1848 } else if (target
->state
== TARGET_RUNNING
) {
1849 /* We want to quickly sample the PC. */
1850 retval
= target_halt(target
);
1852 LOG_INFO("Target not halted or running");
1858 if (retval
!= ERROR_OK
) {
1859 LOG_ERROR("Error while reading %s", use_pcsr
? "PCSR" : "target pc");
1864 gettimeofday(&now
, NULL
);
1865 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1866 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1871 *num_samples
= sample_count
;
1876 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1877 * on r/w if the core is not running, and clear on resume or reset ... or
1878 * at least, in a post_restore_context() method.
1881 struct dwt_reg_state
{
1882 struct target
*target
;
1884 uint8_t value
[4]; /* scratch/cache */
1887 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1889 struct dwt_reg_state
*state
= reg
->arch_info
;
1892 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1893 if (retval
!= ERROR_OK
)
1896 buf_set_u32(state
->value
, 0, 32, tmp
);
1900 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1902 struct dwt_reg_state
*state
= reg
->arch_info
;
1904 return target_write_u32(state
->target
, state
->addr
,
1905 buf_get_u32(buf
, 0, reg
->size
));
1914 static const struct dwt_reg dwt_base_regs
[] = {
1915 { DWT_CTRL
, "dwt_ctrl", 32, },
1916 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1917 * increments while the core is asleep.
1919 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1920 /* plus some 8 bit counters, useful for profiling with TPIU */
1923 static const struct dwt_reg dwt_comp
[] = {
1924 #define DWT_COMPARATOR(i) \
1925 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1926 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1927 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1944 #undef DWT_COMPARATOR
1947 static const struct reg_arch_type dwt_reg_type
= {
1948 .get
= cortex_m_dwt_get_reg
,
1949 .set
= cortex_m_dwt_set_reg
,
1952 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1954 struct dwt_reg_state
*state
;
1956 state
= calloc(1, sizeof *state
);
1959 state
->addr
= d
->addr
;
1964 r
->value
= state
->value
;
1965 r
->arch_info
= state
;
1966 r
->type
= &dwt_reg_type
;
1969 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1972 struct reg_cache
*cache
;
1973 struct cortex_m_dwt_comparator
*comparator
;
1976 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1977 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
1979 LOG_DEBUG("no DWT");
1983 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1984 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1985 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1986 sizeof(struct cortex_m_dwt_comparator
));
1987 if (!cm
->dwt_comparator_list
) {
1989 cm
->dwt_num_comp
= 0;
1990 LOG_ERROR("out of mem");
1994 cache
= calloc(1, sizeof *cache
);
1997 free(cm
->dwt_comparator_list
);
2000 cache
->name
= "Cortex-M DWT registers";
2001 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2002 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
2003 if (!cache
->reg_list
) {
2008 for (reg
= 0; reg
< 2; reg
++)
2009 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2010 dwt_base_regs
+ reg
);
2012 comparator
= cm
->dwt_comparator_list
;
2013 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2016 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2017 for (j
= 0; j
< 3; j
++, reg
++)
2018 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2019 dwt_comp
+ 3 * i
+ j
);
2021 /* make sure we clear any watchpoints enabled on the target */
2022 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2025 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2026 cm
->dwt_cache
= cache
;
2028 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2029 dwtcr
, cm
->dwt_num_comp
,
2030 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2032 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2033 * implement single-address data value watchpoints ... so we
2034 * won't need to check it later, when asked to set one up.
2038 static void cortex_m_dwt_free(struct target
*target
)
2040 struct cortex_m_common
*cm
= target_to_cm(target
);
2041 struct reg_cache
*cache
= cm
->dwt_cache
;
2043 free(cm
->dwt_comparator_list
);
2044 cm
->dwt_comparator_list
= NULL
;
2045 cm
->dwt_num_comp
= 0;
2048 register_unlink_cache(&target
->reg_cache
, cache
);
2050 if (cache
->reg_list
) {
2051 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2052 free(cache
->reg_list
[i
].arch_info
);
2053 free(cache
->reg_list
);
2057 cm
->dwt_cache
= NULL
;
2060 #define MVFR0 0xe000ef40
2061 #define MVFR1 0xe000ef44
2063 #define MVFR0_DEFAULT_M4 0x10110021
2064 #define MVFR1_DEFAULT_M4 0x11000011
2066 #define MVFR0_DEFAULT_M7_SP 0x10110021
2067 #define MVFR0_DEFAULT_M7_DP 0x10110221
2068 #define MVFR1_DEFAULT_M7_SP 0x11000011
2069 #define MVFR1_DEFAULT_M7_DP 0x12000011
2071 int cortex_m_examine(struct target
*target
)
2074 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2076 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2077 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2078 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2080 /* stlink shares the examine handler but does not support
2082 if (!armv7m
->stlink
) {
2083 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2084 /* Search for the MEM-AP */
2085 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7m
->debug_ap
);
2086 if (retval
!= ERROR_OK
) {
2087 LOG_ERROR("Could not find MEM-AP to control the core");
2091 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
2094 /* Leave (only) generic DAP stuff for debugport_init(); */
2095 armv7m
->debug_ap
->memaccess_tck
= 8;
2097 retval
= mem_ap_init(armv7m
->debug_ap
);
2098 if (retval
!= ERROR_OK
)
2102 if (!target_was_examined(target
)) {
2103 target_set_examined(target
);
2105 /* Read from Device Identification Registers */
2106 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2107 if (retval
!= ERROR_OK
)
2111 i
= (cpuid
>> 4) & 0xf;
2113 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2114 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2115 cortex_m
->maskints_erratum
= false;
2118 rev
= (cpuid
>> 20) & 0xf;
2119 patch
= (cpuid
>> 0) & 0xf;
2120 if ((rev
== 0) && (patch
< 2)) {
2121 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2122 cortex_m
->maskints_erratum
= true;
2125 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2127 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2128 cortex_m
->vectreset_supported
= i
> 1;
2131 target_read_u32(target
, MVFR0
, &mvfr0
);
2132 target_read_u32(target
, MVFR1
, &mvfr1
);
2134 /* test for floating point feature on Cortex-M4 */
2135 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2136 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2137 armv7m
->fp_feature
= FPv4_SP
;
2139 } else if (i
== 7) {
2140 target_read_u32(target
, MVFR0
, &mvfr0
);
2141 target_read_u32(target
, MVFR1
, &mvfr1
);
2143 /* test for floating point features on Cortex-M7 */
2144 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2145 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2146 armv7m
->fp_feature
= FPv5_SP
;
2147 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2148 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2149 armv7m
->fp_feature
= FPv5_DP
;
2151 } else if (i
== 0) {
2152 /* Cortex-M0 does not support unaligned memory access */
2153 armv7m
->arm
.is_armv6m
= true;
2156 if (armv7m
->fp_feature
== FP_NONE
&&
2157 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2158 /* free unavailable FPU registers */
2161 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2162 idx
< armv7m
->arm
.core_cache
->num_regs
;
2164 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
2165 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2166 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2168 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2171 if (!armv7m
->stlink
) {
2172 if (i
== 3 || i
== 4)
2173 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2174 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2175 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2177 /* Cortex-M7 has only 1024 bytes autoincrement range */
2178 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2181 /* Configure trace modules */
2182 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2183 if (retval
!= ERROR_OK
)
2186 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2187 armv7m_trace_tpiu_config(target
);
2188 armv7m_trace_itm_config(target
);
2191 /* NOTE: FPB and DWT are both optional. */
2194 target_read_u32(target
, FP_CTRL
, &fpcr
);
2195 /* bits [14:12] and [7:4] */
2196 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2197 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2198 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2199 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2200 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2201 free(cortex_m
->fp_comparator_list
);
2202 cortex_m
->fp_comparator_list
= calloc(
2203 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2204 sizeof(struct cortex_m_fp_comparator
));
2205 cortex_m
->fpb_enabled
= fpcr
& 1;
2206 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2207 cortex_m
->fp_comparator_list
[i
].type
=
2208 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2209 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2211 /* make sure we clear any breakpoints enabled on the target */
2212 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2214 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2216 cortex_m
->fp_num_code
,
2217 cortex_m
->fp_num_lit
);
2220 cortex_m_dwt_free(target
);
2221 cortex_m_dwt_setup(cortex_m
, target
);
2223 /* These hardware breakpoints only work for code in flash! */
2224 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2225 target_name(target
),
2226 cortex_m
->fp_num_code
,
2227 cortex_m
->dwt_num_comp
);
2233 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2235 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2240 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2241 if (retval
!= ERROR_OK
)
2244 dcrdr
= target_buffer_get_u16(target
, buf
);
2245 *ctrl
= (uint8_t)dcrdr
;
2246 *value
= (uint8_t)(dcrdr
>> 8);
2248 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2250 /* write ack back to software dcc register
2251 * signify we have read data */
2252 if (dcrdr
& (1 << 0)) {
2253 target_buffer_set_u16(target
, buf
, 0);
2254 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2255 if (retval
!= ERROR_OK
)
2262 static int cortex_m_target_request_data(struct target
*target
,
2263 uint32_t size
, uint8_t *buffer
)
2269 for (i
= 0; i
< (size
* 4); i
++) {
2270 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2271 if (retval
!= ERROR_OK
)
2279 static int cortex_m_handle_target_request(void *priv
)
2281 struct target
*target
= priv
;
2282 if (!target_was_examined(target
))
2285 if (!target
->dbg_msg_enabled
)
2288 if (target
->state
== TARGET_RUNNING
) {
2293 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2294 if (retval
!= ERROR_OK
)
2297 /* check if we have data */
2298 if (ctrl
& (1 << 0)) {
2301 /* we assume target is quick enough */
2303 for (int i
= 1; i
<= 3; i
++) {
2304 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2305 if (retval
!= ERROR_OK
)
2307 request
|= ((uint32_t)data
<< (i
* 8));
2309 target_request(target
, request
);
2316 static int cortex_m_init_arch_info(struct target
*target
,
2317 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2319 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2321 armv7m_init_arch_info(target
, armv7m
);
2323 /* default reset mode is to use srst if fitted
2324 * if not it will use CORTEX_M3_RESET_VECTRESET */
2325 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2327 armv7m
->arm
.dap
= dap
;
2329 /* register arch-specific functions */
2330 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2332 armv7m
->post_debug_entry
= NULL
;
2334 armv7m
->pre_restore_context
= NULL
;
2336 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2337 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2339 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2340 TARGET_TIMER_TYPE_PERIODIC
, target
);
2345 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2347 struct adiv5_private_config
*pc
;
2349 pc
= (struct adiv5_private_config
*)target
->private_config
;
2350 if (adiv5_verify_config(pc
) != ERROR_OK
)
2353 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2354 if (cortex_m
== NULL
) {
2355 LOG_ERROR("No memory creating target");
2359 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2360 cortex_m
->apsel
= pc
->ap_num
;
2362 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2367 /*--------------------------------------------------------------------------*/
2369 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2370 struct cortex_m_common
*cm
)
2372 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2373 command_print(cmd
->ctx
, "target is not a Cortex-M");
2374 return ERROR_TARGET_INVALID
;
2380 * Only stuff below this line should need to verify that its target
2381 * is a Cortex-M3. Everything else should have indirected through the
2382 * cortexm3_target structure, which is only used with CM3 targets.
2385 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2387 struct target
*target
= get_current_target(CMD_CTX
);
2388 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2389 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2393 static const struct {
2397 { "hard_err", VC_HARDERR
, },
2398 { "int_err", VC_INTERR
, },
2399 { "bus_err", VC_BUSERR
, },
2400 { "state_err", VC_STATERR
, },
2401 { "chk_err", VC_CHKERR
, },
2402 { "nocp_err", VC_NOCPERR
, },
2403 { "mm_err", VC_MMERR
, },
2404 { "reset", VC_CORERESET
, },
2407 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2408 if (retval
!= ERROR_OK
)
2411 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2412 if (retval
!= ERROR_OK
)
2418 if (CMD_ARGC
== 1) {
2419 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2420 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2421 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2422 | VC_MMERR
| VC_CORERESET
;
2424 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2427 while (CMD_ARGC
-- > 0) {
2429 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2430 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2432 catch |= vec_ids
[i
].mask
;
2435 if (i
== ARRAY_SIZE(vec_ids
)) {
2436 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2437 return ERROR_COMMAND_SYNTAX_ERROR
;
2441 /* For now, armv7m->demcr only stores vector catch flags. */
2442 armv7m
->demcr
= catch;
2447 /* write, but don't assume it stuck (why not??) */
2448 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2449 if (retval
!= ERROR_OK
)
2451 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2452 if (retval
!= ERROR_OK
)
2455 /* FIXME be sure to clear DEMCR on clean server shutdown.
2456 * Otherwise the vector catch hardware could fire when there's
2457 * no debugger hooked up, causing much confusion...
2461 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2462 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2463 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2469 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2471 struct target
*target
= get_current_target(CMD_CTX
);
2472 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2475 static const Jim_Nvp nvp_maskisr_modes
[] = {
2476 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2477 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2478 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2479 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2480 { .name
= NULL
, .value
= -1 },
2485 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2486 if (retval
!= ERROR_OK
)
2489 if (target
->state
!= TARGET_HALTED
) {
2490 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2495 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2496 if (n
->name
== NULL
)
2497 return ERROR_COMMAND_SYNTAX_ERROR
;
2498 cortex_m
->isrmasking_mode
= n
->value
;
2499 cortex_m_set_maskints_for_halt(target
);
2502 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2503 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2508 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2510 struct target
*target
= get_current_target(CMD_CTX
);
2511 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2515 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2516 if (retval
!= ERROR_OK
)
2520 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2521 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2523 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2524 if (target_was_examined(target
)
2525 && !cortex_m
->vectreset_supported
)
2526 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2528 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2531 return ERROR_COMMAND_SYNTAX_ERROR
;
2534 switch (cortex_m
->soft_reset_config
) {
2535 case CORTEX_M_RESET_SYSRESETREQ
:
2536 reset_config
= "sysresetreq";
2539 case CORTEX_M_RESET_VECTRESET
:
2540 reset_config
= "vectreset";
2544 reset_config
= "unknown";
2548 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2553 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2556 .handler
= handle_cortex_m_mask_interrupts_command
,
2557 .mode
= COMMAND_EXEC
,
2558 .help
= "mask cortex_m interrupts",
2559 .usage
= "['auto'|'on'|'off'|'steponly']",
2562 .name
= "vector_catch",
2563 .handler
= handle_cortex_m_vector_catch_command
,
2564 .mode
= COMMAND_EXEC
,
2565 .help
= "configure hardware vectors to trigger debug entry",
2566 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2569 .name
= "reset_config",
2570 .handler
= handle_cortex_m_reset_config_command
,
2571 .mode
= COMMAND_ANY
,
2572 .help
= "configure software reset handling",
2573 .usage
= "['sysresetreq'|'vectreset']",
2575 COMMAND_REGISTRATION_DONE
2577 static const struct command_registration cortex_m_command_handlers
[] = {
2579 .chain
= armv7m_command_handlers
,
2582 .chain
= armv7m_trace_command_handlers
,
2586 .mode
= COMMAND_EXEC
,
2587 .help
= "Cortex-M command group",
2589 .chain
= cortex_m_exec_command_handlers
,
2591 COMMAND_REGISTRATION_DONE
2594 struct target_type cortexm_target
= {
2596 .deprecated_name
= "cortex_m3",
2598 .poll
= cortex_m_poll
,
2599 .arch_state
= armv7m_arch_state
,
2601 .target_request_data
= cortex_m_target_request_data
,
2603 .halt
= cortex_m_halt
,
2604 .resume
= cortex_m_resume
,
2605 .step
= cortex_m_step
,
2607 .assert_reset
= cortex_m_assert_reset
,
2608 .deassert_reset
= cortex_m_deassert_reset
,
2609 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2611 .get_gdb_arch
= arm_get_gdb_arch
,
2612 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2614 .read_memory
= cortex_m_read_memory
,
2615 .write_memory
= cortex_m_write_memory
,
2616 .checksum_memory
= armv7m_checksum_memory
,
2617 .blank_check_memory
= armv7m_blank_check_memory
,
2619 .run_algorithm
= armv7m_run_algorithm
,
2620 .start_algorithm
= armv7m_start_algorithm
,
2621 .wait_algorithm
= armv7m_wait_algorithm
,
2623 .add_breakpoint
= cortex_m_add_breakpoint
,
2624 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2625 .add_watchpoint
= cortex_m_add_watchpoint
,
2626 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2628 .commands
= cortex_m_command_handlers
,
2629 .target_create
= cortex_m_target_create
,
2630 .target_jim_configure
= adiv5_jim_configure
,
2631 .init_target
= cortex_m_init_target
,
2632 .examine
= cortex_m_examine
,
2633 .deinit_target
= cortex_m_deinit_target
,
2635 .profiling
= cortex_m_profiling
,
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