1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
32 ***************************************************************************/
39 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
43 #define _DEBUG_INSTRUCTION_EXECUTION_
46 char* armv7m_mode_strings
[] =
48 "Thread", "Thread (User)", "Handler",
51 static char *armv7m_exception_strings
[] =
53 "", "Reset", "NMI", "HardFault",
54 "MemManage", "BusFault", "UsageFault", "RESERVED",
55 "RESERVED", "RESERVED", "RESERVED", "SVCall",
56 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
59 uint8_t armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
61 reg_t armv7m_gdb_dummy_fp_reg
=
63 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
66 uint8_t armv7m_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
68 reg_t armv7m_gdb_dummy_fps_reg
=
70 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
73 #ifdef ARMV7_GDB_HACKS
74 uint8_t armv7m_gdb_dummy_cpsr_value
[] = {0, 0, 0, 0};
76 reg_t armv7m_gdb_dummy_cpsr_reg
=
78 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value
, 0, 1, 32, NULL
, 0, NULL
, 0
83 * These registers are not memory-mapped. The ARMv7-M profile includes
84 * memory mapped registers too, such as for the NVIC (interrupt controller)
85 * and SysTick (timer) modules; those can mostly be treated as peripherals.
103 { ARMV7M_R10
, "r10" },
104 { ARMV7M_R11
, "r11" },
106 { ARMV7M_R12
, "r12" },
107 { ARMV7M_R13
, "sp" },
108 { ARMV7M_R14
, "lr" },
111 { ARMV7M_xPSR
, "xPSR" },
112 { ARMV7M_MSP
, "msp" },
113 { ARMV7M_PSP
, "psp" },
115 { ARMV7M_PRIMASK
, "primask" },
116 { ARMV7M_BASEPRI
, "basepri" },
117 { ARMV7M_FAULTMASK
, "faultmask" },
118 { ARMV7M_CONTROL
, "control" },
121 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
123 int armv7m_core_reg_arch_type
= -1;
124 int armv7m_dummy_core_reg_arch_type
= -1;
126 int armv7m_restore_context(target_t
*target
)
130 /* get pointers to arch-specific information */
131 armv7m_common_t
*armv7m
= target
->arch_info
;
135 if (armv7m
->pre_restore_context
)
136 armv7m
->pre_restore_context(target
);
138 for (i
= ARMV7M_NUM_REGS
- 1; i
>= 0; i
--)
140 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
142 armv7m
->write_core_reg(target
, i
);
146 if (armv7m
->post_restore_context
)
147 armv7m
->post_restore_context(target
);
152 /* Core state functions */
153 char *armv7m_exception_string(int number
)
155 static char enamebuf
[32];
157 if ((number
< 0) | (number
> 511))
158 return "Invalid exception";
160 return armv7m_exception_strings
[number
];
161 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
165 int armv7m_get_core_reg(reg_t
*reg
)
168 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
169 target_t
*target
= armv7m_reg
->target
;
170 armv7m_common_t
*armv7m_target
= target
->arch_info
;
172 if (target
->state
!= TARGET_HALTED
)
174 return ERROR_TARGET_NOT_HALTED
;
177 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
182 int armv7m_set_core_reg(reg_t
*reg
, uint8_t *buf
)
184 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
185 target_t
*target
= armv7m_reg
->target
;
186 uint32_t value
= buf_get_u32(buf
, 0, 32);
188 if (target
->state
!= TARGET_HALTED
)
190 return ERROR_TARGET_NOT_HALTED
;
193 buf_set_u32(reg
->value
, 0, 32, value
);
200 int armv7m_read_core_reg(struct target_s
*target
, int num
)
204 armv7m_core_reg_t
* armv7m_core_reg
;
206 /* get pointers to arch-specific information */
207 armv7m_common_t
*armv7m
= target
->arch_info
;
209 if ((num
< 0) || (num
>= ARMV7M_NUM_REGS
))
210 return ERROR_INVALID_ARGUMENTS
;
212 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
213 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
214 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
215 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
216 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
221 int armv7m_write_core_reg(struct target_s
*target
, int num
)
225 armv7m_core_reg_t
*armv7m_core_reg
;
227 /* get pointers to arch-specific information */
228 armv7m_common_t
*armv7m
= target
->arch_info
;
230 if ((num
< 0) || (num
>= ARMV7M_NUM_REGS
))
231 return ERROR_INVALID_ARGUMENTS
;
233 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
234 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
235 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
236 if (retval
!= ERROR_OK
)
238 LOG_ERROR("JTAG failure");
239 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
240 return ERROR_JTAG_DEVICE_ERROR
;
242 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
243 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
244 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
249 int armv7m_invalidate_core_regs(target_t
*target
)
251 /* get pointers to arch-specific information */
252 armv7m_common_t
*armv7m
= target
->arch_info
;
255 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
257 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
258 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
264 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
266 /* get pointers to arch-specific information */
267 armv7m_common_t
*armv7m
= target
->arch_info
;
271 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
274 * GDB register packet format for ARM:
275 * - the first 16 registers are r0..r15
276 * - (obsolete) 8 FPA registers
277 * - (obsolete) FPA status
280 for (i
= 0; i
< 16; i
++)
282 (*reg_list
)[i
] = &armv7m
->core_cache
->reg_list
[i
];
285 for (i
= 16; i
< 24; i
++)
287 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
290 (*reg_list
)[24] = &armv7m_gdb_dummy_fps_reg
;
292 #ifdef ARMV7_GDB_HACKS
293 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
294 (*reg_list
)[25] = &armv7m_gdb_dummy_cpsr_reg
;
296 /* ARMV7M is always in thumb mode, try to make GDB understand this
297 * if it does not support this arch */
298 *((char*)armv7m
->core_cache
->reg_list
[15].value
) |= 1;
300 (*reg_list
)[25] = &armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
];
306 /* run to exit point. return error if exit point was not reached. */
307 static int armv7m_run_and_wait(struct target_s
*target
, uint32_t entry_point
, int timeout_ms
, uint32_t exit_point
, armv7m_common_t
*armv7m
)
311 /* This code relies on the target specific resume() and poll()->debug_entry()
312 * sequence to write register values to the processor and the read them back */
313 if ((retval
= target_resume(target
, 0, entry_point
, 1, 1)) != ERROR_OK
)
318 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
319 /* If the target fails to halt due to the breakpoint, force a halt */
320 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
)
322 if ((retval
= target_halt(target
)) != ERROR_OK
)
324 if ((retval
= target_wait_state(target
, TARGET_HALTED
, 500)) != ERROR_OK
)
328 return ERROR_TARGET_TIMEOUT
;
331 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
332 if (pc
!= exit_point
)
334 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32
" ", pc
);
335 return ERROR_TARGET_TIMEOUT
;
341 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
343 /* get pointers to arch-specific information */
344 armv7m_common_t
*armv7m
= target
->arch_info
;
345 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
346 enum armv7m_mode core_mode
= armv7m
->core_mode
;
347 int retval
= ERROR_OK
;
349 uint32_t context
[ARMV7M_NUM_REGS
];
351 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
353 LOG_ERROR("current target isn't an ARMV7M target");
354 return ERROR_TARGET_INVALID
;
357 if (target
->state
!= TARGET_HALTED
)
359 LOG_WARNING("target not halted");
360 return ERROR_TARGET_NOT_HALTED
;
363 /* refresh core register cache */
364 /* Not needed if core register cache is always consistent with target process state */
365 for (i
= 0; i
< ARMV7M_NUM_REGS
; i
++)
367 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
368 armv7m
->read_core_reg(target
, i
);
369 context
[i
] = buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
372 for (i
= 0; i
< num_mem_params
; i
++)
374 if ((retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
378 for (i
= 0; i
< num_reg_params
; i
++)
380 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
381 // uint32_t regvalue;
385 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
389 if (reg
->size
!= reg_params
[i
].size
)
391 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
395 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
396 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
399 if (armv7m_algorithm_info
->core_mode
!= ARMV7M_MODE_ANY
)
401 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
402 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
,
403 0, 1, armv7m_algorithm_info
->core_mode
);
404 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
405 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
408 /* ARMV7M always runs in Thumb state */
409 if ((retval
= breakpoint_add(target
, exit_point
, 2, BKPT_SOFT
)) != ERROR_OK
)
411 LOG_ERROR("can't add breakpoint to finish algorithm execution");
412 return ERROR_TARGET_FAILURE
;
415 retval
= armv7m_run_and_wait(target
, entry_point
, timeout_ms
, exit_point
, armv7m
);
417 breakpoint_remove(target
, exit_point
);
419 if (retval
!= ERROR_OK
)
424 /* Read memory values to mem_params[] */
425 for (i
= 0; i
< num_mem_params
; i
++)
427 if (mem_params
[i
].direction
!= PARAM_OUT
)
428 if ((retval
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
434 /* Copy core register values to reg_params[] */
435 for (i
= 0; i
< num_reg_params
; i
++)
437 if (reg_params
[i
].direction
!= PARAM_OUT
)
439 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
443 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
447 if (reg
->size
!= reg_params
[i
].size
)
449 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
453 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
457 for (i
= ARMV7M_NUM_REGS
- 1; i
>= 0; i
--)
460 regvalue
= buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
461 if (regvalue
!= context
[i
])
463 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
464 armv7m
->core_cache
->reg_list
[i
].name
, context
[i
]);
465 buf_set_u32(armv7m
->core_cache
->reg_list
[i
].value
,
467 armv7m
->core_cache
->reg_list
[i
].valid
= 1;
468 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
472 armv7m
->core_mode
= core_mode
;
477 int armv7m_arch_state(struct target_s
*target
)
479 /* get pointers to arch-specific information */
480 armv7m_common_t
*armv7m
= target
->arch_info
;
483 ctrl
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 32);
484 sp
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_R13
].value
, 0, 32);
486 LOG_USER("target halted due to %s, current mode: %s %s\n"
487 "xPSR: %#8.8" PRIx32
" pc: %#8.8" PRIx32
" %csp: %#8.8" PRIx32
,
488 Jim_Nvp_value2name_simple(nvp_target_debug_reason
,
489 target
->debug_reason
)->name
,
490 armv7m_mode_strings
[armv7m
->core_mode
],
491 armv7m_exception_string(armv7m
->exception_number
),
492 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
493 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PC
].value
, 0, 32),
494 (ctrl
& 0x02) ? 'p' : 'm',
500 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
502 /* get pointers to arch-specific information */
503 armv7m_common_t
*armv7m
= target
->arch_info
;
505 int num_regs
= ARMV7M_NUM_REGS
;
506 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
507 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
508 reg_t
*reg_list
= calloc(num_regs
, sizeof(reg_t
));
509 armv7m_core_reg_t
*arch_info
= calloc(num_regs
, sizeof(armv7m_core_reg_t
));
512 if (armv7m_core_reg_arch_type
== -1)
514 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
517 register_init_dummy(&armv7m_gdb_dummy_fps_reg
);
518 #ifdef ARMV7_GDB_HACKS
519 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg
);
521 register_init_dummy(&armv7m_gdb_dummy_fp_reg
);
523 /* Build the process context cache */
524 cache
->name
= "arm v7m registers";
526 cache
->reg_list
= reg_list
;
527 cache
->num_regs
= num_regs
;
529 armv7m
->core_cache
= cache
;
531 for (i
= 0; i
< num_regs
; i
++)
533 arch_info
[i
].num
= armv7m_regs
[i
].id
;
534 arch_info
[i
].target
= target
;
535 arch_info
[i
].armv7m_common
= armv7m
;
536 reg_list
[i
].name
= armv7m_regs
[i
].name
;
537 reg_list
[i
].size
= 32;
538 reg_list
[i
].value
= calloc(1, 4);
539 reg_list
[i
].dirty
= 0;
540 reg_list
[i
].valid
= 0;
541 reg_list
[i
].bitfield_desc
= NULL
;
542 reg_list
[i
].num_bitfields
= 0;
543 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
544 reg_list
[i
].arch_info
= &arch_info
[i
];
550 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
552 armv7m_build_reg_cache(target
);
557 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
559 /* register arch-specific functions */
561 target
->arch_info
= armv7m
;
562 armv7m
->read_core_reg
= armv7m_read_core_reg
;
563 armv7m
->write_core_reg
= armv7m_write_core_reg
;
568 int armv7m_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
570 working_area_t
*crc_algorithm
;
571 armv7m_algorithm_t armv7m_info
;
572 reg_param_t reg_params
[2];
575 uint16_t cortex_m3_crc_code
[] = {
576 0x4602, /* mov r2, r0 */
577 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
578 0x460B, /* mov r3, r1 */
579 0xF04F, 0x0400, /* mov r4, #0 */
580 0xE013, /* b ncomp */
582 0x5D11, /* ldrb r1, [r2, r4] */
583 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
584 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
586 0xF04F, 0x0500, /* mov r5, #0 */
588 0x2800, /* cmp r0, #0 */
589 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
590 0xF105, 0x0501, /* add r5, r5, #1 */
591 0x4630, /* mov r0, r6 */
593 0xEA86, 0x0007, /* eor r0, r6, r7 */
594 0x2D08, /* cmp r5, #8 */
595 0xD1F4, /* bne loop */
597 0xF104, 0x0401, /* add r4, r4, #1 */
599 0x429C, /* cmp r4, r3 */
600 0xD1E9, /* bne nbyte */
603 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
608 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
610 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
613 /* convert flash writing code into a buffer in target endianness */
614 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(uint16_t)); i
++)
615 if ((retval
= target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(uint16_t), cortex_m3_crc_code
[i
])) != ERROR_OK
)
620 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
621 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
623 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
624 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
626 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
627 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
629 if ((retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
630 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
632 LOG_ERROR("error executing cortex_m3 crc algorithm");
633 destroy_reg_param(®_params
[0]);
634 destroy_reg_param(®_params
[1]);
635 target_free_working_area(target
, crc_algorithm
);
639 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
641 destroy_reg_param(®_params
[0]);
642 destroy_reg_param(®_params
[1]);
644 target_free_working_area(target
, crc_algorithm
);
649 int armv7m_blank_check_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* blank
)
651 working_area_t
*erase_check_algorithm
;
652 reg_param_t reg_params
[3];
653 armv7m_algorithm_t armv7m_info
;
657 uint16_t erase_check_code
[] =
660 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
661 0xEA02, 0x0203, /* and r2, r2, r3 */
662 0x3901, /* subs r1, r1, #1 */
663 0xD1F9, /* bne loop */
668 /* make sure we have a working area */
669 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
671 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
674 /* convert flash writing code into a buffer in target endianness */
675 for (i
= 0; i
< (sizeof(erase_check_code
)/sizeof(uint16_t)); i
++)
676 target_write_u16(target
, erase_check_algorithm
->address
+ i
*sizeof(uint16_t), erase_check_code
[i
]);
678 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
679 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
681 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
682 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
684 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
685 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
687 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
688 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
690 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
691 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-2), 10000, &armv7m_info
)) != ERROR_OK
)
693 destroy_reg_param(®_params
[0]);
694 destroy_reg_param(®_params
[1]);
695 destroy_reg_param(®_params
[2]);
696 target_free_working_area(target
, erase_check_algorithm
);
700 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
702 destroy_reg_param(®_params
[0]);
703 destroy_reg_param(®_params
[1]);
704 destroy_reg_param(®_params
[2]);
706 target_free_working_area(target
, erase_check_algorithm
);
712 * Return the debug ap baseaddress in hexadecimal;
713 * no extra output to simplify script processing
715 static int handle_dap_baseaddr_command(struct command_context_s
*cmd_ctx
,
716 char *cmd
, char **args
, int argc
)
718 target_t
*target
= get_current_target(cmd_ctx
);
719 armv7m_common_t
*armv7m
= target
->arch_info
;
720 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
721 uint32_t apsel
, apselsave
, baseaddr
;
724 apsel
= swjdp
->apsel
;
725 apselsave
= swjdp
->apsel
;
728 apsel
= strtoul(args
[0], NULL
, 0);
730 if (apselsave
!= apsel
)
732 dap_ap_select(swjdp
, apsel
);
735 dap_ap_read_reg_u32(swjdp
, 0xF8, &baseaddr
);
736 retval
= swjdp_transaction_endcheck(swjdp
);
737 command_print(cmd_ctx
, "0x%8.8" PRIx32
"", baseaddr
);
739 if (apselsave
!= apsel
)
741 dap_ap_select(swjdp
, apselsave
);
749 * Return the debug ap id in hexadecimal;
750 * no extra output to simplify script processing
752 extern int handle_dap_apid_command(struct command_context_s
*cmd_ctx
,
753 char *cmd
, char **args
, int argc
)
755 target_t
*target
= get_current_target(cmd_ctx
);
756 armv7m_common_t
*armv7m
= target
->arch_info
;
757 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
759 return dap_apid_command(cmd_ctx
, swjdp
, args
, argc
);
762 static int handle_dap_apsel_command(struct command_context_s
*cmd_ctx
,
763 char *cmd
, char **args
, int argc
)
765 target_t
*target
= get_current_target(cmd_ctx
);
766 armv7m_common_t
*armv7m
= target
->arch_info
;
767 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
769 return dap_apsel_command(cmd_ctx
, swjdp
, args
, argc
);
772 static int handle_dap_memaccess_command(struct command_context_s
*cmd_ctx
,
773 char *cmd
, char **args
, int argc
)
775 target_t
*target
= get_current_target(cmd_ctx
);
776 armv7m_common_t
*armv7m
= target
->arch_info
;
777 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
779 return dap_memaccess_command(cmd_ctx
, swjdp
, args
, argc
);
783 static int handle_dap_info_command(struct command_context_s
*cmd_ctx
,
784 char *cmd
, char **args
, int argc
)
786 target_t
*target
= get_current_target(cmd_ctx
);
787 armv7m_common_t
*armv7m
= target
->arch_info
;
788 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
791 apsel
= swjdp
->apsel
;
793 apsel
= strtoul(args
[0], NULL
, 0);
795 return dap_info_command(cmd_ctx
, swjdp
, apsel
);
798 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
800 command_t
*arm_adi_v5_dap_cmd
;
802 arm_adi_v5_dap_cmd
= register_command(cmd_ctx
, NULL
, "dap",
804 "cortex dap specific commands");
806 register_command(cmd_ctx
, arm_adi_v5_dap_cmd
, "info",
807 handle_dap_info_command
, COMMAND_EXEC
,
808 "Displays dap info for ap [num],"
809 "default currently selected AP");
810 register_command(cmd_ctx
, arm_adi_v5_dap_cmd
, "apsel",
811 handle_dap_apsel_command
, COMMAND_EXEC
,
812 "Select a different AP [num] (default 0)");
813 register_command(cmd_ctx
, arm_adi_v5_dap_cmd
, "apid",
814 handle_dap_apid_command
, COMMAND_EXEC
,
815 "Displays id reg from AP [num], "
816 "default currently selected AP");
817 register_command(cmd_ctx
, arm_adi_v5_dap_cmd
, "baseaddr",
818 handle_dap_baseaddr_command
, COMMAND_EXEC
,
819 "Displays debug base address from AP [num],"
820 "default currently selected AP");
821 register_command(cmd_ctx
, arm_adi_v5_dap_cmd
, "memaccess",
822 handle_dap_memaccess_command
, COMMAND_EXEC
,
823 "set/get number of extra tck for mem-ap "
824 "memory bus access [0-255]");
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