1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 char* armv7m_mode_strings
[] =
45 "Thread", "Thread (User)", "Handler",
48 char* armv7m_exception_strings
[] =
50 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
51 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
54 char* armv7m_core_reg_list
[] =
56 /* Registers accessed through core debug */
57 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
60 /* Registers accessed through special reg 20 */
61 "primask", "basepri", "faultmask", "control"
64 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
66 reg_t armv7m_gdb_dummy_fp_reg
=
68 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
71 u8 armv7m_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
73 reg_t armv7m_gdb_dummy_fps_reg
=
75 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
78 #ifdef ARMV7_GDB_HACKS
79 u8 armv7m_gdb_dummy_cpsr_value
[] = {0, 0, 0, 0};
81 reg_t armv7m_gdb_dummy_cpsr_reg
=
83 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value
, 0, 1, 32, NULL
, 0, NULL
, 0
87 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
89 /* CORE_GP are accesible using the core debug registers */
90 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
91 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
107 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
108 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
109 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
111 /* CORE_SP are accesible using coreregister 20 */
112 {19, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
113 {20, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
114 {21, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
115 {22, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
118 int armv7m_core_reg_arch_type
= -1;
120 int armv7m_restore_context(target_t
*target
)
124 /* get pointers to arch-specific information */
125 armv7m_common_t
*armv7m
= target
->arch_info
;
129 if (armv7m
->pre_restore_context
)
130 armv7m
->pre_restore_context(target
);
132 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
134 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
136 armv7m
->write_core_reg(target
, i
);
140 if (armv7m
->post_restore_context
)
141 armv7m
->post_restore_context(target
);
146 /* Core state functions */
147 char *armv7m_exception_string(int number
)
149 static char enamebuf
[32];
151 if ((number
< 0) | (number
> 511))
152 return "Invalid exception";
154 return armv7m_exception_strings
[number
];
155 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
159 int armv7m_get_core_reg(reg_t
*reg
)
162 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
163 target_t
*target
= armv7m_reg
->target
;
164 armv7m_common_t
*armv7m_target
= target
->arch_info
;
166 if (target
->state
!= TARGET_HALTED
)
168 return ERROR_TARGET_NOT_HALTED
;
171 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
176 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
178 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
179 target_t
*target
= armv7m_reg
->target
;
180 u32 value
= buf_get_u32(buf
, 0, 32);
182 if (target
->state
!= TARGET_HALTED
)
184 return ERROR_TARGET_NOT_HALTED
;
187 buf_set_u32(reg
->value
, 0, 32, value
);
194 int armv7m_read_core_reg(struct target_s
*target
, int num
)
198 armv7m_core_reg_t
* armv7m_core_reg
;
200 /* get pointers to arch-specific information */
201 armv7m_common_t
*armv7m
= target
->arch_info
;
203 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
204 return ERROR_INVALID_ARGUMENTS
;
206 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
207 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
208 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
209 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
210 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
215 int armv7m_write_core_reg(struct target_s
*target
, int num
)
219 armv7m_core_reg_t
*armv7m_core_reg
;
221 /* get pointers to arch-specific information */
222 armv7m_common_t
*armv7m
= target
->arch_info
;
224 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
225 return ERROR_INVALID_ARGUMENTS
;
227 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
228 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
229 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
230 if (retval
!= ERROR_OK
)
232 LOG_ERROR("JTAG failure");
233 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
234 return ERROR_JTAG_DEVICE_ERROR
;
236 LOG_DEBUG("write core reg %i value 0x%x", num
, reg_value
);
237 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
238 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
243 int armv7m_invalidate_core_regs(target_t
*target
)
245 /* get pointers to arch-specific information */
246 armv7m_common_t
*armv7m
= target
->arch_info
;
249 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
251 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
252 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
258 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
260 /* get pointers to arch-specific information */
261 armv7m_common_t
*armv7m
= target
->arch_info
;
265 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
267 for (i
= 0; i
< 16; i
++)
269 (*reg_list
)[i
] = &armv7m
->core_cache
->reg_list
[i
];
272 for (i
= 16; i
< 24; i
++)
274 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
277 (*reg_list
)[24] = &armv7m_gdb_dummy_fps_reg
;
279 #ifdef ARMV7_GDB_HACKS
280 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
281 (*reg_list
)[25] = &armv7m_gdb_dummy_cpsr_reg
;
283 /* ARMV7M is always in thumb mode, try to make GDB understand this
284 * if it does not support this arch */
285 armv7m
->core_cache
->reg_list
[15].value
[0] |= 1;
287 (*reg_list
)[25] = &armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
];
293 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
295 /* get pointers to arch-specific information */
296 armv7m_common_t
*armv7m
= target
->arch_info
;
297 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
298 enum armv7m_mode core_mode
= armv7m
->core_mode
;
299 int retval
= ERROR_OK
;
302 u32 context
[ARMV7NUMCOREREGS
];
304 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
306 LOG_ERROR("current target isn't an ARMV7M target");
307 return ERROR_TARGET_INVALID
;
310 if (target
->state
!= TARGET_HALTED
)
312 LOG_WARNING("target not halted");
313 return ERROR_TARGET_NOT_HALTED
;
316 /* refresh core register cache */
317 /* Not needed if core register cache is always consistent with target process state */
318 for (i
= 0; i
< ARMV7NUMCOREREGS
; i
++)
320 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
321 armv7m
->read_core_reg(target
, i
);
322 context
[i
] = buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
325 for (i
= 0; i
< num_mem_params
; i
++)
327 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
330 for (i
= 0; i
< num_reg_params
; i
++)
332 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
337 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
341 if (reg
->size
!= reg_params
[i
].size
)
343 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
347 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
348 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
351 if (armv7m_algorithm_info
->core_mode
!= ARMV7M_MODE_ANY
)
353 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
354 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1, armv7m_algorithm_info
->core_mode
);
355 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
356 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
359 /* ARMV7M always runs in Thumb state */
360 if ((retval
= breakpoint_add(target
, exit_point
, 2, BKPT_SOFT
)) != ERROR_OK
)
362 LOG_ERROR("can't add breakpoint to finish algorithm execution");
363 return ERROR_TARGET_FAILURE
;
366 /* This code relies on the target specific resume() and poll()->debug_entry()
367 sequence to write register values to the processor and the read them back */
368 target_resume(target
, 0, entry_point
, 1, 1);
371 while (target
->state
!= TARGET_HALTED
)
375 if ((timeout_ms
-= 5) <= 0)
377 LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
380 while (target
->state
!= TARGET_HALTED
)
384 if ((timeout_ms
-= 10) <= 0)
386 LOG_ERROR("target didn't reenter debug state, exiting");
390 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
391 LOG_DEBUG("failed algoritm halted at 0x%x ", pc
);
392 retval
= ERROR_TARGET_TIMEOUT
;
396 breakpoint_remove(target
, exit_point
);
398 /* Read memory values to mem_params[] */
399 for (i
= 0; i
< num_mem_params
; i
++)
401 if (mem_params
[i
].direction
!= PARAM_OUT
)
402 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
405 /* Copy core register values to reg_params[] */
406 for (i
= 0; i
< num_reg_params
; i
++)
408 if (reg_params
[i
].direction
!= PARAM_OUT
)
410 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
414 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
418 if (reg
->size
!= reg_params
[i
].size
)
420 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
424 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
428 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
430 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m
->core_cache
->reg_list
[i
].name
, context
[i
]);
431 buf_set_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32, context
[i
]);
432 armv7m
->core_cache
->reg_list
[i
].valid
= 1;
433 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
436 armv7m
->core_mode
= core_mode
;
441 int armv7m_arch_state(struct target_s
*target
)
443 /* get pointers to arch-specific information */
444 armv7m_common_t
*armv7m
= target
->arch_info
;
446 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
447 target_debug_reason_strings
[target
->debug_reason
],
448 armv7m_mode_strings
[armv7m
->core_mode
],
449 armv7m_exception_string(armv7m
->exception_number
),
450 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
451 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
456 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
458 /* get pointers to arch-specific information */
459 armv7m_common_t
*armv7m
= target
->arch_info
;
461 int num_regs
= ARMV7NUMCOREREGS
;
462 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
463 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
464 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
465 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
468 if (armv7m_core_reg_arch_type
== -1)
469 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
471 /* Build the process context cache */
472 cache
->name
= "arm v7m registers";
474 cache
->reg_list
= reg_list
;
475 cache
->num_regs
= num_regs
;
477 armv7m
->core_cache
= cache
;
479 for (i
= 0; i
< num_regs
; i
++)
481 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
482 arch_info
[i
].target
= target
;
483 arch_info
[i
].armv7m_common
= armv7m
;
484 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
485 reg_list
[i
].size
= 32;
486 reg_list
[i
].value
= calloc(1, 4);
487 reg_list
[i
].dirty
= 0;
488 reg_list
[i
].valid
= 0;
489 reg_list
[i
].bitfield_desc
= NULL
;
490 reg_list
[i
].num_bitfields
= 0;
491 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
492 reg_list
[i
].arch_info
= &arch_info
[i
];
498 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
500 armv7m_build_reg_cache(target
);
505 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
507 /* register arch-specific functions */
509 target
->arch_info
= armv7m
;
510 armv7m
->read_core_reg
= armv7m_read_core_reg
;
511 armv7m
->write_core_reg
= armv7m_write_core_reg
;
516 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
521 int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
523 working_area_t
*crc_algorithm
;
524 armv7m_algorithm_t armv7m_info
;
525 reg_param_t reg_params
[2];
528 u16 cortex_m3_crc_code
[] = {
529 0x4602, /* mov r2, r0 */
530 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
531 0x460B, /* mov r3, r1 */
532 0xF04F, 0x0400, /* mov r4, #0 */
533 0xE013, /* b ncomp */
535 0x5D11, /* ldrb r1, [r2, r4] */
536 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
537 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
539 0xF04F, 0x0500, /* mov r5, #0 */
541 0x2800, /* cmp r0, #0 */
542 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
543 0xF105, 0x0501, /* add r5, r5, #1 */
544 0x4630, /* mov r0, r6 */
546 0xEA86, 0x0007, /* eor r0, r6, r7 */
547 0x2D08, /* cmp r5, #8 */
548 0xD1F4, /* bne loop */
550 0xF104, 0x0401, /* add r4, r4, #1 */
552 0x429C, /* cmp r4, r3 */
553 0xD1E9, /* bne nbyte */
556 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
561 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
563 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
566 /* convert flash writing code into a buffer in target endianness */
567 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(u16
)); i
++)
568 target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(u16
), cortex_m3_crc_code
[i
]);
570 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
571 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
573 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
574 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
576 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
577 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
579 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
580 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
582 LOG_ERROR("error executing cortex_m3 crc algorithm");
583 destroy_reg_param(®_params
[0]);
584 destroy_reg_param(®_params
[1]);
585 target_free_working_area(target
, crc_algorithm
);
589 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
591 destroy_reg_param(®_params
[0]);
592 destroy_reg_param(®_params
[1]);
594 target_free_working_area(target
, crc_algorithm
);
599 int armv7m_blank_check_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* blank
)
601 working_area_t
*erase_check_algorithm
;
602 reg_param_t reg_params
[3];
603 armv7m_algorithm_t armv7m_info
;
607 u16 erase_check_code
[] =
610 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
611 0xEA02, 0x0203, /* and r2, r2, r3 */
612 0x3901, /* subs r1, r1, #1 */
613 0xD1F9, /* bne loop */
618 /* make sure we have a working area */
619 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
621 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
624 /* convert flash writing code into a buffer in target endianness */
625 for (i
= 0; i
< (sizeof(erase_check_code
)/sizeof(u16
)); i
++)
626 target_write_u16(target
, erase_check_algorithm
->address
+ i
*sizeof(u16
), erase_check_code
[i
]);
628 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
629 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
631 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
632 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
634 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
635 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
637 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
638 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
640 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
,
641 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-2), 10000, &armv7m_info
)) != ERROR_OK
)
643 destroy_reg_param(®_params
[0]);
644 destroy_reg_param(®_params
[1]);
645 destroy_reg_param(®_params
[2]);
646 target_free_working_area(target
, erase_check_algorithm
);
650 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
652 destroy_reg_param(®_params
[0]);
653 destroy_reg_param(®_params
[1]);
654 destroy_reg_param(®_params
[2]);
656 target_free_working_area(target
, erase_check_algorithm
);
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