1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
18 ***************************************************************************/
23 #include "arm_adi_v5.h"
25 #include "armv4_5_mmu.h"
26 #include "armv4_5_cache.h"
34 #define ARMV7_COMMON_MAGIC 0x0A450999
36 /* VA to PA translation operations opc2 values*/
45 /* L210/L220 cache controller support */
46 struct armv7a_l2x_cache
{
51 struct armv7a_cachesize
{
53 /* cache dimensionning */
55 uint32_t associativity
;
58 /* info for set way operation on cache */
65 struct armv7a_cache_common
{
67 struct armv7a_cachesize d_u_size
; /* data cache */
68 struct armv7a_cachesize i_size
; /* instruction cache */
70 int d_u_cache_enabled
;
71 /* l2 external unified cache if some */
73 int (*flush_all_data_cache
)(struct target
*target
);
74 int (*display_cache_info
)(struct command_context
*cmd_ctx
,
75 struct armv7a_cache_common
*armv7a_cache
);
78 struct armv7a_mmu_common
{
79 /* following field mmu working way */
81 int32_t ttbr1_used
; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
82 uint32_t ttbr0_mask
;/* masked to be used */
85 int (*read_physical_memory
)(struct target
*target
, uint32_t address
, uint32_t size
,
86 uint32_t count
, uint8_t *buffer
);
87 struct armv7a_cache_common armv7a_cache
;
91 struct armv7a_common
{
94 struct reg_cache
*core_cache
;
103 bool memory_ap_available
;
105 uint8_t multi_processor_system
;
113 uint32_t implementor
;
115 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
116 struct armv7a_mmu_common armv7a_mmu
;
118 int (*examine_debug_reason
)(struct target
*target
);
119 int (*post_debug_entry
)(struct target
*target
);
121 void (*pre_restore_context
)(struct target
*target
);
124 static inline struct armv7a_common
*
125 target_to_armv7a(struct target
*target
)
127 return container_of(target
->arch_info
, struct armv7a_common
, arm
);
130 /* register offsets from armv7a.debug_base */
132 /* See ARMv7a arch spec section C10.2 */
133 #define CPUDBG_DIDR 0x000
135 /* See ARMv7a arch spec section C10.3 */
136 #define CPUDBG_WFAR 0x018
137 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
138 #define CPUDBG_DSCR 0x088
139 #define CPUDBG_DRCR 0x090
140 #define CPUDBG_PRCR 0x310
141 #define CPUDBG_PRSR 0x314
143 /* See ARMv7a arch spec section C10.4 */
144 #define CPUDBG_DTRRX 0x080
145 #define CPUDBG_ITR 0x084
146 #define CPUDBG_DTRTX 0x08c
148 /* See ARMv7a arch spec section C10.5 */
149 #define CPUDBG_BVR_BASE 0x100
150 #define CPUDBG_BCR_BASE 0x140
151 #define CPUDBG_WVR_BASE 0x180
152 #define CPUDBG_WCR_BASE 0x1C0
153 #define CPUDBG_VCR 0x01C
155 /* See ARMv7a arch spec section C10.6 */
156 #define CPUDBG_OSLAR 0x300
157 #define CPUDBG_OSLSR 0x304
158 #define CPUDBG_OSSRR 0x308
159 #define CPUDBG_ECR 0x024
161 /* See ARMv7a arch spec section C10.7 */
162 #define CPUDBG_DSCCR 0x028
164 /* See ARMv7a arch spec section C10.8 */
165 #define CPUDBG_AUTHSTATUS 0xFB8
167 int armv7a_arch_state(struct target
*target
);
168 int armv7a_identify_cache(struct target
*target
);
169 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
);
170 int armv7a_mmu_translate_va_pa(struct target
*target
, uint32_t va
,
171 uint32_t *val
, int meminfo
);
172 int armv7a_mmu_translate_va(struct target
*target
, uint32_t va
, uint32_t *val
);
174 int armv7a_handle_cache_info_command(struct command_context
*cmd_ctx
,
175 struct armv7a_cache_common
*armv7a_cache
);
177 extern const struct command_registration armv7a_command_handlers
[];
179 #endif /* ARMV4_5_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)