1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
34 #include <helper/list.h>
37 /* three-bit ACK values for SWD access (sent LSB first) */
38 #define SWD_ACK_OK 0x1
39 #define SWD_ACK_WAIT 0x2
40 #define SWD_ACK_FAULT 0x4
45 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
47 /* A[3:0] for DP registers; A[1:0] are always zero.
48 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
49 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
50 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
52 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
53 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
54 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
55 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
56 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
57 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
58 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
59 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
60 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
61 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
62 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
64 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
66 /* Fields of the DP's AP ABORT register */
67 #define DAPABORT (1UL << 0)
68 #define STKCMPCLR (1UL << 1) /* SWD-only */
69 #define STKERRCLR (1UL << 2) /* SWD-only */
70 #define WDERRCLR (1UL << 3) /* SWD-only */
71 #define ORUNERRCLR (1UL << 4) /* SWD-only */
73 /* Fields of the DP's CTRL/STAT register */
74 #define CORUNDETECT (1UL << 0)
75 #define SSTICKYORUN (1UL << 1)
76 /* 3:2 - transaction mode (e.g. pushed compare) */
77 #define SSTICKYCMP (1UL << 4)
78 #define SSTICKYERR (1UL << 5)
79 #define READOK (1UL << 6) /* SWD-only */
80 #define WDATAERR (1UL << 7) /* SWD-only */
81 /* 11:8 - mask lanes for pushed compare or verify ops */
82 /* 21:12 - transaction counter */
83 #define CDBGRSTREQ (1UL << 26)
84 #define CDBGRSTACK (1UL << 27)
85 #define CDBGPWRUPREQ (1UL << 28)
86 #define CDBGPWRUPACK (1UL << 29)
87 #define CSYSPWRUPREQ (1UL << 30)
88 #define CSYSPWRUPACK (1UL << 31)
90 /* MEM-AP register addresses */
91 #define MEM_AP_REG_CSW 0x00
92 #define MEM_AP_REG_TAR 0x04
93 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
94 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
95 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
96 #define MEM_AP_REG_BD1 0x14
97 #define MEM_AP_REG_BD2 0x18
98 #define MEM_AP_REG_BD3 0x1C
99 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
100 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
101 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
102 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
103 /* Generic AP register address */
104 #define AP_REG_IDR 0xFC /* RO: Identification Register */
106 /* Fields of the MEM-AP's CSW register */
110 #define CSW_ADDRINC_MASK (3UL << 4)
111 #define CSW_ADDRINC_OFF 0UL
112 #define CSW_ADDRINC_SINGLE (1UL << 4)
113 #define CSW_ADDRINC_PACKED (2UL << 4)
114 #define CSW_DEVICE_EN (1UL << 6)
115 #define CSW_TRIN_PROG (1UL << 7)
116 #define CSW_SPIDEN (1UL << 23)
117 /* 30:24 - implementation-defined! */
118 #define CSW_HPROT (1UL << 25) /* ? */
119 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
120 #define CSW_SPROT (1UL << 30)
121 #define CSW_DBGSWENABLE (1UL << 31)
123 /* Fields of the MEM-AP's IDR register */
124 #define IDR_REV (0xFUL << 28)
125 #define IDR_JEP106 (0x7FFUL << 17)
126 #define IDR_CLASS (0xFUL << 13)
127 #define IDR_VARIANT (0xFUL << 4)
128 #define IDR_TYPE (0xFUL << 0)
130 #define IDR_JEP106_ARM 0x04760000
132 #define DP_SELECT_APSEL 0xFF000000
133 #define DP_SELECT_APBANK 0x000000F0
134 #define DP_SELECT_DPBANK 0x0000000F
135 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
138 * This represents an ARM Debug Interface (v5) Access Port (AP).
139 * Most common is a MEM-AP, for memory access.
143 * DAP this AP belongs to.
145 struct adiv5_dap
*dap
;
153 * Default value for (MEM-AP) AP_REG_CSW register.
155 uint32_t csw_default
;
158 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
159 * configure an access mode, such as autoincrementing AP_REG_TAR during
160 * word access. "-1" indicates no cached value.
165 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
166 * configure the address being read or written
167 * "-1" indicates no cached value.
172 * Configures how many extra tck clocks are added after starting a
173 * MEM-AP access before we try to read its status (and/or result).
175 uint32_t memaccess_tck
;
177 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
178 uint32_t tar_autoincr_block
;
180 /* true if packed transfers are supported by the MEM-AP */
181 bool packed_transfers
;
183 /* true if unaligned memory access is not supported by the MEM-AP */
184 bool unaligned_access_bad
;
189 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
190 * A DAP has two types of component: one Debug Port (DP), which is a
191 * transport agent; and at least one Access Port (AP), controlling
194 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
195 * Accordingly, this interface is responsible for hiding the transport
196 * differences so upper layer code can largely ignore them.
198 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
199 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
200 * a choice made at board design time (by only using the SWD pins), or
201 * as part of setting up a debug session (if all the dual-role JTAG/SWD
202 * signals are available).
205 const struct dap_ops
*ops
;
207 /* dap transaction list for WAIT support */
208 struct list_head cmd_journal
;
210 struct jtag_tap
*tap
;
212 uint32_t dp_ctrl_stat
;
214 struct adiv5_ap ap
[256];
216 /* The current manually selected AP by the "dap apsel" command */
220 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
221 * indicates no cached value and forces rewrite of the register.
225 /* information about current pending SWjDP-AHBAP transaction */
229 * Holds the pointer to the destination word for the last queued read,
230 * for use with posted AP read sequence optimization.
234 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
235 * despite lack of support in the ARMv7 architecture. Memory access through
236 * the AHB-AP has strange byte ordering these processors, and we need to
237 * swizzle appropriately. */
238 bool ti_be_32_quirks
;
241 * Signals that an attempt to reestablish communication afresh
242 * should be performed before the next access.
248 * Transport-neutral representation of queued DAP transactions, supporting
249 * both JTAG and SWD transports. All submitted transactions are logically
250 * queued, until the queue is executed by run(). Some implementations might
251 * execute transactions as soon as they're submitted, but no status is made
252 * available until run().
255 /** DP register read. */
256 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
258 /** DP register write. */
259 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
262 /** AP register read. */
263 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
265 /** AP register write. */
266 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
269 /** AP operation abort. */
270 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
272 /** Executes all queued DAP operations. */
273 int (*run
)(struct adiv5_dap
*dap
);
275 /** Executes all queued DAP operations but doesn't check
276 * sticky error conditions */
277 int (*sync
)(struct adiv5_dap
*dap
);
281 * Access Port classes
284 AP_CLASS_NONE
= 0x00000, /* No class defined */
285 AP_CLASS_MEM_AP
= 0x10000, /* MEM-AP */
292 AP_TYPE_JTAG_AP
= 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
293 AP_TYPE_AHB_AP
= 0x1, /* AHB Memory-AP */
294 AP_TYPE_APB_AP
= 0x2, /* APB Memory-AP */
295 AP_TYPE_AXI_AP
= 0x4, /* AXI Memory-AP */
299 * Queue a DP register read.
300 * Note that not all DP registers are readable; also, that JTAG and SWD
301 * have slight differences in DP register support.
303 * @param dap The DAP used for reading.
304 * @param reg The two-bit number of the DP register being read.
305 * @param data Pointer saying where to store the register's value
306 * (in host endianness).
308 * @return ERROR_OK for success, else a fault code.
310 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
311 unsigned reg
, uint32_t *data
)
313 assert(dap
->ops
!= NULL
);
314 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
318 * Queue a DP register write.
319 * Note that not all DP registers are writable; also, that JTAG and SWD
320 * have slight differences in DP register support.
322 * @param dap The DAP used for writing.
323 * @param reg The two-bit number of the DP register being written.
324 * @param data Value being written (host endianness)
326 * @return ERROR_OK for success, else a fault code.
328 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
329 unsigned reg
, uint32_t data
)
331 assert(dap
->ops
!= NULL
);
332 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
336 * Queue an AP register read.
338 * @param ap The AP used for reading.
339 * @param reg The number of the AP register being read.
340 * @param data Pointer saying where to store the register's value
341 * (in host endianness).
343 * @return ERROR_OK for success, else a fault code.
345 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
346 unsigned reg
, uint32_t *data
)
348 assert(ap
->dap
->ops
!= NULL
);
349 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
353 * Queue an AP register write.
355 * @param ap The AP used for writing.
356 * @param reg The number of the AP register being written.
357 * @param data Value being written (host endianness)
359 * @return ERROR_OK for success, else a fault code.
361 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
362 unsigned reg
, uint32_t data
)
364 assert(ap
->dap
->ops
!= NULL
);
365 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
369 * Queue an AP abort operation. The current AP transaction is aborted,
370 * including any update of the transaction counter. The AP is left in
371 * an unknown state (so it must be re-initialized). For use only after
372 * the AP has reported WAIT status for an extended period.
374 * @param dap The DAP used for writing.
375 * @param ack Pointer to where transaction status will be stored.
377 * @return ERROR_OK for success, else a fault code.
379 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
381 assert(dap
->ops
!= NULL
);
382 return dap
->ops
->queue_ap_abort(dap
, ack
);
386 * Perform all queued DAP operations, and clear any errors posted in the
387 * CTRL_STAT register when they are done. Note that if more than one AP
388 * operation will be queued, one of the first operations in the queue
389 * should probably enable CORUNDETECT in the CTRL/STAT register.
391 * @param dap The DAP used.
393 * @return ERROR_OK for success, else a fault code.
395 static inline int dap_run(struct adiv5_dap
*dap
)
397 assert(dap
->ops
!= NULL
);
398 return dap
->ops
->run(dap
);
401 static inline int dap_sync(struct adiv5_dap
*dap
)
403 assert(dap
->ops
!= NULL
);
405 return dap
->ops
->sync(dap
);
409 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
414 retval
= dap_queue_dp_read(dap
, reg
, value
);
415 if (retval
!= ERROR_OK
)
421 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
422 uint32_t mask
, uint32_t value
, int timeout
)
425 assert((value
& mask
) == value
);
429 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
432 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
436 if ((regval
& mask
) == value
)
443 LOG_DEBUG("DAP: poll %x timeout", reg
);
450 /* Queued MEM-AP memory mapped single word transfers. */
451 int mem_ap_read_u32(struct adiv5_ap
*ap
,
452 uint32_t address
, uint32_t *value
);
453 int mem_ap_write_u32(struct adiv5_ap
*ap
,
454 uint32_t address
, uint32_t value
);
456 /* Synchronous MEM-AP memory mapped single word transfers. */
457 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
458 uint32_t address
, uint32_t *value
);
459 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
460 uint32_t address
, uint32_t value
);
462 /* Synchronous MEM-AP memory mapped bus block transfers. */
463 int mem_ap_read_buf(struct adiv5_ap
*ap
,
464 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
465 int mem_ap_write_buf(struct adiv5_ap
*ap
,
466 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
468 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
469 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
470 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
471 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
472 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
);
474 /* Create DAP struct */
475 struct adiv5_dap
*dap_init(void);
477 /* Initialisation of the debug system, power domains and registers */
478 int dap_dp_init(struct adiv5_dap
*dap
);
479 int mem_ap_init(struct adiv5_ap
*ap
);
481 /* Probe the AP for ROM Table location */
482 int dap_get_debugbase(struct adiv5_ap
*ap
,
483 uint32_t *dbgbase
, uint32_t *apid
);
485 /* Probe Access Ports to find a particular type */
486 int dap_find_ap(struct adiv5_dap
*dap
,
487 enum ap_type type_to_find
,
488 struct adiv5_ap
**ap_out
);
490 static inline struct adiv5_ap
*dap_ap(struct adiv5_dap
*dap
, uint8_t ap_num
)
492 return &dap
->ap
[ap_num
];
495 /* Lookup CoreSight component */
496 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
497 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
);
501 /* Put debug link into SWD mode */
502 int dap_to_swd(struct target
*target
);
504 /* Put debug link into JTAG mode */
505 int dap_to_jtag(struct target
*target
);
507 extern const struct command_registration dap_command_handlers
[];
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