1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
36 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #define FNC_INFO LOG_DEBUG("-")
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #define FNC_INFO_NOTIMPLEMENTED
51 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
);
53 bool arm11_config_memwrite_burst
= true;
54 bool arm11_config_memwrite_error_fatal
= true;
56 bool arm11_config_memrw_no_increment
= false;
57 bool arm11_config_step_irq_enable
= false;
59 #define ARM11_HANDLER(x) \
62 target_type_t arm11_target
=
67 ARM11_HANDLER(arch_state
),
69 ARM11_HANDLER(target_request_data
),
72 ARM11_HANDLER(resume
),
75 ARM11_HANDLER(assert_reset
),
76 ARM11_HANDLER(deassert_reset
),
77 ARM11_HANDLER(soft_reset_halt
),
79 ARM11_HANDLER(get_gdb_reg_list
),
81 ARM11_HANDLER(read_memory
),
82 ARM11_HANDLER(write_memory
),
84 ARM11_HANDLER(bulk_write_memory
),
86 ARM11_HANDLER(checksum_memory
),
88 ARM11_HANDLER(add_breakpoint
),
89 ARM11_HANDLER(remove_breakpoint
),
90 ARM11_HANDLER(add_watchpoint
),
91 ARM11_HANDLER(remove_watchpoint
),
93 ARM11_HANDLER(run_algorithm
),
95 ARM11_HANDLER(register_commands
),
96 ARM11_HANDLER(target_create
),
97 ARM11_HANDLER(init_target
),
98 ARM11_HANDLER(examine
),
102 int arm11_regs_arch_type
= -1;
120 ARM11_REGISTER_SPSR_FIQ
,
121 ARM11_REGISTER_SPSR_SVC
,
122 ARM11_REGISTER_SPSR_ABT
,
123 ARM11_REGISTER_SPSR_IRQ
,
124 ARM11_REGISTER_SPSR_UND
,
125 ARM11_REGISTER_SPSR_MON
,
134 typedef struct arm11_reg_defs_s
139 enum arm11_regtype type
;
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs
[] =
145 {"r0", 0, 0, ARM11_REGISTER_CORE
},
146 {"r1", 1, 1, ARM11_REGISTER_CORE
},
147 {"r2", 2, 2, ARM11_REGISTER_CORE
},
148 {"r3", 3, 3, ARM11_REGISTER_CORE
},
149 {"r4", 4, 4, ARM11_REGISTER_CORE
},
150 {"r5", 5, 5, ARM11_REGISTER_CORE
},
151 {"r6", 6, 6, ARM11_REGISTER_CORE
},
152 {"r7", 7, 7, ARM11_REGISTER_CORE
},
153 {"r8", 8, 8, ARM11_REGISTER_CORE
},
154 {"r9", 9, 9, ARM11_REGISTER_CORE
},
155 {"r10", 10, 10, ARM11_REGISTER_CORE
},
156 {"r11", 11, 11, ARM11_REGISTER_CORE
},
157 {"r12", 12, 12, ARM11_REGISTER_CORE
},
158 {"sp", 13, 13, ARM11_REGISTER_CORE
},
159 {"lr", 14, 14, ARM11_REGISTER_CORE
},
160 {"pc", 15, 15, ARM11_REGISTER_CORE
},
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX
},
164 {"f1", 1, 17, ARM11_REGISTER_FX
},
165 {"f2", 2, 18, ARM11_REGISTER_FX
},
166 {"f3", 3, 19, ARM11_REGISTER_FX
},
167 {"f4", 4, 20, ARM11_REGISTER_FX
},
168 {"f5", 5, 21, ARM11_REGISTER_FX
},
169 {"f6", 6, 22, ARM11_REGISTER_FX
},
170 {"f7", 7, 23, ARM11_REGISTER_FX
},
171 {"fps", 0, 24, ARM11_REGISTER_FPS
},
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
198 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
214 enum arm11_regcache_ids
217 ARM11_RC_RX
= ARM11_RC_R0
,
232 ARM11_RC_SP
= ARM11_RC_R13
,
234 ARM11_RC_LR
= ARM11_RC_R14
,
236 ARM11_RC_PC
= ARM11_RC_R15
,
238 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_FX
= ARM11_RC_F0
,
253 #if ARM11_REGCACHE_MODEREGS
291 #define ARM11_GDB_REGISTER_COUNT 26
293 u8 arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295 reg_t arm11_gdb_dummy_fp_reg
=
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
300 u8 arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
302 reg_t arm11_gdb_dummy_fps_reg
=
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
309 /** Check and if necessary take control of the system
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
316 int arm11_check_init(arm11_common_t
* arm11
, u32
* dscr
)
320 u32 dscr_local_tmp_copy
;
324 dscr
= &dscr_local_tmp_copy
;
326 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
329 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
331 LOG_DEBUG("Bringing target into debug mode");
333 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
334 arm11_write_DSCR(arm11
, *dscr
);
336 /* add further reset initialization here */
338 arm11
->simulate_reset_on_next_halt
= true;
340 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called
346 arm11
->target
->state
= TARGET_HALTED
;
347 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
351 arm11
->target
->state
= TARGET_RUNNING
;
352 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
355 arm11_sc7_clear_vbw(arm11
);
364 (arm11->reg_values[ARM11_RC_##x])
366 /** Save processor state.
368 * This is called when the HALT instruction has succeeded
369 * or on other occasions that stop the processor.
372 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
)
377 for(i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
379 arm11
->reg_list
[i
].valid
= 1;
380 arm11
->reg_list
[i
].dirty
= 0;
384 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
388 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
390 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
392 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
394 scan_field_t chain5_fields
[3];
396 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
397 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
398 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
400 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
404 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
408 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
409 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
410 ARM1136 seems to require this to issue ITR's as well */
412 u32 new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
414 /* this executes JTAG queue: */
416 arm11_write_DSCR(arm11
, new_dscr
);
420 Before executing any instruction in debug state you have to drain the write buffer.
421 This ensures that no imprecise Data Aborts can return at a later point:*/
423 /** \todo TODO: Test drain write buffer. */
428 /* MRC p14,0,R0,c5,c10,0 */
429 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
431 /* mcr 15, 0, r0, cr7, cr10, {4} */
432 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
434 u32 dscr
= arm11_read_DSCR(arm11
);
436 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
438 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
440 arm11_run_instr_no_data1(arm11
, 0xe320f000);
442 dscr
= arm11_read_DSCR(arm11
);
444 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
451 arm11_run_instr_data_prepare(arm11
);
455 /** \todo TODO: handle other mode registers */
458 for (i
= 0; i
< 15; i
++)
460 /* MCR p14,0,R?,c0,c5,0 */
461 arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
466 /* check rDTRfull in DSCR */
468 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
475 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
488 /* adjust PC depending on ARM state */
490 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
492 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
494 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
496 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
500 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
503 if (arm11
->simulate_reset_on_next_halt
)
505 arm11
->simulate_reset_on_next_halt
= false;
507 LOG_DEBUG("Reset c1 Control Register");
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
516 arm11_run_instr_data_finish(arm11
);
518 arm11_dump_reg_changes(arm11
);
523 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
526 if (!(debug_level
>= LOG_LVL_DEBUG
))
532 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
534 if (!arm11
->reg_list
[i
].valid
)
536 if (arm11
->reg_history
[i
].valid
)
537 LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
541 if (arm11
->reg_history
[i
].valid
)
543 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
544 LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
548 LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
554 /** Restore processor state
556 * This is called in preparation for the RESTART function.
559 int arm11_leave_debug_state(arm11_common_t
* arm11
)
563 arm11_run_instr_data_prepare(arm11
);
565 /** \todo TODO: handle other mode registers */
567 /* restore R1 - R14 */
569 for (i
= 1; i
< 15; i
++)
571 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
574 /* MRC p14,0,r?,c0,c5,0 */
575 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
577 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
580 arm11_run_instr_data_finish(arm11
);
582 /* spec says clear wDTR and rDTR; we assume they are clear as
583 otherwise our programming would be sloppy */
587 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
589 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
591 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR
);
595 arm11_run_instr_data_prepare(arm11
);
597 /* restore original wDTR */
599 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
601 /* MCR p14,0,R0,c0,c5,0 */
602 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
608 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
613 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
617 /* MRC p14,0,r0,c0,c5,0 */
618 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
620 arm11_run_instr_data_finish(arm11
);
624 arm11_write_DSCR(arm11
, R(DSCR
));
628 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
630 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
632 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
634 scan_field_t chain5_fields
[3];
636 u8 Ready
= 0; /* ignored */
637 u8 Valid
= 0; /* ignored */
639 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
640 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
641 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
643 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
646 arm11_record_register_history(arm11
);
651 void arm11_record_register_history(arm11_common_t
* arm11
)
654 for(i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
656 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
657 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
659 arm11
->reg_list
[i
].valid
= 0;
660 arm11
->reg_list
[i
].dirty
= 0;
665 /* poll current target status */
666 int arm11_poll(struct target_s
*target
)
670 arm11_common_t
* arm11
= target
->arch_info
;
672 if (arm11
->trst_active
)
677 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
679 LOG_DEBUG("DSCR %08x", dscr
);
681 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
683 if (dscr
& ARM11_DSCR_CORE_HALTED
)
685 if (target
->state
!= TARGET_HALTED
)
687 enum target_state old_state
= target
->state
;
689 LOG_DEBUG("enter TARGET_HALTED");
690 target
->state
= TARGET_HALTED
;
691 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
692 arm11_on_enter_debug_state(arm11
);
694 target_call_event_callbacks(target
,
695 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
700 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
702 LOG_DEBUG("enter TARGET_RUNNING");
703 target
->state
= TARGET_RUNNING
;
704 target
->debug_reason
= DBG_REASON_NOTHALTED
;
710 /* architecture specific status reply */
711 int arm11_arch_state(struct target_s
*target
)
713 arm11_common_t
* arm11
= target
->arch_info
;
715 LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
716 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
723 /* target request support */
724 int arm11_target_request_data(struct target_s
*target
, u32 size
, u8
*buffer
)
726 FNC_INFO_NOTIMPLEMENTED
;
731 /* target execution control */
732 int arm11_halt(struct target_s
*target
)
736 arm11_common_t
* arm11
= target
->arch_info
;
738 LOG_DEBUG("target->state: %s",
739 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
741 if (target
->state
== TARGET_UNKNOWN
)
743 arm11
->simulate_reset_on_next_halt
= true;
746 if (target
->state
== TARGET_HALTED
)
748 LOG_DEBUG("target was already halted");
752 if (arm11
->trst_active
)
754 arm11
->halt_requested
= true;
758 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
760 CHECK_RETVAL(jtag_execute_queue());
766 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
768 if (dscr
& ARM11_DSCR_CORE_HALTED
)
772 arm11_on_enter_debug_state(arm11
);
774 enum target_state old_state
= target
->state
;
776 target
->state
= TARGET_HALTED
;
777 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
780 target_call_event_callbacks(target
,
781 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
786 int arm11_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
790 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
791 // current, address, handle_breakpoints, debug_execution);
793 arm11_common_t
* arm11
= target
->arch_info
;
795 LOG_DEBUG("target->state: %s",
796 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
799 if (target
->state
!= TARGET_HALTED
)
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED
;
808 LOG_DEBUG("RESUME PC %08x%s", R(PC
), !current
? "!" : "");
810 /* clear breakpoints/watchpoints and VCR*/
811 arm11_sc7_clear_vbw(arm11
);
813 /* Set up breakpoints */
814 if (!debug_execution
)
816 /* check if one matches PC and step over it if necessary */
820 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
822 if (bp
->address
== R(PC
))
824 LOG_DEBUG("must step over %08x", bp
->address
);
825 arm11_step(target
, 1, 0, 0);
830 /* set all breakpoints */
834 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
836 arm11_sc7_action_t brp
[2];
839 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
840 brp
[0].value
= bp
->address
;
842 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
843 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
845 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
847 LOG_DEBUG("Add BP " ZU
" at %08x", brp_num
, bp
->address
);
852 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
855 arm11_leave_debug_state(arm11
);
857 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
859 CHECK_RETVAL(jtag_execute_queue());
865 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
867 LOG_DEBUG("DSCR %08x", dscr
);
869 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
873 if (!debug_execution
)
875 target
->state
= TARGET_RUNNING
;
876 target
->debug_reason
= DBG_REASON_NOTHALTED
;
878 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
882 target
->state
= TARGET_DEBUG_RUNNING
;
883 target
->debug_reason
= DBG_REASON_NOTHALTED
;
885 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
891 int arm11_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
895 LOG_DEBUG("target->state: %s",
896 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
898 if (target
->state
!= TARGET_HALTED
)
900 LOG_WARNING("target was not halted");
901 return ERROR_TARGET_NOT_HALTED
;
904 arm11_common_t
* arm11
= target
->arch_info
;
909 LOG_INFO("STEP PC %08x%s", R(PC
), !current
? "!" : "");
911 /** \todo TODO: Thumb not supported here */
913 u32 next_instruction
;
915 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
918 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
921 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
922 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
923 LOG_INFO("Skipping BKPT");
925 /* skip over Wait for interrupt / Standby */
926 /* mcr 15, 0, r?, cr7, cr0, {4} */
927 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
930 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
931 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
932 LOG_INFO("Skipping WFI");
934 /* ignore B to self */
935 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
937 LOG_INFO("Not stepping jump to self");
941 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
944 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
945 * the VCR might be something worth looking into. */
948 /* Set up breakpoint for stepping */
950 arm11_sc7_action_t brp
[2];
953 brp
[0].address
= ARM11_SC7_BVR0
;
954 brp
[0].value
= R(PC
);
956 brp
[1].address
= ARM11_SC7_BCR0
;
957 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
959 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, asizeof(brp
)));
964 if (arm11_config_step_irq_enable
)
965 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
967 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
970 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
972 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
974 CHECK_RETVAL(jtag_execute_queue());
976 /** \todo TODO: add a timeout */
984 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
986 LOG_DEBUG("DSCR %08x", dscr
);
988 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
989 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
993 /* clear breakpoint */
994 arm11_sc7_clear_vbw(arm11
);
997 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
999 /* restore default state */
1000 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1004 // target->state = TARGET_HALTED;
1005 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1007 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1012 /* target reset control */
1013 int arm11_assert_reset(struct target_s
*target
)
1018 /* assert reset lines */
1019 /* resets only the DBGTAP, not the ARM */
1021 jtag_add_reset(1, 0);
1022 jtag_add_sleep(5000);
1024 arm11_common_t
* arm11
= target
->arch_info
;
1025 arm11
->trst_active
= true;
1028 if (target
->reset_halt
)
1030 CHECK_RETVAL(target_halt(target
));
1036 int arm11_deassert_reset(struct target_s
*target
)
1041 LOG_DEBUG("target->state: %s",
1042 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
1045 /* deassert reset lines */
1046 jtag_add_reset(0, 0);
1048 arm11_common_t
* arm11
= target
->arch_info
;
1049 arm11
->trst_active
= false;
1051 if (arm11
->halt_requested
)
1052 return arm11_halt(target
);
1058 int arm11_soft_reset_halt(struct target_s
*target
)
1060 FNC_INFO_NOTIMPLEMENTED
;
1065 /* target register access for gdb */
1066 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1070 arm11_common_t
* arm11
= target
->arch_info
;
1072 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1073 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1076 for (i
= 16; i
< 24; i
++)
1078 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1081 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1084 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1086 if (arm11_reg_defs
[i
].gdb_num
== -1)
1089 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1095 /* target memory access
1096 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1097 * count: number of items of <size>
1099 int arm11_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1101 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1105 if (target
->state
!= TARGET_HALTED
)
1107 LOG_WARNING("target was not halted");
1108 return ERROR_TARGET_NOT_HALTED
;
1111 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1113 arm11_common_t
* arm11
= target
->arch_info
;
1115 arm11_run_instr_data_prepare(arm11
);
1117 /* MRC p14,0,r0,c0,c5,0 */
1118 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1123 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1124 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1127 for (i
= 0; i
< count
; i
++)
1129 /* ldrb r1, [r0], #1 */
1131 arm11_run_instr_no_data1(arm11
,
1132 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1135 /* MCR p14,0,R1,c0,c5,0 */
1136 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1145 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1147 u16
* buf16
= (u16
*)buffer
;
1150 for (i
= 0; i
< count
; i
++)
1152 /* ldrh r1, [r0], #2 */
1153 arm11_run_instr_no_data1(arm11
,
1154 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1158 /* MCR p14,0,R1,c0,c5,0 */
1159 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1169 /* LDC p14,c5,[R0],#4 */
1170 /* LDC p14,c5,[R0] */
1171 arm11_run_instr_data_from_core(arm11
,
1172 (!arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00),
1173 (u32
*)buffer
, count
);
1177 arm11_run_instr_data_finish(arm11
);
1182 int arm11_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1186 if (target
->state
!= TARGET_HALTED
)
1188 LOG_WARNING("target was not halted");
1189 return ERROR_TARGET_NOT_HALTED
;
1192 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address
, size
, count
);
1194 arm11_common_t
* arm11
= target
->arch_info
;
1196 arm11_run_instr_data_prepare(arm11
);
1198 /* MRC p14,0,r0,c0,c5,0 */
1199 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1205 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1208 for (i
= 0; i
< count
; i
++)
1210 /* MRC p14,0,r1,c0,c5,0 */
1211 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1213 /* strb r1, [r0], #1 */
1215 arm11_run_instr_no_data1(arm11
,
1216 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1224 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1226 u16
* buf16
= (u16
*)buffer
;
1229 for (i
= 0; i
< count
; i
++)
1231 /* MRC p14,0,r1,c0,c5,0 */
1232 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buf16
++);
1234 /* strh r1, [r0], #2 */
1236 arm11_run_instr_no_data1(arm11
,
1237 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1244 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1246 if (!arm11_config_memwrite_burst
)
1248 /* STC p14,c5,[R0],#4 */
1249 /* STC p14,c5,[R0]*/
1250 arm11_run_instr_data_to_core(arm11
,
1251 (!arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00),
1252 (u32
*)buffer
, count
);
1256 /* STC p14,c5,[R0],#4 */
1257 /* STC p14,c5,[R0]*/
1258 arm11_run_instr_data_to_core_noack(arm11
,
1259 (!arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00),
1260 (u32
*)buffer
, count
);
1267 /* r0 verification */
1268 if (!arm11_config_memrw_no_increment
)
1272 /* MCR p14,0,R0,c0,c5,0 */
1273 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1275 if (address
+ size
* count
!= r0
)
1277 LOG_ERROR("Data transfer failed. (%d)", (r0
- address
) - size
* count
);
1279 if (arm11_config_memwrite_burst
)
1280 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1282 if (arm11_config_memwrite_error_fatal
)
1288 arm11_run_instr_data_finish(arm11
);
1294 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1295 int arm11_bulk_write_memory(struct target_s
*target
, u32 address
, u32 count
, u8
*buffer
)
1299 if (target
->state
!= TARGET_HALTED
)
1301 LOG_WARNING("target was not halted");
1302 return ERROR_TARGET_NOT_HALTED
;
1305 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1308 int arm11_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
1310 FNC_INFO_NOTIMPLEMENTED
;
1315 /* target break-/watchpoint control
1316 * rw: 0 = write, 1 = read, 2 = access
1318 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1322 arm11_common_t
* arm11
= target
->arch_info
;
1325 if (breakpoint
->type
== BKPT_SOFT
)
1327 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1328 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1332 if (!arm11
->free_brps
)
1334 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1335 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1338 if (breakpoint
->length
!= 4)
1340 LOG_INFO("only breakpoints of four bytes length supported");
1341 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1349 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1353 arm11_common_t
* arm11
= target
->arch_info
;
1360 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1362 FNC_INFO_NOTIMPLEMENTED
;
1367 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1369 FNC_INFO_NOTIMPLEMENTED
;
1374 // HACKHACKHACK - FIXME mode/state
1375 /* target algorithm support */
1376 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
,
1377 int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
,
1378 int timeout_ms
, void *arch_info
)
1380 arm11_common_t
*arm11
= target
->arch_info
;
1381 armv4_5_algorithm_t
*arm11_algorithm_info
= arch_info
;
1382 // enum armv4_5_state core_state = arm11->core_state;
1383 // enum armv4_5_mode core_mode = arm11->core_mode;
1386 int exit_breakpoint_size
= 0;
1388 int retval
= ERROR_OK
;
1389 LOG_DEBUG("Running algorithm");
1391 if (arm11_algorithm_info
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
1393 LOG_ERROR("current target isn't an ARMV4/5 target");
1394 return ERROR_TARGET_INVALID
;
1397 if (target
->state
!= TARGET_HALTED
)
1399 LOG_WARNING("target not halted");
1400 return ERROR_TARGET_NOT_HALTED
;
1404 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1405 // return ERROR_FAIL;
1408 for (i
= 0; i
< 16; i
++)
1410 context
[i
] = buf_get_u32((u8
*)(&arm11
->reg_values
[i
]),0,32);
1411 LOG_DEBUG("Save %i: 0x%x",i
,context
[i
]);
1414 cpsr
= buf_get_u32((u8
*)(arm11
->reg_values
+ARM11_RC_CPSR
),0,32);
1415 LOG_DEBUG("Save CPSR: 0x%x", cpsr
);
1417 for (i
= 0; i
< num_mem_params
; i
++)
1419 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1422 // Set register parameters
1423 for (i
= 0; i
< num_reg_params
; i
++)
1425 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1428 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1432 if (reg
->size
!= reg_params
[i
].size
)
1434 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1437 arm11_set_reg(reg
,reg_params
[i
].value
);
1438 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1441 exit_breakpoint_size
= 4;
1443 /* arm11->core_state = arm11_algorithm_info->core_state;
1444 if (arm11->core_state == ARMV4_5_STATE_ARM)
1445 exit_breakpoint_size = 4;
1446 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1447 exit_breakpoint_size = 2;
1450 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1454 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1456 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1457 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1458 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1459 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1462 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1464 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1465 retval
= ERROR_TARGET_FAILURE
;
1469 // no debug, otherwise breakpoint is not set
1470 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1472 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1474 if (target
->state
!= TARGET_HALTED
)
1476 CHECK_RETVAL(target_halt(target
));
1478 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1480 retval
= ERROR_TARGET_TIMEOUT
;
1482 goto del_breakpoint
;
1485 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1487 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1488 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1489 retval
= ERROR_TARGET_TIMEOUT
;
1490 goto del_breakpoint
;
1493 for (i
= 0; i
< num_mem_params
; i
++)
1495 if (mem_params
[i
].direction
!= PARAM_OUT
)
1496 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1499 for (i
= 0; i
< num_reg_params
; i
++)
1501 if (reg_params
[i
].direction
!= PARAM_OUT
)
1503 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1506 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1510 if (reg
->size
!= reg_params
[i
].size
)
1512 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1516 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1521 breakpoint_remove(target
, exit_point
);
1525 for (i
= 0; i
< 16; i
++)
1527 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1528 arm11
->reg_list
[i
].name
, context
[i
]);
1529 arm11_set_reg(&arm11
->reg_list
[i
], (u8
*)&context
[i
]);
1531 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr
);
1532 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (u8
*)&cpsr
);
1534 // arm11->core_state = core_state;
1535 // arm11->core_mode = core_mode;
1540 int arm11_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1544 NEW(arm11_common_t
, arm11
, 1);
1546 arm11
->target
= target
;
1548 /* prepare JTAG information for the new target */
1549 arm11
->jtag_info
.tap
= target
->tap
;
1550 arm11
->jtag_info
.scann_size
= 5;
1552 CHECK_RETVAL(arm_jtag_setup_connection(&arm11
->jtag_info
));
1554 if (target
->tap
==NULL
)
1557 if (target
->tap
->ir_length
!= 5)
1559 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1560 return ERROR_COMMAND_SYNTAX_ERROR
;
1563 target
->arch_info
= arm11
;
1568 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1570 /* Initialize anything we can set up without talking to the target */
1571 return arm11_build_reg_cache(target
);
1574 /* talk to the target and set things up */
1575 int arm11_examine(struct target_s
*target
)
1579 arm11_common_t
* arm11
= target
->arch_info
;
1583 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1585 scan_field_t idcode_field
;
1587 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1589 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1593 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1595 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1597 scan_field_t chain0_fields
[2];
1599 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1600 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1602 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1604 CHECK_RETVAL(jtag_execute_queue());
1606 switch (arm11
->device_id
& 0x0FFFF000)
1608 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1609 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1610 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1613 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1618 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1620 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1621 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1623 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1627 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1628 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1630 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1631 arm11
->free_brps
= arm11
->brp
;
1632 arm11
->free_wrps
= arm11
->wrp
;
1634 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1639 /* as a side-effect this reads DSCR and thus
1640 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1641 * as suggested by the spec.
1644 arm11_check_init(arm11
, NULL
);
1646 target
->type
->examined
= 1;
1651 int arm11_quit(void)
1653 FNC_INFO_NOTIMPLEMENTED
;
1658 /** Load a register that is marked !valid in the register cache */
1659 int arm11_get_reg(reg_t
*reg
)
1663 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1665 if (target
->state
!= TARGET_HALTED
)
1667 LOG_WARNING("target was not halted");
1668 return ERROR_TARGET_NOT_HALTED
;
1671 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1674 arm11_common_t
*arm11
= target
->arch_info
;
1675 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1681 /** Change a value in the register cache */
1682 int arm11_set_reg(reg_t
*reg
, u8
*buf
)
1686 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1687 arm11_common_t
*arm11
= target
->arch_info
;
1688 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1690 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1697 int arm11_build_reg_cache(target_t
*target
)
1699 arm11_common_t
*arm11
= target
->arch_info
;
1701 NEW(reg_cache_t
, cache
, 1);
1702 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1703 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1705 if (arm11_regs_arch_type
== -1)
1706 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1708 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1709 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1711 arm11
->reg_list
= reg_list
;
1713 /* Build the process context cache */
1714 cache
->name
= "arm11 registers";
1716 cache
->reg_list
= reg_list
;
1717 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1719 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1722 arm11
->core_cache
= cache
;
1723 // armv7m->process_context = cache;
1727 /* Not very elegant assertion */
1728 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1729 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1730 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1732 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1736 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1738 reg_t
* r
= reg_list
+ i
;
1739 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1740 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1744 r
->value
= (u8
*)(arm11
->reg_values
+ i
);
1747 r
->bitfield_desc
= NULL
;
1748 r
->num_bitfields
= 0;
1749 r
->arch_type
= arm11_regs_arch_type
;
1753 rs
->target
= target
;
1759 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1763 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1768 return ERROR_COMMAND_SYNTAX_ERROR
;
1773 case 'f': /* false */
1775 case 'd': /* disable */
1781 case 't': /* true */
1783 case 'e': /* enable */
1789 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
1794 #define BOOL_WRAPPER(name, print_name) \
1795 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1797 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1800 #define RC_TOP(name, descr, more) \
1802 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1803 command_t * top_cmd = new_cmd; \
1807 #define RC_FINAL(name, descr, handler) \
1808 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1810 #define RC_FINAL_BOOL(name, descr, var) \
1811 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1813 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1814 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1815 BOOL_WRAPPER(memrw_no_increment
, "\"no increment\" mode for memory transfers")
1816 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1818 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1822 arm11_vcr
= strtoul(args
[0], NULL
, 0);
1826 return ERROR_COMMAND_SYNTAX_ERROR
;
1829 LOG_INFO("VCR 0x%08X", arm11_vcr
);
1833 const u32 arm11_coproc_instruction_limits
[] =
1835 15, /* coprocessor */
1840 0xFFFFFFFF, /* value */
1843 const char arm11_mrc_syntax
[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1844 const char arm11_mcr_syntax
[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1846 arm11_common_t
* arm11_find_target(const char * arg
)
1851 tap
= jtag_TapByString(arg
);
1856 for (t
= all_targets
; t
; t
= t
->next
)
1861 /* if (t->type == arm11_target) */
1862 if (0 == strcmp(t
->type
->name
, "arm11"))
1863 return t
->arch_info
;
1869 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
1871 if (argc
!= (read
? 6 : 7))
1873 LOG_ERROR("Invalid number of arguments. %s", read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1877 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
1881 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1882 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1887 if (arm11
->target
->state
!= TARGET_HALTED
)
1889 LOG_WARNING("target was not halted");
1890 return ERROR_TARGET_NOT_HALTED
;
1896 for (i
= 0; i
< (read
? 5 : 6); i
++)
1898 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
1900 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
1902 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1903 (long)(i
+ 2), arm11_coproc_instruction_limits
[i
],
1904 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1909 u32 instr
= 0xEE000010 |
1917 instr
|= 0x00100000;
1919 arm11_run_instr_data_prepare(arm11
);
1924 arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
1926 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1927 values
[0], values
[1], values
[2], values
[3], values
[4], result
, result
);
1931 arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
1933 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1934 values
[0], values
[1],
1936 values
[2], values
[3], values
[4]);
1939 arm11_run_instr_data_finish(arm11
);
1945 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1947 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
1950 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1952 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
1955 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
1959 command_t
* top_cmd
= NULL
;
1961 RC_TOP( "arm11", "arm11 specific commands",
1963 RC_TOP( "memwrite", "Control memory write transfer mode",
1965 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1968 RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
1969 memwrite_error_fatal
)
1972 RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1975 RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1978 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1981 RC_FINAL( "mrc", "Read Coprocessor register",
1984 RC_FINAL( "mcr", "Write Coprocessor register",
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)