src/target/arc.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
   3  *   Frank Dols <frank.dols@synopsys.com>                                  *
   4  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
   5  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
   6  *   Evgeniy Didin <didin@synopsys.com>                                    *
   7  *                                                                         *
   8  *   SPDX-License-Identifier: GPL-2.0-or-later                             *
   9  ***************************************************************************/
  10
  11 #ifndef OPENOCD_TARGET_ARC_H
  12 #define OPENOCD_TARGET_ARC_H
  13
  14 #include <helper/time_support.h>
  15 #include <jtag/jtag.h>
  16
  17 #include "algorithm.h"
  18 #include "breakpoints.h"
  19 #include "jtag/interface.h"
  20 #include "register.h"
  21 #include "target.h"
  22 #include "target_request.h"
  23 #include "target_type.h"
  24 #include "helper/bits.h"
  25
  26 #include "arc_jtag.h"
  27 #include "arc_cmd.h"
  28 #include "arc_mem.h"
  29
  30 #define ARC_COMMON_MAGIC        0xB32EB324  /* just a unique number */
  31
  32 #define AUX_DEBUG_REG                   0x5
  33 #define AUX_PC_REG                      0x6
  34 #define AUX_STATUS32_REG                0xA
  35
  36
  37 #define SET_CORE_FORCE_HALT             BIT(1)
  38 #define SET_CORE_HALT_BIT               BIT(0)      /* STATUS32[0] = H field */
  39 #define SET_CORE_ENABLE_INTERRUPTS      BIT(31)
  40 /* STATUS32[5] or AE bit indicates if the processor is in exception state */
  41 #define SET_CORE_AE_BIT                 BIT(5)
  42 /* Single instruction step bit in Debug register */
  43 #define SET_CORE_SINGLE_INSTR_STEP      BIT(11)
  44
  45 #define AUX_STATUS32_REG_HALT_BIT       BIT(0)
  46 #define AUX_STATUS32_REG_IE_BIT         BIT(31)    /* STATUS32[31] = IE field */
  47
  48 /* Reserved core registers */
  49 #define CORE_R61_NUM                    (61)
  50 #define CORE_R62_NUM                    (62)
  51
  52 #define CORE_REG_MAX_NUMBER             (63)
  53
  54 /* Limit reg_type/reg_type_field  name to 20 symbols */
  55 #define REG_TYPE_MAX_NAME_LENGTH        20
  56
  57 struct arc_reg_bitfield {
  58         struct reg_data_type_bitfield bitfield;
  59         char name[REG_TYPE_MAX_NAME_LENGTH];
  60 };
  61 /* Register data type */
  62 struct arc_reg_data_type {
  63         struct list_head list;
  64         struct reg_data_type data_type;
  65         struct reg_data_type_flags data_type_flags;
  66         struct reg_data_type_struct data_type_struct;
  67         char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
  68         struct arc_reg_bitfield *bitfields;
  69         union {
  70                 struct reg_data_type_struct_field *reg_type_struct_field;
  71                 struct reg_data_type_flags_field *reg_type_flags_field;
  72         };
  73 };
  74
  75
  76
  77 /* Standard GDB register types */
  78 static const struct reg_data_type standard_gdb_types[] = {
  79         { .type = REG_TYPE_INT,         .id = "int" },
  80         { .type = REG_TYPE_INT8,        .id = "int8" },
  81         { .type = REG_TYPE_INT16,       .id = "int16" },
  82         { .type = REG_TYPE_INT32,       .id = "int32" },
  83         { .type = REG_TYPE_INT64,       .id = "int64" },
  84         { .type = REG_TYPE_INT128,      .id = "int128" },
  85         { .type = REG_TYPE_UINT8,       .id = "uint8" },
  86         { .type = REG_TYPE_UINT16,      .id = "uint16" },
  87         { .type = REG_TYPE_UINT32,      .id = "uint32" },
  88         { .type = REG_TYPE_UINT64,      .id = "uint64" },
  89         { .type = REG_TYPE_UINT128,     .id = "uint128" },
  90         { .type = REG_TYPE_CODE_PTR,    .id = "code_ptr" },
  91         { .type = REG_TYPE_DATA_PTR,    .id = "data_ptr" },
  92         { .type = REG_TYPE_FLOAT,       .id = "float" },
  93         { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
  94         { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
  95 };
  96
  97
  98 struct arc_common {
  99         uint32_t common_magic;
 100
 101         struct arc_jtag jtag_info;
 102
 103         struct reg_cache *core_and_aux_cache;
 104         struct reg_cache *bcr_cache;
 105
 106         /* Indicate if cach was built (for deinit function) */
 107         bool core_aux_cache_built;
 108         bool bcr_cache_built;
 109         /* Closely Coupled memory(CCM) regions for performance-critical
 110          * code (optional). */
 111         uint32_t iccm0_start;
 112         uint32_t iccm0_end;
 113         uint32_t iccm1_start;
 114         uint32_t iccm1_end;
 115         uint32_t dccm_start;
 116         uint32_t dccm_end;
 117
 118         int irq_state;
 119
 120         /* Register descriptions */
 121         struct list_head reg_data_types;
 122         struct list_head core_reg_descriptions;
 123         struct list_head aux_reg_descriptions;
 124         struct list_head bcr_reg_descriptions;
 125         unsigned long num_regs;
 126         unsigned long num_core_regs;
 127         unsigned long num_aux_regs;
 128         unsigned long num_bcr_regs;
 129         unsigned long last_general_reg;
 130
 131         /* PC register location in register cache. */
 132         unsigned long pc_index_in_cache;
 133         /* DEBUG register location in register cache. */
 134         unsigned long debug_index_in_cache;
 135 };
 136
 137 /* Borrowed from nds32.h */
 138 #define CHECK_RETVAL(action)                    \
 139         do {                                    \
 140                 int __retval = (action);        \
 141                 if (__retval != ERROR_OK) {     \
 142                         LOG_DEBUG("error while calling \"%s\"", \
 143                                 # action);     \
 144                         return __retval;        \
 145                 }                               \
 146         } while (0)
 147
 148 #define JIM_CHECK_RETVAL(action)                \
 149         do {                                    \
 150                 int __retval = (action);        \
 151                 if (__retval != JIM_OK) {       \
 152                         LOG_DEBUG("error while calling \"%s\"", \
 153                                 # action);     \
 154                         return __retval;        \
 155                 }                               \
 156         } while (0)
 157
 158 static inline struct arc_common *target_to_arc(struct target *target)
 159 {
 160         return target->arch_info;
 161 }
 162
 163 /* ----- Inlined functions ------------------------------------------------- */
 164
 165 /**
 166  * Convert data in host endianness to the middle endian. This is required to
 167  * write 4-byte instructions.
 168  */
 169 static inline void arc_h_u32_to_me(uint8_t *buf, int val)
 170 {
 171         buf[1] = (uint8_t) (val >> 24);
 172         buf[0] = (uint8_t) (val >> 16);
 173         buf[3] = (uint8_t) (val >> 8);
 174         buf[2] = (uint8_t) (val >> 0);
 175 }
 176
 177 /**
 178  * Convert data in middle endian to host endian. This is required to read 32-bit
 179  * instruction from little endian ARCs.
 180  */
 181 static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
 182 {
 183         return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
 184 }
 185
 186
 187 /* ARC Register description */
 188 struct arc_reg_desc {
 189
 190         struct target *target;
 191
 192         /* Register name */
 193         char *name;
 194
 195         /* Actual place of storing reg_value */
 196         uint8_t reg_value[4];
 197
 198         /* Actual place of storing register feature */
 199         struct reg_feature feature;
 200
 201         /* GDB XML feature */
 202         char *gdb_xml_feature;
 203
 204         /* Is this a register in g/G-packet? */
 205         bool is_general;
 206
 207         /* Architectural number: core reg num or AUX reg num */
 208         uint32_t arch_num;
 209
 210         /* Core or AUX register? */
 211         bool is_core;
 212
 213         /* Build configuration register? */
 214         bool is_bcr;
 215
 216         /* Data type */
 217         struct reg_data_type *data_type;
 218
 219         struct list_head list;
 220 };
 221
 222 /* Error codes */
 223 #define ERROR_ARC_REGISTER_NOT_FOUND       (-700)
 224 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
 225 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT   (-702)
 226 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD    (-703)
 227 #define ERROR_ARC_REGTYPE_NOT_FOUND        (-704)
 228
 229 void free_reg_desc(struct arc_reg_desc *r);
 230
 231
 232 void arc_reg_data_type_add(struct target *target,
 233                 struct arc_reg_data_type *data_type);
 234
 235 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 236                 const char * const type_name, const size_t type_name_len);
 237
 238 struct reg *arc_reg_get_by_name(struct reg_cache *first,
 239                                         const char *name, bool search_all);
 240
 241 int arc_reg_get_field(struct target *target, const char *reg_name,
 242                 const char *field_name, uint32_t *value_ptr);
 243
 244 #endif /* OPENOCD_TARGET_ARC_H */