1 /***************************************************************************
2 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
21 * ARC architecture specific details.
23 * ARC has two types of registers:
24 * 1) core registers(e.g. r0,r1..) [is_core = true]
25 * 2) Auxiliary registers [is_core = false]..
27 * Auxiliary registers at the same time can be divided into
28 * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
29 * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
31 * The way of accessing to Core and AUX registers differs on Jtag level.
32 * BCR/non-BCR describes if the register is immutable and that reading
33 * unexisting register is safe RAZ, rather then an error.
34 * Note, core registers cannot be BCR.
36 * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
37 * and BCR aux, in "add-reg" command they are passed to three lists
38 * respectively: core_reg_descriptions, aux_reg_descriptions,
39 * bcr_reg_descriptions.
41 * Due to the specifics of accessing to BCR/non-BCR registers there are two
43 * 1) core_and_aux_cache - includes registers described in
44 * core_reg_descriptions and aux_reg_descriptions lists.
45 * Used during save/restore context step.
46 * 2) bcr_cache - includes registers described bcr_reg_descriptions.
47 * Currently used internally during configure step.
52 void arc_reg_data_type_add(struct target
*target
,
53 struct arc_reg_data_type
*data_type
)
55 LOG_DEBUG("Adding %s reg_data_type", data_type
->data_type
.id
);
56 struct arc_common
*arc
= target_to_arc(target
);
59 list_add_tail(&data_type
->list
, &arc
->reg_data_types
);
63 * Private implementation of register_get_by_name() for ARC that
64 * doesn't skip not [yet] existing registers. Used in many places
65 * for iteration through registers and even for marking required registers as
68 struct reg
*arc_reg_get_by_name(struct reg_cache
*first
,
69 const char *name
, bool search_all
)
72 struct reg_cache
*cache
= first
;
75 for (i
= 0; i
< cache
->num_regs
; i
++) {
76 if (!strcmp(cache
->reg_list
[i
].name
, name
))
77 return &(cache
->reg_list
[i
]);
90 * Reset internal states of caches. Must be called when entering debugging.
92 * @param target Target for which to reset caches states.
94 int arc_reset_caches_states(struct target
*target
)
96 struct arc_common
*arc
= target_to_arc(target
);
98 LOG_DEBUG("Resetting internal variables of caches states");
100 /* Reset caches states. */
101 arc
->dcache_flushed
= false;
102 arc
->l2cache_flushed
= false;
103 arc
->icache_invalidated
= false;
104 arc
->dcache_invalidated
= false;
105 arc
->l2cache_invalidated
= false;
110 /* Initialize arc_common structure, which passes to openocd target instance */
111 static int arc_init_arch_info(struct target
*target
, struct arc_common
*arc
,
112 struct jtag_tap
*tap
)
114 arc
->common_magic
= ARC_COMMON_MAGIC
;
115 target
->arch_info
= arc
;
117 arc
->jtag_info
.tap
= tap
;
119 /* The only allowed ir_length is 4 for ARC jtag. */
120 if (tap
->ir_length
!= 4) {
121 LOG_ERROR("ARC jtag instruction length should be equal to 4");
125 /* On most ARC targets there is a dcache, so we enable its flushing
126 * by default. If there no dcache, there will be no error, just a slight
127 * performance penalty from unnecessary JTAG operations. */
128 arc
->has_dcache
= true;
129 arc
->has_icache
= true;
130 /* L2$ is not available in a target by default. */
131 arc
->has_l2cache
= false;
132 arc_reset_caches_states(target
);
134 /* Add standard GDB data types */
135 INIT_LIST_HEAD(&arc
->reg_data_types
);
136 struct arc_reg_data_type
*std_types
= calloc(ARRAY_SIZE(standard_gdb_types
),
140 LOG_ERROR("Unable to allocate memory");
144 for (unsigned int i
= 0; i
< ARRAY_SIZE(standard_gdb_types
); i
++) {
145 std_types
[i
].data_type
.type
= standard_gdb_types
[i
].type
;
146 std_types
[i
].data_type
.id
= standard_gdb_types
[i
].id
;
147 arc_reg_data_type_add(target
, &(std_types
[i
]));
150 /* Fields related to target descriptions */
151 INIT_LIST_HEAD(&arc
->core_reg_descriptions
);
152 INIT_LIST_HEAD(&arc
->aux_reg_descriptions
);
153 INIT_LIST_HEAD(&arc
->bcr_reg_descriptions
);
155 arc
->num_core_regs
= 0;
156 arc
->num_aux_regs
= 0;
157 arc
->num_bcr_regs
= 0;
158 arc
->last_general_reg
= ULONG_MAX
;
159 arc
->pc_index_in_cache
= ULONG_MAX
;
160 arc
->debug_index_in_cache
= ULONG_MAX
;
165 int arc_reg_add(struct target
*target
, struct arc_reg_desc
*arc_reg
,
166 const char * const type_name
, const size_t type_name_len
)
171 struct arc_common
*arc
= target_to_arc(target
);
174 /* Find register type */
176 struct arc_reg_data_type
*type
;
177 list_for_each_entry(type
, &arc
->reg_data_types
, list
)
178 if (!strncmp(type
->data_type
.id
, type_name
, type_name_len
)) {
179 arc_reg
->data_type
= &(type
->data_type
);
183 if (!arc_reg
->data_type
)
184 return ERROR_ARC_REGTYPE_NOT_FOUND
;
187 if (arc_reg
->is_core
) {
188 list_add_tail(&arc_reg
->list
, &arc
->core_reg_descriptions
);
189 arc
->num_core_regs
+= 1;
190 } else if (arc_reg
->is_bcr
) {
191 list_add_tail(&arc_reg
->list
, &arc
->bcr_reg_descriptions
);
192 arc
->num_bcr_regs
+= 1;
194 list_add_tail(&arc_reg
->list
, &arc
->aux_reg_descriptions
);
195 arc
->num_aux_regs
+= 1;
200 "added register {name=%s, num=0x%" PRIx32
", type=%s%s%s%s}",
201 arc_reg
->name
, arc_reg
->arch_num
, arc_reg
->data_type
->id
,
202 arc_reg
->is_core
? ", core" : "", arc_reg
->is_bcr
? ", bcr" : "",
203 arc_reg
->is_general
? ", general" : ""
209 /* Reading core or aux register */
210 static int arc_get_register(struct reg
*reg
)
214 struct arc_reg_desc
*desc
= reg
->arch_info
;
215 struct target
*target
= desc
->target
;
216 struct arc_common
*arc
= target_to_arc(target
);
221 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
222 reg
->number
, desc
->name
, target_buffer_get_u32(target
, reg
->value
));
227 /* Accessing to R61/R62 registers causes Jtag hang */
228 if (desc
->arch_num
== CORE_R61_NUM
|| desc
->arch_num
== CORE_R62_NUM
) {
229 LOG_ERROR("It is forbidden to read core registers 61 and 62.");
232 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc
->jtag_info
, desc
->arch_num
,
235 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, desc
->arch_num
,
239 target_buffer_set_u32(target
, reg
->value
, value
);
241 /* If target is unhalted all register reads should be uncached. */
242 if (target
->state
== TARGET_HALTED
)
249 LOG_DEBUG("Get register gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
250 reg
->number
, desc
->name
, value
);
256 /* Writing core or aux register */
257 static int arc_set_register(struct reg
*reg
, uint8_t *buf
)
259 struct arc_reg_desc
*desc
= reg
->arch_info
;
260 struct target
*target
= desc
->target
;
261 uint32_t value
= target_buffer_get_u32(target
, buf
);
262 /* Unlike "get" function "set" is supported only if target
263 * is in halt mode. Async writes are not supported yet. */
264 if (target
->state
!= TARGET_HALTED
)
265 return ERROR_TARGET_NOT_HALTED
;
267 /* Accessing to R61/R62 registers causes Jtag hang */
268 if (desc
->is_core
&& (desc
->arch_num
== CORE_R61_NUM
||
269 desc
->arch_num
== CORE_R62_NUM
)) {
270 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
273 target_buffer_set_u32(target
, reg
->value
, value
);
275 LOG_DEBUG("Set register gdb_num=%" PRIu32
", name=%s, value=0x%08" PRIx32
,
276 reg
->number
, desc
->name
, value
);
284 const struct reg_arch_type arc_reg_type
= {
285 .get
= arc_get_register
,
286 .set
= arc_set_register
,
289 /* GDB register groups. For now we support only general and "empty" */
290 static const char * const reg_group_general
= "general";
291 static const char * const reg_group_other
= "";
293 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
294 static int arc_init_reg(struct target
*target
, struct reg
*reg
,
295 struct arc_reg_desc
*reg_desc
, unsigned long number
)
301 struct arc_common
*arc
= target_to_arc(target
);
303 /* Initialize struct reg */
304 reg
->name
= reg_desc
->name
;
305 reg
->size
= 32; /* All register in ARC are 32-bit */
306 reg
->value
= ®_desc
->reg_value
;
307 reg
->type
= &arc_reg_type
;
308 reg
->arch_info
= reg_desc
;
309 reg
->caller_save
= true; /* @todo should be configurable. */
310 reg
->reg_data_type
= reg_desc
->data_type
;
311 reg
->feature
= ®_desc
->feature
;
313 reg
->feature
->name
= reg_desc
->gdb_xml_feature
;
315 /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
316 * value of a register GDB will use it as a number of register in
317 * P-packet. OpenOCD gdbserver will then use number of register in
318 * P-packet as an array index in the reg_list returned by
319 * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
320 * correctly it would be required to either sort registers in
321 * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
322 * according to how registers will be sorted in
323 * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
324 reg
->number
= number
;
326 if (reg_desc
->is_general
) {
327 arc
->last_general_reg
= reg
->number
;
328 reg
->group
= reg_group_general
;
330 reg
->group
= reg_group_other
;
336 /* Building aux/core reg_cache */
337 static int arc_build_reg_cache(struct target
*target
)
340 struct arc_reg_desc
*reg_desc
;
341 /* get pointers to arch-specific information */
342 struct arc_common
*arc
= target_to_arc(target
);
343 const unsigned long num_regs
= arc
->num_core_regs
+ arc
->num_aux_regs
;
344 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
345 struct reg_cache
*cache
= calloc(1, sizeof(*cache
));
346 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
348 if (!cache
|| !reg_list
) {
349 LOG_ERROR("Not enough memory");
353 /* Build the process context cache */
354 cache
->name
= "arc registers";
356 cache
->reg_list
= reg_list
;
357 cache
->num_regs
= num_regs
;
358 arc
->core_and_aux_cache
= cache
;
361 if (list_empty(&arc
->core_reg_descriptions
)) {
362 LOG_ERROR("No core registers were defined");
366 list_for_each_entry(reg_desc
, &arc
->core_reg_descriptions
, list
) {
367 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
369 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
370 reg_list
[i
].name
, reg_list
[i
].group
,
371 reg_list
[i
].feature
->name
);
376 if (list_empty(&arc
->aux_reg_descriptions
)) {
377 LOG_ERROR("No aux registers were defined");
381 list_for_each_entry(reg_desc
, &arc
->aux_reg_descriptions
, list
) {
382 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
384 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
385 reg_list
[i
].name
, reg_list
[i
].group
,
386 reg_list
[i
].feature
->name
);
388 /* PC and DEBUG are essential so we search for them. */
389 if (!strcmp("pc", reg_desc
->name
)) {
390 if (arc
->pc_index_in_cache
!= ULONG_MAX
) {
391 LOG_ERROR("Double definition of PC in configuration");
394 arc
->pc_index_in_cache
= i
;
395 } else if (!strcmp("debug", reg_desc
->name
)) {
396 if (arc
->debug_index_in_cache
!= ULONG_MAX
) {
397 LOG_ERROR("Double definition of DEBUG in configuration");
400 arc
->debug_index_in_cache
= i
;
405 if (arc
->pc_index_in_cache
== ULONG_MAX
406 || arc
->debug_index_in_cache
== ULONG_MAX
) {
407 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
411 assert(i
== (arc
->num_core_regs
+ arc
->num_aux_regs
));
413 arc
->core_aux_cache_built
= true;
424 /* Build bcr reg_cache.
425 * This function must be called only after arc_build_reg_cache */
426 static int arc_build_bcr_reg_cache(struct target
*target
)
428 /* get pointers to arch-specific information */
429 struct arc_common
*arc
= target_to_arc(target
);
430 const unsigned long num_regs
= arc
->num_bcr_regs
;
431 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
432 struct reg_cache
*cache
= malloc(sizeof(*cache
));
433 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
435 struct arc_reg_desc
*reg_desc
;
437 unsigned long gdb_regnum
= arc
->core_and_aux_cache
->num_regs
;
439 if (!cache
|| !reg_list
) {
440 LOG_ERROR("Unable to allocate memory");
444 /* Build the process context cache */
445 cache
->name
= "arc.bcr";
447 cache
->reg_list
= reg_list
;
448 cache
->num_regs
= num_regs
;
449 arc
->bcr_cache
= cache
;
452 if (list_empty(&arc
->bcr_reg_descriptions
)) {
453 LOG_ERROR("No BCR registers are defined");
457 list_for_each_entry(reg_desc
, &arc
->bcr_reg_descriptions
, list
) {
458 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, gdb_regnum
));
459 /* BCRs always semantically, they are just read-as-zero, if there is
460 * not real register. */
461 reg_list
[i
].exist
= true;
463 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
464 reg_list
[i
].name
, reg_list
[i
].group
,
465 reg_list
[i
].feature
->name
);
470 assert(i
== arc
->num_bcr_regs
);
472 arc
->bcr_cache_built
= true;
484 static int arc_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
485 int *reg_list_size
, enum target_register_class reg_class
)
487 assert(target
->reg_cache
);
488 struct arc_common
*arc
= target_to_arc(target
);
490 /* get pointers to arch-specific information storage */
491 *reg_list_size
= arc
->num_regs
;
492 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
495 LOG_ERROR("Unable to allocate memory");
499 /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
500 * XML tdesc it filters out !exist registers, however when creating a
501 * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
502 * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
503 * out !exist register for "general", but not for "all". Attempts to filter out
504 * !exist for "all" as well will cause a failed check in OpenOCD GDB
506 if (reg_class
== REG_CLASS_ALL
) {
508 struct reg_cache
*reg_cache
= target
->reg_cache
;
510 for (unsigned j
= 0; j
< reg_cache
->num_regs
; j
++, i
++)
511 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
512 reg_cache
= reg_cache
->next
;
514 assert(i
== arc
->num_regs
);
515 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size
);
518 unsigned long gdb_reg_number
= 0;
519 struct reg_cache
*reg_cache
= target
->reg_cache
;
522 j
< reg_cache
->num_regs
&& gdb_reg_number
<= arc
->last_general_reg
;
524 if (reg_cache
->reg_list
[j
].exist
) {
525 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
530 reg_cache
= reg_cache
->next
;
533 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size
);
539 /* Reading field of struct_type register */
540 int arc_reg_get_field(struct target
*target
, const char *reg_name
,
541 const char *field_name
, uint32_t *value_ptr
)
543 struct reg_data_type_struct_field
*field
;
545 LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name
, field_name
);
548 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
551 LOG_ERROR("Requested register `%s' doesn't exist.", reg_name
);
552 return ERROR_ARC_REGISTER_NOT_FOUND
;
555 if (reg
->reg_data_type
->type
!= REG_TYPE_ARCH_DEFINED
556 || reg
->reg_data_type
->type_class
!= REG_TYPE_CLASS_STRUCT
)
557 return ERROR_ARC_REGISTER_IS_NOT_STRUCT
;
559 /* Get field in a register */
560 struct reg_data_type_struct
*reg_struct
=
561 reg
->reg_data_type
->reg_type_struct
;
562 for (field
= reg_struct
->fields
;
564 field
= field
->next
) {
565 if (!strcmp(field
->name
, field_name
))
570 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND
;
572 if (!field
->use_bitfields
)
573 return ERROR_ARC_FIELD_IS_NOT_BITFIELD
;
576 CHECK_RETVAL(reg
->type
->get(reg
));
578 /* First do endianness-safe read of register value
579 * then convert it to binary buffer for further
580 * field extraction */
582 *value_ptr
= buf_get_u32(reg
->value
, field
->bitfield
->start
,
583 field
->bitfield
->end
- field
->bitfield
->start
+ 1);
588 static int arc_get_register_value(struct target
*target
, const char *reg_name
,
591 LOG_DEBUG("reg_name=%s", reg_name
);
593 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
596 return ERROR_ARC_REGISTER_NOT_FOUND
;
599 CHECK_RETVAL(reg
->type
->get(reg
));
601 *value_ptr
= target_buffer_get_u32(target
, reg
->value
);
606 static int arc_set_register_value(struct target
*target
, const char *reg_name
,
609 LOG_DEBUG("reg_name=%s value=0x%08" PRIx32
, reg_name
, value
);
611 if (!(target
&& reg_name
)) {
612 LOG_ERROR("Arguments cannot be NULL.");
616 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
619 return ERROR_ARC_REGISTER_NOT_FOUND
;
621 uint8_t value_buf
[4];
622 buf_set_u32(value_buf
, 0, 32, value
);
623 CHECK_RETVAL(reg
->type
->set(reg
, value_buf
));
628 /* Configure DCCM's */
629 static int arc_configure_dccm(struct target
*target
)
631 struct arc_common
*arc
= target_to_arc(target
);
633 uint32_t dccm_build_version
, dccm_build_size0
, dccm_build_size1
;
634 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "version",
635 &dccm_build_version
));
636 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size0",
638 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size1",
640 /* There is no yet support of configurable number of cycles,
641 * So there is no difference between v3 and v4 */
642 if ((dccm_build_version
== 3 || dccm_build_version
== 4) && dccm_build_size0
> 0) {
643 CHECK_RETVAL(arc_get_register_value(target
, "aux_dccm", &(arc
->dccm_start
)));
644 uint32_t dccm_size
= 0x100;
645 dccm_size
<<= dccm_build_size0
;
646 if (dccm_build_size0
== 0xF)
647 dccm_size
<<= dccm_build_size1
;
648 arc
->dccm_end
= arc
->dccm_start
+ dccm_size
;
649 LOG_DEBUG("DCCM detected start=0x%" PRIx32
" end=0x%" PRIx32
,
650 arc
->dccm_start
, arc
->dccm_end
);
657 /* Configure ICCM's */
659 static int arc_configure_iccm(struct target
*target
)
661 struct arc_common
*arc
= target_to_arc(target
);
664 uint32_t iccm_build_version
, iccm_build_size00
, iccm_build_size01
;
665 uint32_t aux_iccm
= 0;
666 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "version",
667 &iccm_build_version
));
668 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size0",
669 &iccm_build_size00
));
670 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size1",
671 &iccm_build_size01
));
672 if (iccm_build_version
== 4 && iccm_build_size00
> 0) {
673 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
674 uint32_t iccm0_size
= 0x100;
675 iccm0_size
<<= iccm_build_size00
;
676 if (iccm_build_size00
== 0xF)
677 iccm0_size
<<= iccm_build_size01
;
678 /* iccm0 start is located in highest 4 bits of aux_iccm */
679 arc
->iccm0_start
= aux_iccm
& 0xF0000000;
680 arc
->iccm0_end
= arc
->iccm0_start
+ iccm0_size
;
681 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
682 arc
->iccm0_start
, arc
->iccm0_end
);
686 uint32_t iccm_build_size10
, iccm_build_size11
;
687 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size0",
688 &iccm_build_size10
));
689 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size1",
690 &iccm_build_size11
));
691 if (iccm_build_version
== 4 && iccm_build_size10
> 0) {
692 /* Use value read for ICCM0 */
694 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
695 uint32_t iccm1_size
= 0x100;
696 iccm1_size
<<= iccm_build_size10
;
697 if (iccm_build_size10
== 0xF)
698 iccm1_size
<<= iccm_build_size11
;
699 arc
->iccm1_start
= aux_iccm
& 0x0F000000;
700 arc
->iccm1_end
= arc
->iccm1_start
+ iccm1_size
;
701 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
702 arc
->iccm1_start
, arc
->iccm1_end
);
707 /* Configure some core features, depending on BCRs. */
708 static int arc_configure(struct target
*target
)
710 LOG_DEBUG("Configuring ARC ICCM and DCCM");
712 /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
713 if (arc_reg_get_by_name(target
->reg_cache
, "dccm_build", true) &&
714 arc_reg_get_by_name(target
->reg_cache
, "aux_dccm", true))
715 CHECK_RETVAL(arc_configure_dccm(target
));
717 /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
718 if (arc_reg_get_by_name(target
->reg_cache
, "iccm_build", true) &&
719 arc_reg_get_by_name(target
->reg_cache
, "aux_iccm", true))
720 CHECK_RETVAL(arc_configure_iccm(target
));
725 /* arc_examine is function, which is used for all arc targets*/
726 static int arc_examine(struct target
*target
)
729 struct arc_common
*arc
= target_to_arc(target
);
731 CHECK_RETVAL(arc_jtag_startup(&arc
->jtag_info
));
733 if (!target_was_examined(target
)) {
734 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
735 if (status
& ARC_JTAG_STAT_RU
)
736 target
->state
= TARGET_RUNNING
;
738 target
->state
= TARGET_HALTED
;
740 /* Read BCRs and configure optional registers. */
741 CHECK_RETVAL(arc_configure(target
));
743 target_set_examined(target
);
749 static int arc_halt(struct target
*target
)
751 uint32_t value
, irq_state
;
752 struct arc_common
*arc
= target_to_arc(target
);
754 LOG_DEBUG("target->state: %s", target_state_name(target
));
756 if (target
->state
== TARGET_HALTED
) {
757 LOG_DEBUG("target was already halted");
761 if (target
->state
== TARGET_UNKNOWN
)
762 LOG_WARNING("target was in unknown state when halt was requested");
764 if (target
->state
== TARGET_RESET
) {
765 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
766 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
767 return ERROR_TARGET_FAILURE
;
769 target
->debug_reason
= DBG_REASON_DBGRQ
;
773 /* Break (stop) processor.
774 * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
775 * We do not use here arc_get/set_core_reg functions here because they imply
776 * that the processor is already halted. */
777 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, &value
));
778 value
|= SET_CORE_FORCE_HALT
; /* set the HALT bit */
779 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, value
));
782 /* Save current IRQ state */
783 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &irq_state
));
785 if (irq_state
& AUX_STATUS32_REG_IE_BIT
)
790 /* update state and notify gdb*/
791 target
->state
= TARGET_HALTED
;
792 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
794 /* some more debug information */
795 if (debug_level
>= LOG_LVL_DEBUG
) {
796 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32
, value
);
797 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
798 LOG_DEBUG("core STATUS32: 0x%08" PRIx32
, value
);
805 * Read registers that are used in GDB g-packet. We don't read them one-by-one,
806 * but do that in one batch operation to improve speed. Calls to JTAG layer are
807 * expensive so it is better to make one big call that reads all necessary
808 * registers, instead of many calls, one for one register.
810 static int arc_save_context(struct target
*target
)
812 int retval
= ERROR_OK
;
814 struct arc_common
*arc
= target_to_arc(target
);
815 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
817 LOG_DEBUG("Saving aux and core registers values");
820 /* It is assumed that there is at least one AUX register in the list, for
822 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
823 /* last_general_reg is inclusive number. To get count of registers it is
824 * required to do +1. */
825 const uint32_t regs_to_scan
=
826 MIN(arc
->last_general_reg
+ 1, arc
->num_regs
);
827 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
828 uint32_t *core_values
= malloc(core_regs_size
);
829 uint32_t *aux_values
= malloc(aux_regs_size
);
830 uint32_t *core_addrs
= malloc(core_regs_size
);
831 uint32_t *aux_addrs
= malloc(aux_regs_size
);
832 unsigned int core_cnt
= 0;
833 unsigned int aux_cnt
= 0;
835 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
836 LOG_ERROR("Unable to allocate memory");
841 memset(core_values
, 0xff, core_regs_size
);
842 memset(core_addrs
, 0xff, core_regs_size
);
843 memset(aux_values
, 0xff, aux_regs_size
);
844 memset(aux_addrs
, 0xff, aux_regs_size
);
846 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
847 struct reg
*reg
= &(reg_list
[i
]);
848 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
849 if (!reg
->valid
&& reg
->exist
) {
850 core_addrs
[core_cnt
] = arc_reg
->arch_num
;
855 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
856 struct reg
*reg
= &(reg_list
[i
]);
857 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
858 if (!reg
->valid
&& reg
->exist
) {
859 aux_addrs
[aux_cnt
] = arc_reg
->arch_num
;
864 /* Read data from target. */
866 retval
= arc_jtag_read_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
867 if (ERROR_OK
!= retval
) {
868 LOG_ERROR("Attempt to read core registers failed.");
874 retval
= arc_jtag_read_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
875 if (ERROR_OK
!= retval
) {
876 LOG_ERROR("Attempt to read aux registers failed.");
882 /* Parse core regs */
884 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
885 struct reg
*reg
= &(reg_list
[i
]);
886 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
887 if (!reg
->valid
&& reg
->exist
) {
888 target_buffer_set_u32(target
, reg
->value
, core_values
[core_cnt
]);
892 LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32
,
893 i
, arc_reg
->name
, core_values
[core_cnt
]);
899 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
900 struct reg
*reg
= &(reg_list
[i
]);
901 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
902 if (!reg
->valid
&& reg
->exist
) {
903 target_buffer_set_u32(target
, reg
->value
, aux_values
[aux_cnt
]);
907 LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32
,
908 i
, arc_reg
->name
, aux_values
[aux_cnt
]);
922 * Finds an actionpoint that triggered last actionpoint event, as specified by
925 * @param actionpoint Pointer to be set to last active actionpoint. Pointer
926 * will be set to NULL if DEBUG.AH is 0.
928 static int get_current_actionpoint(struct target
*target
,
929 struct arc_actionpoint
**actionpoint
)
931 assert(target
!= NULL
);
932 assert(actionpoint
!= NULL
);
935 /* Check if actionpoint caused halt */
936 CHECK_RETVAL(arc_reg_get_field(target
, "debug", "ah",
940 struct arc_common
*arc
= target_to_arc(target
);
943 CHECK_RETVAL(arc_reg_get_field(target
, "debug",
946 for (ap
= 0; debug_asr
> 1; debug_asr
>>= 1)
949 assert(ap
< arc
->actionpoints_num
);
951 *actionpoint
= &(arc
->actionpoints_list
[ap
]);
959 static int arc_examine_debug_reason(struct target
*target
)
963 /* Only check for reason if don't know it already. */
964 /* BTW After singlestep at this point core is not marked as halted, so
965 * reading from memory to get current instruction wouldn't work anyway. */
966 if (target
->debug_reason
== DBG_REASON_DBGRQ
||
967 target
->debug_reason
== DBG_REASON_SINGLESTEP
) {
971 CHECK_RETVAL(arc_reg_get_field(target
, "debug", "bh",
975 /* DEBUG.BH is set if core halted due to BRK instruction. */
976 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
978 struct arc_actionpoint
*actionpoint
= NULL
;
979 CHECK_RETVAL(get_current_actionpoint(target
, &actionpoint
));
981 if (actionpoint
!= NULL
) {
982 if (!actionpoint
->used
)
983 LOG_WARNING("Target halted by an unused actionpoint.");
985 if (actionpoint
->type
== ARC_AP_BREAKPOINT
)
986 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
987 else if (actionpoint
->type
== ARC_AP_WATCHPOINT
)
988 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
990 LOG_WARNING("Unknown type of actionpoint.");
997 static int arc_debug_entry(struct target
*target
)
999 CHECK_RETVAL(arc_save_context(target
));
1001 /* TODO: reset internal indicators of caches states, otherwise D$/I$
1002 * will not be flushed/invalidated when required. */
1003 CHECK_RETVAL(arc_reset_caches_states(target
));
1004 CHECK_RETVAL(arc_examine_debug_reason(target
));
1009 static int arc_poll(struct target
*target
)
1011 uint32_t status
, value
;
1012 struct arc_common
*arc
= target_to_arc(target
);
1014 /* gdb calls continuously through this arc_poll() function */
1015 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
1017 /* check for processor halted */
1018 if (status
& ARC_JTAG_STAT_RU
) {
1019 if (target
->state
!= TARGET_RUNNING
) {
1020 LOG_WARNING("target is still running!");
1021 target
->state
= TARGET_RUNNING
;
1025 /* In some cases JTAG status register indicates that
1026 * processor is in halt mode, but processor is still running.
1027 * We check halt bit of AUX STATUS32 register for setting correct state. */
1028 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
)) {
1029 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
1030 if (value
& AUX_STATUS32_REG_HALT_BIT
) {
1031 LOG_DEBUG("ARC core in halt or reset state.");
1032 /* Save context if target was not in reset state */
1033 if (target
->state
== TARGET_RUNNING
)
1034 CHECK_RETVAL(arc_debug_entry(target
));
1035 target
->state
= TARGET_HALTED
;
1036 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1038 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
1039 "target is still running");
1042 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
1044 target
->state
= TARGET_HALTED
;
1045 LOG_DEBUG("ARC core is in debug running mode");
1047 CHECK_RETVAL(arc_debug_entry(target
));
1049 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
));
1055 static int arc_assert_reset(struct target
*target
)
1057 struct arc_common
*arc
= target_to_arc(target
);
1058 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1059 bool srst_asserted
= false;
1061 LOG_DEBUG("target->state: %s", target_state_name(target
));
1063 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1064 /* allow scripts to override the reset event */
1066 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1067 register_cache_invalidate(arc
->core_and_aux_cache
);
1068 /* An ARC target might be in halt state after reset, so
1069 * if script requested processor to resume, then it must
1070 * be manually started to ensure that this request
1072 if (target
->state
== TARGET_HALTED
&& !target
->reset_halt
) {
1073 /* Resume the target and continue from the current
1074 * PC register value. */
1075 LOG_DEBUG("Starting CPU execution after reset");
1076 CHECK_RETVAL(target_resume(target
, 1, 0, 0, 0));
1078 target
->state
= TARGET_RESET
;
1083 /* some cores support connecting while srst is asserted
1084 * use that mode if it has been configured */
1085 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
1086 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1087 jtag_add_reset(0, 1);
1088 srst_asserted
= true;
1091 if (jtag_reset_config
& RESET_HAS_SRST
) {
1092 /* should issue a srst only, but we may have to assert trst as well */
1093 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1094 jtag_add_reset(1, 1);
1095 else if (!srst_asserted
)
1096 jtag_add_reset(0, 1);
1099 target
->state
= TARGET_RESET
;
1100 jtag_add_sleep(50000);
1102 register_cache_invalidate(arc
->core_and_aux_cache
);
1104 if (target
->reset_halt
)
1105 CHECK_RETVAL(target_halt(target
));
1110 static int arc_deassert_reset(struct target
*target
)
1112 LOG_DEBUG("target->state: %s", target_state_name(target
));
1114 /* deassert reset lines */
1115 jtag_add_reset(0, 0);
1120 static int arc_arch_state(struct target
*target
)
1124 if (debug_level
< LOG_LVL_DEBUG
)
1127 CHECK_RETVAL(arc_get_register_value(target
, "pc", &pc_value
));
1129 LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32
,
1130 target_state_name(target
),
1137 * See arc_save_context() for reason why we want to dump all regs at once.
1138 * This however means that if there are dependencies between registers they
1139 * will not be observable until target will be resumed.
1141 static int arc_restore_context(struct target
*target
)
1143 int retval
= ERROR_OK
;
1145 struct arc_common
*arc
= target_to_arc(target
);
1146 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
1148 LOG_DEBUG("Restoring registers values");
1151 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
1152 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
1153 uint32_t *core_values
= malloc(core_regs_size
);
1154 uint32_t *aux_values
= malloc(aux_regs_size
);
1155 uint32_t *core_addrs
= malloc(core_regs_size
);
1156 uint32_t *aux_addrs
= malloc(aux_regs_size
);
1157 unsigned int core_cnt
= 0;
1158 unsigned int aux_cnt
= 0;
1160 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
1161 LOG_ERROR("Unable to allocate memory");
1162 retval
= ERROR_FAIL
;
1166 memset(core_values
, 0xff, core_regs_size
);
1167 memset(core_addrs
, 0xff, core_regs_size
);
1168 memset(aux_values
, 0xff, aux_regs_size
);
1169 memset(aux_addrs
, 0xff, aux_regs_size
);
1171 for (i
= 0; i
< arc
->num_core_regs
; i
++) {
1172 struct reg
*reg
= &(reg_list
[i
]);
1173 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1174 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1175 LOG_DEBUG("Will write regnum=%u", i
);
1176 core_addrs
[core_cnt
] = arc_reg
->arch_num
;
1177 core_values
[core_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1182 for (i
= 0; i
< arc
->num_aux_regs
; i
++) {
1183 struct reg
*reg
= &(reg_list
[arc
->num_core_regs
+ i
]);
1184 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1185 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1186 LOG_DEBUG("Will write regnum=%lu", arc
->num_core_regs
+ i
);
1187 aux_addrs
[aux_cnt
] = arc_reg
->arch_num
;
1188 aux_values
[aux_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1193 /* Write data to target.
1194 * Check before write, if aux and core count is greater than 0. */
1196 retval
= arc_jtag_write_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
1197 if (ERROR_OK
!= retval
) {
1198 LOG_ERROR("Attempt to write to core registers failed.");
1199 retval
= ERROR_FAIL
;
1205 retval
= arc_jtag_write_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
1206 if (ERROR_OK
!= retval
) {
1207 LOG_ERROR("Attempt to write to aux registers failed.");
1208 retval
= ERROR_FAIL
;
1222 static int arc_enable_interrupts(struct target
*target
, int enable
)
1226 struct arc_common
*arc
= target_to_arc(target
);
1228 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1231 /* enable interrupts */
1232 value
|= SET_CORE_ENABLE_INTERRUPTS
;
1233 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1234 LOG_DEBUG("interrupts enabled");
1236 /* disable interrupts */
1237 value
&= ~SET_CORE_ENABLE_INTERRUPTS
;
1238 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1239 LOG_DEBUG("interrupts disabled");
1245 static int arc_resume(struct target
*target
, int current
, target_addr_t address
,
1246 int handle_breakpoints
, int debug_execution
)
1248 struct arc_common
*arc
= target_to_arc(target
);
1249 uint32_t resume_pc
= 0;
1251 struct reg
*pc
= &arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
];
1253 LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR
", handle_breakpoints(not supported yet):%i,"
1254 " debug_execution:%i", current
, address
, handle_breakpoints
, debug_execution
);
1256 /* We need to reset ARC cache variables so caches
1257 * would be invalidated and actual data
1258 * would be fetched from memory. */
1259 CHECK_RETVAL(arc_reset_caches_states(target
));
1261 if (target
->state
!= TARGET_HALTED
) {
1262 LOG_WARNING("target not halted");
1263 return ERROR_TARGET_NOT_HALTED
;
1266 /* current = 1: continue on current PC, otherwise continue at <address> */
1268 target_buffer_set_u32(target
, pc
->value
, address
);
1271 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR
, address
);
1275 resume_pc
= address
;
1277 resume_pc
= target_buffer_get_u32(target
, pc
->value
);
1279 CHECK_RETVAL(arc_restore_context(target
));
1281 LOG_DEBUG("Target resumes from PC=0x%" PRIx32
", pc.dirty=%i, pc.valid=%i",
1282 resume_pc
, pc
->dirty
, pc
->valid
);
1284 /* check if GDB tells to set our PC where to continue from */
1285 if ((pc
->valid
== 1) && (resume_pc
== target_buffer_get_u32(target
, pc
->value
))) {
1286 value
= target_buffer_get_u32(target
, pc
->value
);
1287 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32
, value
);
1288 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_PC_REG
, value
));
1291 /* Restore IRQ state if not in debug_execution*/
1292 if (!debug_execution
)
1293 CHECK_RETVAL(arc_enable_interrupts(target
, arc
->irq_state
));
1295 CHECK_RETVAL(arc_enable_interrupts(target
, !debug_execution
));
1297 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1299 /* ready to get us going again */
1300 target
->state
= TARGET_RUNNING
;
1301 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1302 value
&= ~SET_CORE_HALT_BIT
; /* clear the HALT bit */
1303 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1304 LOG_DEBUG("Core started to run");
1306 /* registers are now invalid */
1307 register_cache_invalidate(arc
->core_and_aux_cache
);
1309 if (!debug_execution
) {
1310 target
->state
= TARGET_RUNNING
;
1311 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1312 LOG_DEBUG("target resumed at 0x%08" PRIx32
, resume_pc
);
1314 target
->state
= TARGET_DEBUG_RUNNING
;
1315 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
));
1316 LOG_DEBUG("target debug resumed at 0x%08" PRIx32
, resume_pc
);
1322 static int arc_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
1324 CHECK_RETVAL(arc_build_reg_cache(target
));
1325 CHECK_RETVAL(arc_build_bcr_reg_cache(target
));
1326 target
->debug_reason
= DBG_REASON_DBGRQ
;
1330 static void arc_free_reg_cache(struct reg_cache
*cache
)
1332 free(cache
->reg_list
);
1336 static void arc_deinit_target(struct target
*target
)
1338 struct arc_common
*arc
= target_to_arc(target
);
1340 LOG_DEBUG("deinitialization of target");
1341 if (arc
->core_aux_cache_built
)
1342 arc_free_reg_cache(arc
->core_and_aux_cache
);
1343 if (arc
->bcr_cache_built
)
1344 arc_free_reg_cache(arc
->bcr_cache
);
1346 struct arc_reg_data_type
*type
, *n
;
1347 struct arc_reg_desc
*desc
, *k
;
1349 /* Free arc-specific reg_data_types allocations*/
1350 list_for_each_entry_safe_reverse(type
, n
, &arc
->reg_data_types
, list
) {
1351 if (type
->data_type
.type_class
== REG_TYPE_CLASS_STRUCT
) {
1352 free(type
->reg_type_struct_field
);
1353 free(type
->bitfields
);
1355 } else if (type
->data_type
.type_class
== REG_TYPE_CLASS_FLAGS
) {
1356 free(type
->reg_type_flags_field
);
1357 free(type
->bitfields
);
1362 /* Free standard_gdb_types reg_data_types allocations */
1363 type
= list_first_entry(&arc
->reg_data_types
, struct arc_reg_data_type
, list
);
1366 list_for_each_entry_safe(desc
, k
, &arc
->aux_reg_descriptions
, list
)
1367 free_reg_desc(desc
);
1369 list_for_each_entry_safe(desc
, k
, &arc
->core_reg_descriptions
, list
)
1370 free_reg_desc(desc
);
1372 list_for_each_entry_safe(desc
, k
, &arc
->bcr_reg_descriptions
, list
)
1373 free_reg_desc(desc
);
1375 free(arc
->actionpoints_list
);
1380 static int arc_target_create(struct target
*target
, Jim_Interp
*interp
)
1382 struct arc_common
*arc
= calloc(1, sizeof(*arc
));
1385 LOG_ERROR("Unable to allocate memory");
1389 LOG_DEBUG("Entering");
1390 CHECK_RETVAL(arc_init_arch_info(target
, arc
, target
->tap
));
1396 * Write 4-byte instruction to memory. This is like target_write_u32, however
1397 * in case of little endian ARC instructions are in middle endian format, not
1398 * little endian, so different type of conversion should be done.
1399 * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
1401 int arc_write_instruction_u32(struct target
*target
, uint32_t address
,
1404 uint8_t value_buf
[4];
1405 if (!target_was_examined(target
)) {
1406 LOG_ERROR("Target not examined yet");
1410 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1413 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1414 arc_h_u32_to_me(value_buf
, instr
);
1416 h_u32_to_be(value_buf
, instr
);
1418 CHECK_RETVAL(target_write_buffer(target
, address
, 4, value_buf
));
1424 * Read 32-bit instruction from memory. It is like target_read_u32, however in
1425 * case of little endian ARC instructions are in middle endian format, so
1426 * different type of conversion should be done.
1428 int arc_read_instruction_u32(struct target
*target
, uint32_t address
,
1431 uint8_t value_buf
[4];
1433 if (!target_was_examined(target
)) {
1434 LOG_ERROR("Target not examined yet");
1439 CHECK_RETVAL(target_read_buffer(target
, address
, 4, value_buf
));
1441 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1442 *value
= arc_me_to_h_u32(value_buf
);
1444 *value
= be_to_h_u32(value_buf
);
1446 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1452 /* Actionpoint mechanism allows to setup HW breakpoints
1453 * and watchpoints. Each actionpoint is controlled by
1454 * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
1455 * and AP control(AC).
1456 * This function is for setting/unsetting actionpoints:
1457 * at - actionpoint target: trigger on mem/reg access
1458 * tt - transaction type : trigger on r/w. */
1459 static int arc_configure_actionpoint(struct target
*target
, uint32_t ap_num
,
1460 uint32_t match_value
, uint32_t control_tt
, uint32_t control_at
)
1462 struct arc_common
*arc
= target_to_arc(target
);
1464 if (control_tt
!= AP_AC_TT_DISABLE
) {
1466 if (arc
->actionpoints_num_avail
< 1) {
1467 LOG_ERROR("No free actionpoints, maximim amount is %u",
1468 arc
->actionpoints_num
);
1469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1472 /* Names of register to set - 24 chars should be enough. Looks a little
1473 * bit out-of-place for C code, but makes it aligned to the bigger
1474 * concept of "ARC registers are defined in TCL" as far as possible.
1476 char ap_amv_reg_name
[24], ap_amm_reg_name
[24], ap_ac_reg_name
[24];
1477 snprintf(ap_amv_reg_name
, 24, "ap_amv%" PRIu32
, ap_num
);
1478 snprintf(ap_amm_reg_name
, 24, "ap_amm%" PRIu32
, ap_num
);
1479 snprintf(ap_ac_reg_name
, 24, "ap_ac%" PRIu32
, ap_num
);
1480 CHECK_RETVAL(arc_set_register_value(target
, ap_amv_reg_name
,
1482 CHECK_RETVAL(arc_set_register_value(target
, ap_amm_reg_name
, 0));
1483 CHECK_RETVAL(arc_set_register_value(target
, ap_ac_reg_name
,
1484 control_tt
| control_at
));
1485 arc
->actionpoints_num_avail
--;
1487 char ap_ac_reg_name
[24];
1488 snprintf(ap_ac_reg_name
, 24, "ap_ac%" PRIu32
, ap_num
);
1489 CHECK_RETVAL(arc_set_register_value(target
, ap_ac_reg_name
,
1491 arc
->actionpoints_num_avail
++;
1497 static int arc_set_breakpoint(struct target
*target
,
1498 struct breakpoint
*breakpoint
)
1500 if (breakpoint
->set
) {
1501 LOG_WARNING("breakpoint already set");
1505 if (breakpoint
->type
== BKPT_SOFT
) {
1506 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1508 if (breakpoint
->length
== 4) {
1509 uint32_t verify
= 0xffffffff;
1511 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1512 breakpoint
->orig_instr
));
1514 CHECK_RETVAL(arc_write_instruction_u32(target
, breakpoint
->address
,
1517 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, &verify
));
1519 if (verify
!= ARC_SDBBP_32
) {
1520 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1521 " - check that memory is read/writable", breakpoint
->address
);
1524 } else if (breakpoint
->length
== 2) {
1525 uint16_t verify
= 0xffff;
1527 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1528 breakpoint
->orig_instr
));
1529 CHECK_RETVAL(target_write_u16(target
, breakpoint
->address
, ARC_SDBBP_16
));
1531 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, &verify
));
1532 if (verify
!= ARC_SDBBP_16
) {
1533 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1534 " - check that memory is read/writable", breakpoint
->address
);
1538 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1539 return ERROR_COMMAND_ARGUMENT_INVALID
;
1542 breakpoint
->set
= 64; /* Any nice value but 0 */
1543 } else if (breakpoint
->type
== BKPT_HARD
) {
1544 struct arc_common
*arc
= target_to_arc(target
);
1545 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1546 unsigned int bp_num
;
1548 for (bp_num
= 0; bp_num
< arc
->actionpoints_num
; bp_num
++) {
1549 if (!ap_list
[bp_num
].used
)
1553 if (bp_num
>= arc
->actionpoints_num
) {
1554 LOG_ERROR("No free actionpoints, maximum amount is %u",
1555 arc
->actionpoints_num
);
1556 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1559 int retval
= arc_configure_actionpoint(target
, bp_num
,
1560 breakpoint
->address
, AP_AC_TT_READWRITE
, AP_AC_AT_INST_ADDR
);
1562 if (retval
== ERROR_OK
) {
1563 breakpoint
->set
= bp_num
+ 1;
1564 ap_list
[bp_num
].used
= 1;
1565 ap_list
[bp_num
].bp_value
= breakpoint
->address
;
1566 ap_list
[bp_num
].type
= ARC_AP_BREAKPOINT
;
1568 LOG_DEBUG("bpid: %" PRIu32
", bp_num %u bp_value 0x%" PRIx32
,
1569 breakpoint
->unique_id
, bp_num
, ap_list
[bp_num
].bp_value
);
1573 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1577 /* core instruction cache is now invalid. */
1578 CHECK_RETVAL(arc_cache_invalidate(target
));
1583 static int arc_unset_breakpoint(struct target
*target
,
1584 struct breakpoint
*breakpoint
)
1586 int retval
= ERROR_OK
;
1588 if (!breakpoint
->set
) {
1589 LOG_WARNING("breakpoint not set");
1593 if (breakpoint
->type
== BKPT_SOFT
) {
1594 /* restore original instruction (kept in target endianness) */
1595 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1596 if (breakpoint
->length
== 4) {
1597 uint32_t current_instr
;
1599 /* check that user program has not modified breakpoint instruction */
1600 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, ¤t_instr
));
1602 if (current_instr
== ARC_SDBBP_32
) {
1603 retval
= target_write_buffer(target
, breakpoint
->address
,
1604 breakpoint
->length
, breakpoint
->orig_instr
);
1605 if (retval
!= ERROR_OK
)
1608 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1609 " has been overwritten outside of debugger."
1610 "Expected: @0x%x, got: @0x%" PRIx32
,
1611 breakpoint
->address
, ARC_SDBBP_32
, current_instr
);
1613 } else if (breakpoint
->length
== 2) {
1614 uint16_t current_instr
;
1616 /* check that user program has not modified breakpoint instruction */
1617 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, ¤t_instr
));
1618 if (current_instr
== ARC_SDBBP_16
) {
1619 retval
= target_write_buffer(target
, breakpoint
->address
,
1620 breakpoint
->length
, breakpoint
->orig_instr
);
1621 if (retval
!= ERROR_OK
)
1624 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1625 " has been overwritten outside of debugger. "
1626 "Expected: 0x%04x, got: 0x%04" PRIx16
,
1627 breakpoint
->address
, ARC_SDBBP_16
, current_instr
);
1630 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1631 return ERROR_COMMAND_ARGUMENT_INVALID
;
1633 breakpoint
->set
= 0;
1635 } else if (breakpoint
->type
== BKPT_HARD
) {
1636 struct arc_common
*arc
= target_to_arc(target
);
1637 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1638 unsigned int bp_num
= breakpoint
->set
- 1;
1640 if ((breakpoint
->set
== 0) || (bp_num
>= arc
->actionpoints_num
)) {
1641 LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32
,
1642 bp_num
, breakpoint
->unique_id
);
1646 retval
= arc_configure_actionpoint(target
, bp_num
,
1647 breakpoint
->address
, AP_AC_TT_DISABLE
, AP_AC_AT_INST_ADDR
);
1649 if (retval
== ERROR_OK
) {
1650 breakpoint
->set
= 0;
1651 ap_list
[bp_num
].used
= 0;
1652 ap_list
[bp_num
].bp_value
= 0;
1654 LOG_DEBUG("bpid: %" PRIu32
" - released actionpoint ID: %i",
1655 breakpoint
->unique_id
, bp_num
);
1658 LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1662 /* core instruction cache is now invalid. */
1663 CHECK_RETVAL(arc_cache_invalidate(target
));
1669 static int arc_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1671 if (target
->state
== TARGET_HALTED
) {
1672 return arc_set_breakpoint(target
, breakpoint
);
1675 LOG_WARNING(" > core was not halted, please try again.");
1676 return ERROR_TARGET_NOT_HALTED
;
1680 static int arc_remove_breakpoint(struct target
*target
,
1681 struct breakpoint
*breakpoint
)
1683 if (target
->state
== TARGET_HALTED
) {
1684 if (breakpoint
->set
)
1685 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
1687 LOG_WARNING("target not halted");
1688 return ERROR_TARGET_NOT_HALTED
;
1694 void arc_reset_actionpoints(struct target
*target
)
1696 struct arc_common
*arc
= target_to_arc(target
);
1697 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1698 struct breakpoint
*next_b
;
1700 while (target
->breakpoints
) {
1701 next_b
= target
->breakpoints
->next
;
1702 arc_remove_breakpoint(target
, target
->breakpoints
);
1703 free(target
->breakpoints
->orig_instr
);
1704 free(target
->breakpoints
);
1705 target
->breakpoints
= next_b
;
1707 for (unsigned int i
= 0; i
< arc
->actionpoints_num
; i
++) {
1708 if ((ap_list
[i
].used
) && (ap_list
[i
].reg_address
))
1709 arc_remove_auxreg_actionpoint(target
, ap_list
[i
].reg_address
);
1713 int arc_set_actionpoints_num(struct target
*target
, uint32_t ap_num
)
1715 LOG_DEBUG("target=%s actionpoints=%" PRIu32
, target_name(target
), ap_num
);
1716 struct arc_common
*arc
= target_to_arc(target
);
1718 /* Make sure that there are no enabled actionpoints in target. */
1719 arc_reset_actionpoints(target
);
1721 /* Assume that all points have been removed from target. */
1722 free(arc
->actionpoints_list
);
1724 arc
->actionpoints_num_avail
= ap_num
;
1725 arc
->actionpoints_num
= ap_num
;
1726 /* calloc can be safely called when ncount == 0. */
1727 arc
->actionpoints_list
= calloc(ap_num
, sizeof(struct arc_actionpoint
));
1729 if (!arc
->actionpoints_list
) {
1730 LOG_ERROR("Unable to allocate memory");
1737 int arc_add_auxreg_actionpoint(struct target
*target
,
1738 uint32_t auxreg_addr
, uint32_t transaction
)
1740 unsigned int ap_num
= 0;
1741 int retval
= ERROR_OK
;
1743 if (target
->state
!= TARGET_HALTED
)
1744 return ERROR_TARGET_NOT_HALTED
;
1746 struct arc_common
*arc
= target_to_arc(target
);
1747 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1749 while (ap_list
[ap_num
].used
)
1752 if (ap_num
>= arc
->actionpoints_num
) {
1753 LOG_ERROR("No actionpoint free, maximum amount is %u",
1754 arc
->actionpoints_num
);
1755 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1758 retval
= arc_configure_actionpoint(target
, ap_num
,
1759 auxreg_addr
, transaction
, AP_AC_AT_AUXREG_ADDR
);
1761 if (retval
== ERROR_OK
) {
1762 ap_list
[ap_num
].used
= 1;
1763 ap_list
[ap_num
].reg_address
= auxreg_addr
;
1769 int arc_remove_auxreg_actionpoint(struct target
*target
, uint32_t auxreg_addr
)
1771 int retval
= ERROR_OK
;
1772 bool ap_found
= false;
1773 unsigned int ap_num
= 0;
1775 if (target
->state
!= TARGET_HALTED
)
1776 return ERROR_TARGET_NOT_HALTED
;
1778 struct arc_common
*arc
= target_to_arc(target
);
1779 struct arc_actionpoint
*ap_list
= arc
->actionpoints_list
;
1781 while ((ap_list
[ap_num
].used
) && (ap_num
< arc
->actionpoints_num
)) {
1782 if (ap_list
[ap_num
].reg_address
== auxreg_addr
) {
1790 retval
= arc_configure_actionpoint(target
, ap_num
,
1791 auxreg_addr
, AP_AC_TT_DISABLE
, AP_AC_AT_AUXREG_ADDR
);
1793 if (retval
== ERROR_OK
) {
1794 ap_list
[ap_num
].used
= 0;
1795 ap_list
[ap_num
].bp_value
= 0;
1798 LOG_ERROR("Register actionpoint not found");
1803 /* Helper function which switches core to single_step mode by
1804 * doing aux r/w operations. */
1805 int arc_config_step(struct target
*target
, int enable_step
)
1809 struct arc_common
*arc
= target_to_arc(target
);
1811 /* enable core debug step mode */
1813 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1815 value
&= ~SET_CORE_AE_BIT
; /* clear the AE bit */
1816 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1818 LOG_DEBUG(" [status32:0x%08" PRIx32
"]", value
);
1820 /* Doing read-modify-write, because DEBUG might contain manually set
1821 * bits like UB or ED, which should be preserved. */
1822 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
,
1823 AUX_DEBUG_REG
, &value
));
1824 value
|= SET_CORE_SINGLE_INSTR_STEP
; /* set the IS bit */
1825 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1827 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32
"]", value
);
1829 } else { /* disable core debug step mode */
1830 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1832 value
&= ~SET_CORE_SINGLE_INSTR_STEP
; /* clear the IS bit */
1833 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1835 LOG_DEBUG("core debug step mode disabled");
1841 int arc_step(struct target
*target
, int current
, target_addr_t address
,
1842 int handle_breakpoints
)
1844 /* get pointers to arch-specific information */
1845 struct arc_common
*arc
= target_to_arc(target
);
1846 struct breakpoint
*breakpoint
= NULL
;
1847 struct reg
*pc
= &(arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
]);
1849 if (target
->state
!= TARGET_HALTED
) {
1850 LOG_WARNING("target not halted");
1851 return ERROR_TARGET_NOT_HALTED
;
1854 /* current = 1: continue on current pc, otherwise continue at <address> */
1856 buf_set_u32(pc
->value
, 0, 32, address
);
1861 LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32
,
1862 buf_get_u32(pc
->value
, 0, 32));
1864 /* the front-end may request us not to handle breakpoints */
1865 if (handle_breakpoints
) {
1866 breakpoint
= breakpoint_find(target
, buf_get_u32(pc
->value
, 0, 32));
1868 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
1871 /* restore context */
1872 CHECK_RETVAL(arc_restore_context(target
));
1874 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1876 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1878 /* disable interrupts while stepping */
1879 CHECK_RETVAL(arc_enable_interrupts(target
, 0));
1881 /* do a single step */
1882 CHECK_RETVAL(arc_config_step(target
, 1));
1884 /* make sure we done our step */
1887 /* registers are now invalid */
1888 register_cache_invalidate(arc
->core_and_aux_cache
);
1891 CHECK_RETVAL(arc_set_breakpoint(target
, breakpoint
));
1893 LOG_DEBUG("target stepped ");
1895 target
->state
= TARGET_HALTED
;
1897 /* Saving context */
1898 CHECK_RETVAL(arc_debug_entry(target
));
1899 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1905 /* This function invalidates icache. */
1906 static int arc_icache_invalidate(struct target
*target
)
1910 struct arc_common
*arc
= target_to_arc(target
);
1912 /* Don't waste time if already done. */
1913 if (!arc
->has_icache
|| arc
->icache_invalidated
)
1916 LOG_DEBUG("Invalidating I$.");
1918 value
= IC_IVIC_INVALIDATE
; /* invalidate I$ */
1919 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_IC_IVIC_REG
, value
));
1921 arc
->icache_invalidated
= true;
1926 /* This function invalidates dcache */
1927 static int arc_dcache_invalidate(struct target
*target
)
1929 uint32_t value
, dc_ctrl_value
;
1931 struct arc_common
*arc
= target_to_arc(target
);
1933 if (!arc
->has_dcache
|| arc
->dcache_invalidated
)
1936 LOG_DEBUG("Invalidating D$.");
1938 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, &value
));
1939 dc_ctrl_value
= value
;
1940 value
&= ~DC_CTRL_IM
;
1942 /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
1943 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, value
));
1944 value
= DC_IVDC_INVALIDATE
; /* invalidate D$ */
1945 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_IVDC_REG
, value
));
1947 /* restore DC_CTRL invalidate mode */
1948 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, dc_ctrl_value
));
1950 arc
->dcache_invalidated
= true;
1955 /* This function invalidates l2 cache. */
1956 static int arc_l2cache_invalidate(struct target
*target
)
1958 uint32_t value
, slc_ctrl_value
;
1960 struct arc_common
*arc
= target_to_arc(target
);
1962 if (!arc
->has_l2cache
|| arc
->l2cache_invalidated
)
1965 LOG_DEBUG("Invalidating L2$.");
1967 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
1968 slc_ctrl_value
= value
;
1969 value
&= ~L2_CTRL_IM
;
1971 /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
1972 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, value
));
1973 /* invalidate L2$ */
1974 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_INV
, L2_INV_IV
));
1976 /* Wait until invalidate operation ends */
1978 LOG_DEBUG("Waiting for invalidation end.");
1979 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
1980 } while (value
& L2_CTRL_BS
);
1982 /* restore L2_CTRL invalidate mode */
1983 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, slc_ctrl_value
));
1985 arc
->l2cache_invalidated
= true;
1991 int arc_cache_invalidate(struct target
*target
)
1993 CHECK_RETVAL(arc_icache_invalidate(target
));
1994 CHECK_RETVAL(arc_dcache_invalidate(target
));
1995 CHECK_RETVAL(arc_l2cache_invalidate(target
));
2000 /* Flush data cache. This function is cheap to call and return quickly if D$
2001 * already has been flushed since target had been halted. JTAG debugger reads
2002 * values directly from memory, bypassing cache, so if there are unflushed
2003 * lines debugger will read invalid values, which will cause a lot of troubles.
2005 int arc_dcache_flush(struct target
*target
)
2007 uint32_t value
, dc_ctrl_value
;
2008 bool has_to_set_dc_ctrl_im
;
2010 struct arc_common
*arc
= target_to_arc(target
);
2012 /* Don't waste time if already done. */
2013 if (!arc
->has_dcache
|| arc
->dcache_flushed
)
2016 LOG_DEBUG("Flushing D$.");
2018 /* Store current value of DC_CTRL */
2019 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, &dc_ctrl_value
));
2021 /* Set DC_CTRL invalidate mode to flush (if not already set) */
2022 has_to_set_dc_ctrl_im
= (dc_ctrl_value
& DC_CTRL_IM
) == 0;
2023 if (has_to_set_dc_ctrl_im
) {
2024 value
= dc_ctrl_value
| DC_CTRL_IM
;
2025 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, value
));
2029 value
= DC_IVDC_INVALIDATE
;
2030 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_IVDC_REG
, value
));
2032 /* Restore DC_CTRL invalidate mode (even of flush failed) */
2033 if (has_to_set_dc_ctrl_im
)
2034 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DC_CTRL_REG
, dc_ctrl_value
));
2036 arc
->dcache_flushed
= true;
2041 /* This function flushes l2cache. */
2042 static int arc_l2cache_flush(struct target
*target
)
2046 struct arc_common
*arc
= target_to_arc(target
);
2048 /* Don't waste time if already done. */
2049 if (!arc
->has_l2cache
|| arc
->l2cache_flushed
)
2052 LOG_DEBUG("Flushing L2$.");
2054 /* Flush L2 cache */
2055 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_FLUSH
, L2_FLUSH_FL
));
2057 /* Wait until flush operation ends */
2059 LOG_DEBUG("Waiting for flushing end.");
2060 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, SLC_AUX_CACHE_CTRL
, &value
));
2061 } while (value
& L2_CTRL_BS
);
2063 arc
->l2cache_flushed
= true;
2068 int arc_cache_flush(struct target
*target
)
2070 CHECK_RETVAL(arc_dcache_flush(target
));
2071 CHECK_RETVAL(arc_l2cache_flush(target
));
2077 struct target_type arcv2_target
= {
2082 .arch_state
= arc_arch_state
,
2084 /* TODO That seems like something similar to metaware hostlink, so perhaps
2085 * we can exploit this in the future. */
2086 .target_request_data
= NULL
,
2089 .resume
= arc_resume
,
2092 .assert_reset
= arc_assert_reset
,
2093 .deassert_reset
= arc_deassert_reset
,
2095 /* TODO Implement soft_reset_halt */
2096 .soft_reset_halt
= NULL
,
2098 .get_gdb_reg_list
= arc_get_gdb_reg_list
,
2100 .read_memory
= arc_mem_read
,
2101 .write_memory
= arc_mem_write
,
2102 .checksum_memory
= NULL
,
2103 .blank_check_memory
= NULL
,
2105 .add_breakpoint
= arc_add_breakpoint
,
2106 .add_context_breakpoint
= NULL
,
2107 .add_hybrid_breakpoint
= NULL
,
2108 .remove_breakpoint
= arc_remove_breakpoint
,
2109 .add_watchpoint
= NULL
,
2110 .remove_watchpoint
= NULL
,
2111 .hit_watchpoint
= NULL
,
2113 .run_algorithm
= NULL
,
2114 .start_algorithm
= NULL
,
2115 .wait_algorithm
= NULL
,
2117 .commands
= arc_monitor_command_handlers
,
2119 .target_create
= arc_target_create
,
2120 .init_target
= arc_init_target
,
2121 .deinit_target
= arc_deinit_target
,
2122 .examine
= arc_examine
,
2125 .read_phys_memory
= NULL
,
2126 .write_phys_memory
= NULL
,
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