Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / arc.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
5 * Frank Dols <frank.dols@synopsys.com> *
6 * Mischa Jonker <mischa.jonker@synopsys.com> *
7 * Anton Kolesov <anton.kolesov@synopsys.com> *
8 * Evgeniy Didin <didin@synopsys.com> *
9 ***************************************************************************/
10
11
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15
16 #include "arc.h"
17
18
19
20 /*
21 * ARC architecture specific details.
22 *
23 * ARC has two types of registers:
24 * 1) core registers(e.g. r0,r1..) [is_core = true]
25 * 2) Auxiliary registers [is_core = false]..
26 *
27 * Auxiliary registers at the same time can be divided into
28 * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
29 * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
30 *
31 * The way of accessing to Core and AUX registers differs on Jtag level.
32 * BCR/non-BCR describes if the register is immutable and that reading
33 * unexisting register is safe RAZ, rather then an error.
34 * Note, core registers cannot be BCR.
35 *
36 * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
37 * and BCR aux, in "add-reg" command they are passed to three lists
38 * respectively: core_reg_descriptions, aux_reg_descriptions,
39 * bcr_reg_descriptions.
40 *
41 * Due to the specifics of accessing to BCR/non-BCR registers there are two
42 * register caches:
43 * 1) core_and_aux_cache - includes registers described in
44 * core_reg_descriptions and aux_reg_descriptions lists.
45 * Used during save/restore context step.
46 * 2) bcr_cache - includes registers described bcr_reg_descriptions.
47 * Currently used internally during configure step.
48 */
49
50
51 static int arc_remove_watchpoint(struct target *target,
52 struct watchpoint *watchpoint);
53 static int arc_enable_watchpoints(struct target *target);
54 static int arc_enable_breakpoints(struct target *target);
55 static int arc_unset_breakpoint(struct target *target,
56 struct breakpoint *breakpoint);
57 static int arc_set_breakpoint(struct target *target,
58 struct breakpoint *breakpoint);
59 static int arc_single_step_core(struct target *target);
60
61 void arc_reg_data_type_add(struct target *target,
62 struct arc_reg_data_type *data_type)
63 {
64 LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
65 struct arc_common *arc = target_to_arc(target);
66 assert(arc);
67
68 list_add_tail(&data_type->list, &arc->reg_data_types);
69 }
70
71 /**
72 * Private implementation of register_get_by_name() for ARC that
73 * doesn't skip not [yet] existing registers. Used in many places
74 * for iteration through registers and even for marking required registers as
75 * existing.
76 */
77 struct reg *arc_reg_get_by_name(struct reg_cache *first,
78 const char *name, bool search_all)
79 {
80 unsigned int i;
81 struct reg_cache *cache = first;
82
83 while (cache) {
84 for (i = 0; i < cache->num_regs; i++) {
85 if (!strcmp(cache->reg_list[i].name, name))
86 return &(cache->reg_list[i]);
87 }
88
89 if (search_all)
90 cache = cache->next;
91 else
92 break;
93 }
94
95 return NULL;
96 }
97
98 /**
99 * Reset internal states of caches. Must be called when entering debugging.
100 *
101 * @param target Target for which to reset caches states.
102 */
103 static int arc_reset_caches_states(struct target *target)
104 {
105 struct arc_common *arc = target_to_arc(target);
106
107 LOG_DEBUG("Resetting internal variables of caches states");
108
109 /* Reset caches states. */
110 arc->dcache_flushed = false;
111 arc->l2cache_flushed = false;
112 arc->icache_invalidated = false;
113 arc->dcache_invalidated = false;
114 arc->l2cache_invalidated = false;
115
116 return ERROR_OK;
117 }
118
119 /* Initialize arc_common structure, which passes to openocd target instance */
120 static int arc_init_arch_info(struct target *target, struct arc_common *arc,
121 struct jtag_tap *tap)
122 {
123 arc->common_magic = ARC_COMMON_MAGIC;
124 target->arch_info = arc;
125
126 arc->jtag_info.tap = tap;
127
128 /* The only allowed ir_length is 4 for ARC jtag. */
129 if (tap->ir_length != 4) {
130 LOG_ERROR("ARC jtag instruction length should be equal to 4");
131 return ERROR_FAIL;
132 }
133
134 /* On most ARC targets there is a dcache, so we enable its flushing
135 * by default. If there no dcache, there will be no error, just a slight
136 * performance penalty from unnecessary JTAG operations. */
137 arc->has_dcache = true;
138 arc->has_icache = true;
139 /* L2$ is not available in a target by default. */
140 arc->has_l2cache = false;
141 arc_reset_caches_states(target);
142
143 /* Add standard GDB data types */
144 INIT_LIST_HEAD(&arc->reg_data_types);
145 struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
146 sizeof(*std_types));
147
148 if (!std_types) {
149 LOG_ERROR("Unable to allocate memory");
150 return ERROR_FAIL;
151 }
152
153 for (unsigned int i = 0; i < ARRAY_SIZE(standard_gdb_types); i++) {
154 std_types[i].data_type.type = standard_gdb_types[i].type;
155 std_types[i].data_type.id = standard_gdb_types[i].id;
156 arc_reg_data_type_add(target, &(std_types[i]));
157 }
158
159 /* Fields related to target descriptions */
160 INIT_LIST_HEAD(&arc->core_reg_descriptions);
161 INIT_LIST_HEAD(&arc->aux_reg_descriptions);
162 INIT_LIST_HEAD(&arc->bcr_reg_descriptions);
163 arc->num_regs = 0;
164 arc->num_core_regs = 0;
165 arc->num_aux_regs = 0;
166 arc->num_bcr_regs = 0;
167 arc->last_general_reg = ULONG_MAX;
168 arc->pc_index_in_cache = ULONG_MAX;
169 arc->debug_index_in_cache = ULONG_MAX;
170
171 return ERROR_OK;
172 }
173
174 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
175 const char * const type_name, const size_t type_name_len)
176 {
177 assert(target);
178 assert(arc_reg);
179
180 struct arc_common *arc = target_to_arc(target);
181 assert(arc);
182
183 /* Find register type */
184 {
185 struct arc_reg_data_type *type;
186 list_for_each_entry(type, &arc->reg_data_types, list)
187 if (!strncmp(type->data_type.id, type_name, type_name_len)) {
188 arc_reg->data_type = &(type->data_type);
189 break;
190 }
191
192 if (!arc_reg->data_type)
193 return ERROR_ARC_REGTYPE_NOT_FOUND;
194 }
195
196 if (arc_reg->is_core) {
197 list_add_tail(&arc_reg->list, &arc->core_reg_descriptions);
198 arc->num_core_regs += 1;
199 } else if (arc_reg->is_bcr) {
200 list_add_tail(&arc_reg->list, &arc->bcr_reg_descriptions);
201 arc->num_bcr_regs += 1;
202 } else {
203 list_add_tail(&arc_reg->list, &arc->aux_reg_descriptions);
204 arc->num_aux_regs += 1;
205 }
206 arc->num_regs += 1;
207
208 LOG_DEBUG(
209 "added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
210 arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
211 arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "",
212 arc_reg->is_general ? ", general" : ""
213 );
214
215 return ERROR_OK;
216 }
217
218 /* Reading core or aux register */
219 static int arc_get_register(struct reg *reg)
220 {
221 assert(reg);
222
223 struct arc_reg_desc *desc = reg->arch_info;
224 struct target *target = desc->target;
225 struct arc_common *arc = target_to_arc(target);
226
227 uint32_t value;
228
229 if (reg->valid) {
230 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
231 reg->number, desc->name, target_buffer_get_u32(target, reg->value));
232 return ERROR_OK;
233 }
234
235 if (desc->is_core) {
236 /* Accessing to R61/R62 registers causes Jtag hang */
237 if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
238 LOG_ERROR("It is forbidden to read core registers 61 and 62.");
239 return ERROR_FAIL;
240 }
241 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
242 &value));
243 } else {
244 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
245 &value));
246 }
247
248 target_buffer_set_u32(target, reg->value, value);
249
250 /* If target is unhalted all register reads should be uncached. */
251 if (target->state == TARGET_HALTED)
252 reg->valid = true;
253 else
254 reg->valid = false;
255
256 reg->dirty = false;
257
258 LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
259 reg->number, desc->name, value);
260
261
262 return ERROR_OK;
263 }
264
265 /* Writing core or aux register */
266 static int arc_set_register(struct reg *reg, uint8_t *buf)
267 {
268 struct arc_reg_desc *desc = reg->arch_info;
269 struct target *target = desc->target;
270 uint32_t value = target_buffer_get_u32(target, buf);
271 /* Unlike "get" function "set" is supported only if target
272 * is in halt mode. Async writes are not supported yet. */
273 if (target->state != TARGET_HALTED)
274 return ERROR_TARGET_NOT_HALTED;
275
276 /* Accessing to R61/R62 registers causes Jtag hang */
277 if (desc->is_core && (desc->arch_num == ARC_R61 ||
278 desc->arch_num == ARC_R62)) {
279 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
280 return ERROR_FAIL;
281 }
282 target_buffer_set_u32(target, reg->value, value);
283
284 LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
285 reg->number, desc->name, value);
286
287 reg->valid = true;
288 reg->dirty = true;
289
290 return ERROR_OK;
291 }
292
293 static const struct reg_arch_type arc_reg_type = {
294 .get = arc_get_register,
295 .set = arc_set_register,
296 };
297
298 /* GDB register groups. For now we support only general and "empty" */
299 static const char * const reg_group_general = "general";
300 static const char * const reg_group_other = "";
301
302 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
303 static int arc_init_reg(struct target *target, struct reg *reg,
304 struct arc_reg_desc *reg_desc, unsigned long number)
305 {
306 assert(target);
307 assert(reg);
308 assert(reg_desc);
309
310 struct arc_common *arc = target_to_arc(target);
311
312 /* Initialize struct reg */
313 reg->name = reg_desc->name;
314 reg->size = 32; /* All register in ARC are 32-bit */
315 reg->value = reg_desc->reg_value;
316 reg->type = &arc_reg_type;
317 reg->arch_info = reg_desc;
318 reg->caller_save = true; /* @todo should be configurable. */
319 reg->reg_data_type = reg_desc->data_type;
320 reg->feature = &reg_desc->feature;
321
322 reg->feature->name = reg_desc->gdb_xml_feature;
323
324 /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
325 * value of a register GDB will use it as a number of register in
326 * P-packet. OpenOCD gdbserver will then use number of register in
327 * P-packet as an array index in the reg_list returned by
328 * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
329 * correctly it would be required to either sort registers in
330 * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
331 * according to how registers will be sorted in
332 * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
333 reg->number = number;
334
335 if (reg_desc->is_general) {
336 arc->last_general_reg = reg->number;
337 reg->group = reg_group_general;
338 } else {
339 reg->group = reg_group_other;
340 }
341
342 return ERROR_OK;
343 }
344
345 /* Building aux/core reg_cache */
346 static int arc_build_reg_cache(struct target *target)
347 {
348 unsigned long i = 0;
349 struct arc_reg_desc *reg_desc;
350 /* get pointers to arch-specific information */
351 struct arc_common *arc = target_to_arc(target);
352 const unsigned long num_regs = arc->num_core_regs + arc->num_aux_regs;
353 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
354 struct reg_cache *cache = calloc(1, sizeof(*cache));
355 struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
356
357 if (!cache || !reg_list) {
358 LOG_ERROR("Not enough memory");
359 goto fail;
360 }
361
362 /* Build the process context cache */
363 cache->name = "arc registers";
364 cache->next = NULL;
365 cache->reg_list = reg_list;
366 cache->num_regs = num_regs;
367 arc->core_and_aux_cache = cache;
368 (*cache_p) = cache;
369
370 if (list_empty(&arc->core_reg_descriptions)) {
371 LOG_ERROR("No core registers were defined");
372 goto fail;
373 }
374
375 list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
376 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
377
378 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
379 reg_list[i].name, reg_list[i].group,
380 reg_list[i].feature->name);
381
382 i += 1;
383 }
384
385 if (list_empty(&arc->aux_reg_descriptions)) {
386 LOG_ERROR("No aux registers were defined");
387 goto fail;
388 }
389
390 list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
391 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
392
393 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
394 reg_list[i].name, reg_list[i].group,
395 reg_list[i].feature->name);
396
397 /* PC and DEBUG are essential so we search for them. */
398 if (!strcmp("pc", reg_desc->name)) {
399 if (arc->pc_index_in_cache != ULONG_MAX) {
400 LOG_ERROR("Double definition of PC in configuration");
401 goto fail;
402 }
403 arc->pc_index_in_cache = i;
404 } else if (!strcmp("debug", reg_desc->name)) {
405 if (arc->debug_index_in_cache != ULONG_MAX) {
406 LOG_ERROR("Double definition of DEBUG in configuration");
407 goto fail;
408 }
409 arc->debug_index_in_cache = i;
410 }
411 i += 1;
412 }
413
414 if (arc->pc_index_in_cache == ULONG_MAX
415 || arc->debug_index_in_cache == ULONG_MAX) {
416 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
417 goto fail;
418 }
419
420 assert(i == (arc->num_core_regs + arc->num_aux_regs));
421
422 arc->core_aux_cache_built = true;
423
424 return ERROR_OK;
425
426 fail:
427 free(cache);
428 free(reg_list);
429
430 return ERROR_FAIL;
431 }
432
433 /* Build bcr reg_cache.
434 * This function must be called only after arc_build_reg_cache */
435 static int arc_build_bcr_reg_cache(struct target *target)
436 {
437 /* get pointers to arch-specific information */
438 struct arc_common *arc = target_to_arc(target);
439 const unsigned long num_regs = arc->num_bcr_regs;
440 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
441 struct reg_cache *cache = malloc(sizeof(*cache));
442 struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
443
444 struct arc_reg_desc *reg_desc;
445 unsigned long i = 0;
446 unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
447
448 if (!cache || !reg_list) {
449 LOG_ERROR("Unable to allocate memory");
450 goto fail;
451 }
452
453 /* Build the process context cache */
454 cache->name = "arc.bcr";
455 cache->next = NULL;
456 cache->reg_list = reg_list;
457 cache->num_regs = num_regs;
458 arc->bcr_cache = cache;
459 (*cache_p) = cache;
460
461 if (list_empty(&arc->bcr_reg_descriptions)) {
462 LOG_ERROR("No BCR registers are defined");
463 goto fail;
464 }
465
466 list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
467 CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
468 /* BCRs always semantically, they are just read-as-zero, if there is
469 * not real register. */
470 reg_list[i].exist = true;
471
472 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
473 reg_list[i].name, reg_list[i].group,
474 reg_list[i].feature->name);
475 i += 1;
476 gdb_regnum += 1;
477 }
478
479 assert(i == arc->num_bcr_regs);
480
481 arc->bcr_cache_built = true;
482
483
484 return ERROR_OK;
485 fail:
486 free(cache);
487 free(reg_list);
488
489 return ERROR_FAIL;
490 }
491
492
493 static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
494 int *reg_list_size, enum target_register_class reg_class)
495 {
496 assert(target->reg_cache);
497 struct arc_common *arc = target_to_arc(target);
498
499 /* get pointers to arch-specific information storage */
500 *reg_list_size = arc->num_regs;
501 *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
502
503 if (!*reg_list) {
504 LOG_ERROR("Unable to allocate memory");
505 return ERROR_FAIL;
506 }
507
508 /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
509 * XML tdesc it filters out !exist registers, however when creating a
510 * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
511 * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
512 * out !exist register for "general", but not for "all". Attempts to filter out
513 * !exist for "all" as well will cause a failed check in OpenOCD GDB
514 * server. */
515 if (reg_class == REG_CLASS_ALL) {
516 unsigned long i = 0;
517 struct reg_cache *reg_cache = target->reg_cache;
518 while (reg_cache) {
519 for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
520 (*reg_list)[i] = &reg_cache->reg_list[j];
521 reg_cache = reg_cache->next;
522 }
523 assert(i == arc->num_regs);
524 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
525 } else {
526 unsigned long i = 0;
527 unsigned long gdb_reg_number = 0;
528 struct reg_cache *reg_cache = target->reg_cache;
529 while (reg_cache) {
530 for (unsigned j = 0;
531 j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
532 j++) {
533 if (reg_cache->reg_list[j].exist) {
534 (*reg_list)[i] = &reg_cache->reg_list[j];
535 i++;
536 }
537 gdb_reg_number += 1;
538 }
539 reg_cache = reg_cache->next;
540 }
541 *reg_list_size = i;
542 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
543 }
544
545 return ERROR_OK;
546 }
547
548 /* Reading field of struct_type register */
549 int arc_reg_get_field(struct target *target, const char *reg_name,
550 const char *field_name, uint32_t *value_ptr)
551 {
552 struct reg_data_type_struct_field *field;
553
554 LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
555
556 /* Get register */
557 struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
558
559 if (!reg) {
560 LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
561 return ERROR_ARC_REGISTER_NOT_FOUND;
562 }
563
564 if (reg->reg_data_type->type != REG_TYPE_ARCH_DEFINED
565 || reg->reg_data_type->type_class != REG_TYPE_CLASS_STRUCT)
566 return ERROR_ARC_REGISTER_IS_NOT_STRUCT;
567
568 /* Get field in a register */
569 struct reg_data_type_struct *reg_struct =
570 reg->reg_data_type->reg_type_struct;
571 for (field = reg_struct->fields;
572 field;
573 field = field->next) {
574 if (!strcmp(field->name, field_name))
575 break;
576 }
577
578 if (!field)
579 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND;
580
581 if (!field->use_bitfields)
582 return ERROR_ARC_FIELD_IS_NOT_BITFIELD;
583
584 if (!reg->valid)
585 CHECK_RETVAL(reg->type->get(reg));
586
587 /* First do endianness-safe read of register value
588 * then convert it to binary buffer for further
589 * field extraction */
590
591 *value_ptr = buf_get_u32(reg->value, field->bitfield->start,
592 field->bitfield->end - field->bitfield->start + 1);
593
594 return ERROR_OK;
595 }
596
597 static int arc_get_register_value(struct target *target, const char *reg_name,
598 uint32_t *value_ptr)
599 {
600 LOG_DEBUG("reg_name=%s", reg_name);
601
602 struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
603
604 if (!reg)
605 return ERROR_ARC_REGISTER_NOT_FOUND;
606
607 if (!reg->valid)
608 CHECK_RETVAL(reg->type->get(reg));
609
610 *value_ptr = target_buffer_get_u32(target, reg->value);
611
612 return ERROR_OK;
613 }
614
615 static int arc_set_register_value(struct target *target, const char *reg_name,
616 uint32_t value)
617 {
618 LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
619
620 if (!(target && reg_name)) {
621 LOG_ERROR("Arguments cannot be NULL.");
622 return ERROR_FAIL;
623 }
624
625 struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
626
627 if (!reg)
628 return ERROR_ARC_REGISTER_NOT_FOUND;
629
630 uint8_t value_buf[4];
631 buf_set_u32(value_buf, 0, 32, value);
632 CHECK_RETVAL(reg->type->set(reg, value_buf));
633
634 return ERROR_OK;
635 }
636
637 /* Configure DCCM's */
638 static int arc_configure_dccm(struct target *target)
639 {
640 struct arc_common *arc = target_to_arc(target);
641
642 uint32_t dccm_build_version, dccm_build_size0, dccm_build_size1;
643 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
644 &dccm_build_version));
645 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
646 &dccm_build_size0));
647 CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
648 &dccm_build_size1));
649 /* There is no yet support of configurable number of cycles,
650 * So there is no difference between v3 and v4 */
651 if ((dccm_build_version == 3 || dccm_build_version == 4) && dccm_build_size0 > 0) {
652 CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
653 uint32_t dccm_size = 0x100;
654 dccm_size <<= dccm_build_size0;
655 if (dccm_build_size0 == 0xF)
656 dccm_size <<= dccm_build_size1;
657 arc->dccm_end = arc->dccm_start + dccm_size;
658 LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
659 arc->dccm_start, arc->dccm_end);
660
661 }
662 return ERROR_OK;
663 }
664
665
666 /* Configure ICCM's */
667
668 static int arc_configure_iccm(struct target *target)
669 {
670 struct arc_common *arc = target_to_arc(target);
671
672 /* ICCM0 */
673 uint32_t iccm_build_version, iccm_build_size00, iccm_build_size01;
674 uint32_t aux_iccm = 0;
675 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
676 &iccm_build_version));
677 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
678 &iccm_build_size00));
679 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
680 &iccm_build_size01));
681 if (iccm_build_version == 4 && iccm_build_size00 > 0) {
682 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
683 uint32_t iccm0_size = 0x100;
684 iccm0_size <<= iccm_build_size00;
685 if (iccm_build_size00 == 0xF)
686 iccm0_size <<= iccm_build_size01;
687 /* iccm0 start is located in highest 4 bits of aux_iccm */
688 arc->iccm0_start = aux_iccm & 0xF0000000;
689 arc->iccm0_end = arc->iccm0_start + iccm0_size;
690 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
691 arc->iccm0_start, arc->iccm0_end);
692 }
693
694 /* ICCM1 */
695 uint32_t iccm_build_size10, iccm_build_size11;
696 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
697 &iccm_build_size10));
698 CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
699 &iccm_build_size11));
700 if (iccm_build_version == 4 && iccm_build_size10 > 0) {
701 /* Use value read for ICCM0 */
702 if (!aux_iccm)
703 CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
704 uint32_t iccm1_size = 0x100;
705 iccm1_size <<= iccm_build_size10;
706 if (iccm_build_size10 == 0xF)
707 iccm1_size <<= iccm_build_size11;
708 arc->iccm1_start = aux_iccm & 0x0F000000;
709 arc->iccm1_end = arc->iccm1_start + iccm1_size;
710 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
711 arc->iccm1_start, arc->iccm1_end);
712 }
713 return ERROR_OK;
714 }
715
716 /* Configure some core features, depending on BCRs. */
717 static int arc_configure(struct target *target)
718 {
719 LOG_DEBUG("Configuring ARC ICCM and DCCM");
720
721 /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
722 if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
723 arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
724 CHECK_RETVAL(arc_configure_dccm(target));
725
726 /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
727 if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
728 arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
729 CHECK_RETVAL(arc_configure_iccm(target));
730
731 return ERROR_OK;
732 }
733
734 /* arc_examine is function, which is used for all arc targets*/
735 static int arc_examine(struct target *target)
736 {
737 uint32_t status;
738 struct arc_common *arc = target_to_arc(target);
739
740 CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
741
742 if (!target_was_examined(target)) {
743 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
744 if (status & ARC_JTAG_STAT_RU)
745 target->state = TARGET_RUNNING;
746 else
747 target->state = TARGET_HALTED;
748
749 /* Read BCRs and configure optional registers. */
750 CHECK_RETVAL(arc_configure(target));
751
752 target_set_examined(target);
753 }
754
755 return ERROR_OK;
756 }
757
758 static int arc_exit_debug(struct target *target)
759 {
760 uint32_t value;
761 struct arc_common *arc = target_to_arc(target);
762
763 /* Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally. */
764 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
765 value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
766 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
767 alive_sleep(1);
768
769 target->state = TARGET_HALTED;
770 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
771
772 if (debug_level >= LOG_LVL_DEBUG) {
773 LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
774 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
775 LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
776 }
777
778 return ERROR_OK;
779 }
780
781 static int arc_halt(struct target *target)
782 {
783 uint32_t value, irq_state;
784 struct arc_common *arc = target_to_arc(target);
785
786 LOG_DEBUG("target->state: %s", target_state_name(target));
787
788 if (target->state == TARGET_HALTED) {
789 LOG_DEBUG("target was already halted");
790 return ERROR_OK;
791 }
792
793 if (target->state == TARGET_UNKNOWN)
794 LOG_WARNING("target was in unknown state when halt was requested");
795
796 if (target->state == TARGET_RESET) {
797 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
798 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
799 return ERROR_TARGET_FAILURE;
800 } else {
801 target->debug_reason = DBG_REASON_DBGRQ;
802 }
803 }
804
805 /* Break (stop) processor.
806 * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
807 * We do not use here arc_get/set_core_reg functions here because they imply
808 * that the processor is already halted. */
809 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
810 value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
811 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
812 alive_sleep(1);
813
814 /* Save current IRQ state */
815 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
816
817 if (irq_state & AUX_STATUS32_REG_IE_BIT)
818 arc->irq_state = 1;
819 else
820 arc->irq_state = 0;
821
822 /* update state and notify gdb*/
823 target->state = TARGET_HALTED;
824 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
825
826 /* some more debug information */
827 if (debug_level >= LOG_LVL_DEBUG) {
828 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
829 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
830 LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
831 }
832
833 return ERROR_OK;
834 }
835
836 /**
837 * Read registers that are used in GDB g-packet. We don't read them one-by-one,
838 * but do that in one batch operation to improve speed. Calls to JTAG layer are
839 * expensive so it is better to make one big call that reads all necessary
840 * registers, instead of many calls, one for one register.
841 */
842 static int arc_save_context(struct target *target)
843 {
844 int retval = ERROR_OK;
845 unsigned int i;
846 struct arc_common *arc = target_to_arc(target);
847 struct reg *reg_list = arc->core_and_aux_cache->reg_list;
848
849 LOG_DEBUG("Saving aux and core registers values");
850 assert(reg_list);
851
852 /* It is assumed that there is at least one AUX register in the list, for
853 * example PC. */
854 const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
855 /* last_general_reg is inclusive number. To get count of registers it is
856 * required to do +1. */
857 const uint32_t regs_to_scan =
858 MIN(arc->last_general_reg + 1, arc->num_regs);
859 const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
860 uint32_t *core_values = malloc(core_regs_size);
861 uint32_t *aux_values = malloc(aux_regs_size);
862 uint32_t *core_addrs = malloc(core_regs_size);
863 uint32_t *aux_addrs = malloc(aux_regs_size);
864 unsigned int core_cnt = 0;
865 unsigned int aux_cnt = 0;
866
867 if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
868 LOG_ERROR("Unable to allocate memory");
869 retval = ERROR_FAIL;
870 goto exit;
871 }
872
873 memset(core_values, 0xff, core_regs_size);
874 memset(core_addrs, 0xff, core_regs_size);
875 memset(aux_values, 0xff, aux_regs_size);
876 memset(aux_addrs, 0xff, aux_regs_size);
877
878 for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
879 struct reg *reg = reg_list + i;
880 struct arc_reg_desc *arc_reg = reg->arch_info;
881 if (!reg->valid && reg->exist)
882 core_addrs[core_cnt++] = arc_reg->arch_num;
883 }
884
885 for (i = arc->num_core_regs; i < regs_to_scan; i++) {
886 struct reg *reg = reg_list + i;
887 struct arc_reg_desc *arc_reg = reg->arch_info;
888 if (!reg->valid && reg->exist)
889 aux_addrs[aux_cnt++] = arc_reg->arch_num;
890 }
891
892 /* Read data from target. */
893 if (core_cnt > 0) {
894 retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
895 if (retval != ERROR_OK) {
896 LOG_ERROR("Attempt to read core registers failed.");
897 retval = ERROR_FAIL;
898 goto exit;
899 }
900 }
901 if (aux_cnt > 0) {
902 retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
903 if (retval != ERROR_OK) {
904 LOG_ERROR("Attempt to read aux registers failed.");
905 retval = ERROR_FAIL;
906 goto exit;
907 }
908 }
909
910 /* Parse core regs */
911 core_cnt = 0;
912 for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
913 struct reg *reg = reg_list + i;
914 struct arc_reg_desc *arc_reg = reg->arch_info;
915 if (!reg->valid && reg->exist) {
916 target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
917 reg->valid = true;
918 reg->dirty = false;
919 LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
920 i, arc_reg->name, core_values[core_cnt]);
921 core_cnt++;
922 }
923 }
924
925 /* Parse aux regs */
926 aux_cnt = 0;
927 for (i = arc->num_core_regs; i < regs_to_scan; i++) {
928 struct reg *reg = reg_list + i;
929 struct arc_reg_desc *arc_reg = reg->arch_info;
930 if (!reg->valid && reg->exist) {
931 target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
932 reg->valid = true;
933 reg->dirty = false;
934 LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
935 i, arc_reg->name, aux_values[aux_cnt]);
936 aux_cnt++;
937 }
938 }
939
940 exit:
941 free(core_values);
942 free(core_addrs);
943 free(aux_values);
944 free(aux_addrs);
945
946 return retval;
947 }
948
949 /**
950 * Finds an actionpoint that triggered last actionpoint event, as specified by
951 * DEBUG.ASR.
952 *
953 * @param target
954 * @param actionpoint Pointer to be set to last active actionpoint. Pointer
955 * will be set to NULL if DEBUG.AH is 0.
956 */
957 static int get_current_actionpoint(struct target *target,
958 struct arc_actionpoint **actionpoint)
959 {
960 assert(target);
961 assert(actionpoint);
962
963 uint32_t debug_ah;
964 /* Check if actionpoint caused halt */
965 CHECK_RETVAL(arc_reg_get_field(target, "debug", "ah",
966 &debug_ah));
967
968 if (debug_ah) {
969 struct arc_common *arc = target_to_arc(target);
970 unsigned int ap;
971 uint32_t debug_asr;
972 CHECK_RETVAL(arc_reg_get_field(target, "debug",
973 "asr", &debug_asr));
974
975 for (ap = 0; debug_asr > 1; debug_asr >>= 1)
976 ap += 1;
977
978 assert(ap < arc->actionpoints_num);
979
980 *actionpoint = &(arc->actionpoints_list[ap]);
981 } else {
982 *actionpoint = NULL;
983 }
984
985 return ERROR_OK;
986 }
987
988 static int arc_examine_debug_reason(struct target *target)
989 {
990 uint32_t debug_bh;
991
992 /* Only check for reason if don't know it already. */
993 /* BTW After singlestep at this point core is not marked as halted, so
994 * reading from memory to get current instruction wouldn't work anyway. */
995 if (target->debug_reason == DBG_REASON_DBGRQ ||
996 target->debug_reason == DBG_REASON_SINGLESTEP) {
997 return ERROR_OK;
998 }
999
1000 CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
1001 &debug_bh));
1002
1003 if (debug_bh) {
1004 /* DEBUG.BH is set if core halted due to BRK instruction. */
1005 target->debug_reason = DBG_REASON_BREAKPOINT;
1006 } else {
1007 struct arc_actionpoint *actionpoint = NULL;
1008 CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
1009
1010 if (actionpoint) {
1011 if (!actionpoint->used)
1012 LOG_WARNING("Target halted by an unused actionpoint.");
1013
1014 if (actionpoint->type == ARC_AP_BREAKPOINT)
1015 target->debug_reason = DBG_REASON_BREAKPOINT;
1016 else if (actionpoint->type == ARC_AP_WATCHPOINT)
1017 target->debug_reason = DBG_REASON_WATCHPOINT;
1018 else
1019 LOG_WARNING("Unknown type of actionpoint.");
1020 }
1021 }
1022
1023 return ERROR_OK;
1024 }
1025
1026 static int arc_debug_entry(struct target *target)
1027 {
1028 CHECK_RETVAL(arc_save_context(target));
1029
1030 /* TODO: reset internal indicators of caches states, otherwise D$/I$
1031 * will not be flushed/invalidated when required. */
1032 CHECK_RETVAL(arc_reset_caches_states(target));
1033 CHECK_RETVAL(arc_examine_debug_reason(target));
1034
1035 return ERROR_OK;
1036 }
1037
1038 static int arc_poll(struct target *target)
1039 {
1040 uint32_t status, value;
1041 struct arc_common *arc = target_to_arc(target);
1042
1043 /* gdb calls continuously through this arc_poll() function */
1044 CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
1045
1046 /* check for processor halted */
1047 if (status & ARC_JTAG_STAT_RU) {
1048 if (target->state != TARGET_RUNNING) {
1049 LOG_WARNING("target is still running!");
1050 target->state = TARGET_RUNNING;
1051 }
1052 return ERROR_OK;
1053 }
1054 /* In some cases JTAG status register indicates that
1055 * processor is in halt mode, but processor is still running.
1056 * We check halt bit of AUX STATUS32 register for setting correct state. */
1057 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
1058 CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
1059 if (value & AUX_STATUS32_REG_HALT_BIT) {
1060 LOG_DEBUG("ARC core in halt or reset state.");
1061 /* Save context if target was not in reset state */
1062 if (target->state == TARGET_RUNNING)
1063 CHECK_RETVAL(arc_debug_entry(target));
1064 target->state = TARGET_HALTED;
1065 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1066 } else {
1067 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
1068 "target is still running");
1069 }
1070
1071 } else if (target->state == TARGET_DEBUG_RUNNING) {
1072
1073 target->state = TARGET_HALTED;
1074 LOG_DEBUG("ARC core is in debug running mode");
1075
1076 CHECK_RETVAL(arc_debug_entry(target));
1077
1078 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
1079 }
1080
1081 return ERROR_OK;
1082 }
1083
1084 static int arc_assert_reset(struct target *target)
1085 {
1086 struct arc_common *arc = target_to_arc(target);
1087 enum reset_types jtag_reset_config = jtag_get_reset_config();
1088 bool srst_asserted = false;
1089
1090 LOG_DEBUG("target->state: %s", target_state_name(target));
1091
1092 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1093 /* allow scripts to override the reset event */
1094
1095 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1096 register_cache_invalidate(arc->core_and_aux_cache);
1097 /* An ARC target might be in halt state after reset, so
1098 * if script requested processor to resume, then it must
1099 * be manually started to ensure that this request
1100 * is satisfied. */
1101 if (target->state == TARGET_HALTED && !target->reset_halt) {
1102 /* Resume the target and continue from the current
1103 * PC register value. */
1104 LOG_DEBUG("Starting CPU execution after reset");
1105 CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
1106 }
1107 target->state = TARGET_RESET;
1108
1109 return ERROR_OK;
1110 }
1111
1112 /* some cores support connecting while srst is asserted
1113 * use that mode if it has been configured */
1114 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
1115 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1116 jtag_add_reset(0, 1);
1117 srst_asserted = true;
1118 }
1119
1120 if (jtag_reset_config & RESET_HAS_SRST) {
1121 /* should issue a srst only, but we may have to assert trst as well */
1122 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1123 jtag_add_reset(1, 1);
1124 else if (!srst_asserted)
1125 jtag_add_reset(0, 1);
1126 }
1127
1128 target->state = TARGET_RESET;
1129 jtag_add_sleep(50000);
1130
1131 register_cache_invalidate(arc->core_and_aux_cache);
1132
1133 if (target->reset_halt)
1134 CHECK_RETVAL(target_halt(target));
1135
1136 return ERROR_OK;
1137 }
1138
1139 static int arc_deassert_reset(struct target *target)
1140 {
1141 LOG_DEBUG("target->state: %s", target_state_name(target));
1142
1143 /* deassert reset lines */
1144 jtag_add_reset(0, 0);
1145
1146 return ERROR_OK;
1147 }
1148
1149 static int arc_arch_state(struct target *target)
1150 {
1151 uint32_t pc_value;
1152
1153 if (debug_level < LOG_LVL_DEBUG)
1154 return ERROR_OK;
1155
1156 CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
1157
1158 LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
1159 target_state_name(target),
1160 pc_value);
1161
1162 return ERROR_OK;
1163 }
1164
1165 /**
1166 * See arc_save_context() for reason why we want to dump all regs at once.
1167 * This however means that if there are dependencies between registers they
1168 * will not be observable until target will be resumed.
1169 */
1170 static int arc_restore_context(struct target *target)
1171 {
1172 int retval = ERROR_OK;
1173 unsigned int i;
1174 struct arc_common *arc = target_to_arc(target);
1175 struct reg *reg_list = arc->core_and_aux_cache->reg_list;
1176
1177 LOG_DEBUG("Restoring registers values");
1178 assert(reg_list);
1179
1180 const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
1181 const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
1182 uint32_t *core_values = malloc(core_regs_size);
1183 uint32_t *aux_values = malloc(aux_regs_size);
1184 uint32_t *core_addrs = malloc(core_regs_size);
1185 uint32_t *aux_addrs = malloc(aux_regs_size);
1186 unsigned int core_cnt = 0;
1187 unsigned int aux_cnt = 0;
1188
1189 if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
1190 LOG_ERROR("Unable to allocate memory");
1191 retval = ERROR_FAIL;
1192 goto exit;
1193 }
1194
1195 memset(core_values, 0xff, core_regs_size);
1196 memset(core_addrs, 0xff, core_regs_size);
1197 memset(aux_values, 0xff, aux_regs_size);
1198 memset(aux_addrs, 0xff, aux_regs_size);
1199
1200 for (i = 0; i < arc->num_core_regs; i++) {
1201 struct reg *reg = &(reg_list[i]);
1202 struct arc_reg_desc *arc_reg = reg->arch_info;
1203 if (reg->valid && reg->exist && reg->dirty) {
1204 LOG_DEBUG("Will write regnum=%u", i);
1205 core_addrs[core_cnt] = arc_reg->arch_num;
1206 core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
1207 core_cnt += 1;
1208 }
1209 }
1210
1211 for (i = 0; i < arc->num_aux_regs; i++) {
1212 struct reg *reg = &(reg_list[arc->num_core_regs + i]);
1213 struct arc_reg_desc *arc_reg = reg->arch_info;
1214 if (reg->valid && reg->exist && reg->dirty) {
1215 LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
1216 aux_addrs[aux_cnt] = arc_reg->arch_num;
1217 aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
1218 aux_cnt += 1;
1219 }
1220 }
1221
1222 /* Write data to target.
1223 * Check before write, if aux and core count is greater than 0. */
1224 if (core_cnt > 0) {
1225 retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
1226 if (retval != ERROR_OK) {
1227 LOG_ERROR("Attempt to write to core registers failed.");
1228 retval = ERROR_FAIL;
1229 goto exit;
1230 }
1231 }
1232
1233 if (aux_cnt > 0) {
1234 retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
1235 if (retval != ERROR_OK) {
1236 LOG_ERROR("Attempt to write to aux registers failed.");
1237 retval = ERROR_FAIL;
1238 goto exit;
1239 }
1240 }
1241
1242 exit:
1243 free(core_values);
1244 free(core_addrs);
1245 free(aux_values);
1246 free(aux_addrs);
1247
1248 return retval;
1249 }
1250
1251 static int arc_enable_interrupts(struct target *target, int enable)
1252 {
1253 uint32_t value;
1254
1255 struct arc_common *arc = target_to_arc(target);
1256
1257 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1258
1259 if (enable) {
1260 /* enable interrupts */
1261 value |= SET_CORE_ENABLE_INTERRUPTS;
1262 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1263 LOG_DEBUG("interrupts enabled");
1264 } else {
1265 /* disable interrupts */
1266 value &= ~SET_CORE_ENABLE_INTERRUPTS;
1267 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1268 LOG_DEBUG("interrupts disabled");
1269 }
1270
1271 return ERROR_OK;
1272 }
1273
1274 static int arc_resume(struct target *target, int current, target_addr_t address,
1275 int handle_breakpoints, int debug_execution)
1276 {
1277 struct arc_common *arc = target_to_arc(target);
1278 uint32_t resume_pc = 0;
1279 uint32_t value;
1280 struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
1281
1282 LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
1283 " debug_execution:%i", current, address, handle_breakpoints, debug_execution);
1284
1285 /* We need to reset ARC cache variables so caches
1286 * would be invalidated and actual data
1287 * would be fetched from memory. */
1288 CHECK_RETVAL(arc_reset_caches_states(target));
1289
1290 if (target->state != TARGET_HALTED) {
1291 LOG_TARGET_ERROR(target, "not halted");
1292 return ERROR_TARGET_NOT_HALTED;
1293 }
1294
1295 if (!debug_execution) {
1296 /* (gdb) continue = execute until we hit break/watch-point */
1297 target_free_all_working_areas(target);
1298 CHECK_RETVAL(arc_enable_breakpoints(target));
1299 CHECK_RETVAL(arc_enable_watchpoints(target));
1300 }
1301
1302 /* current = 1: continue on current PC, otherwise continue at <address> */
1303 if (!current) {
1304 target_buffer_set_u32(target, pc->value, address);
1305 pc->dirty = true;
1306 pc->valid = true;
1307 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
1308 }
1309
1310 if (!current)
1311 resume_pc = address;
1312 else
1313 resume_pc = target_buffer_get_u32(target, pc->value);
1314
1315 CHECK_RETVAL(arc_restore_context(target));
1316
1317 LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
1318 resume_pc, pc->dirty, pc->valid);
1319
1320 /* check if GDB tells to set our PC where to continue from */
1321 if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
1322 value = target_buffer_get_u32(target, pc->value);
1323 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
1324 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
1325 }
1326
1327 /* the front-end may request us not to handle breakpoints here */
1328 if (handle_breakpoints) {
1329 /* Single step past breakpoint at current address */
1330 struct breakpoint *breakpoint = breakpoint_find(target, resume_pc);
1331 if (breakpoint) {
1332 LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
1333 breakpoint->address);
1334 CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1335 CHECK_RETVAL(arc_single_step_core(target));
1336 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
1337 }
1338 }
1339
1340 /* Restore IRQ state if not in debug_execution*/
1341 if (!debug_execution)
1342 CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
1343 else
1344 CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
1345
1346 target->debug_reason = DBG_REASON_NOTHALTED;
1347
1348 /* ready to get us going again */
1349 target->state = TARGET_RUNNING;
1350 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
1351 value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */
1352 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
1353 LOG_DEBUG("Core started to run");
1354
1355 /* registers are now invalid */
1356 register_cache_invalidate(arc->core_and_aux_cache);
1357
1358 if (!debug_execution) {
1359 target->state = TARGET_RUNNING;
1360 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
1361 LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
1362 } else {
1363 target->state = TARGET_DEBUG_RUNNING;
1364 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
1365 LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
1366 }
1367
1368 return ERROR_OK;
1369 }
1370
1371 static int arc_init_target(struct command_context *cmd_ctx, struct target *target)
1372 {
1373 CHECK_RETVAL(arc_build_reg_cache(target));
1374 CHECK_RETVAL(arc_build_bcr_reg_cache(target));
1375 target->debug_reason = DBG_REASON_DBGRQ;
1376 return ERROR_OK;
1377 }
1378
1379 static void arc_free_reg_cache(struct reg_cache *cache)
1380 {
1381 free(cache->reg_list);
1382 free(cache);
1383 }
1384
1385 static void arc_deinit_target(struct target *target)
1386 {
1387 struct arc_common *arc = target_to_arc(target);
1388
1389 LOG_DEBUG("deinitialization of target");
1390 if (arc->core_aux_cache_built)
1391 arc_free_reg_cache(arc->core_and_aux_cache);
1392 if (arc->bcr_cache_built)
1393 arc_free_reg_cache(arc->bcr_cache);
1394
1395 struct arc_reg_data_type *type, *n;
1396 struct arc_reg_desc *desc, *k;
1397
1398 /* Free arc-specific reg_data_types allocations*/
1399 list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
1400 if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
1401 free(type->reg_type_struct_field);
1402 free(type->bitfields);
1403 free(type);
1404 } else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
1405 free(type->reg_type_flags_field);
1406 free(type->bitfields);
1407 free(type);
1408 }
1409 }
1410
1411 /* Free standard_gdb_types reg_data_types allocations */
1412 type = list_first_entry(&arc->reg_data_types, struct arc_reg_data_type, list);
1413 free(type);
1414
1415 list_for_each_entry_safe(desc, k, &arc->aux_reg_descriptions, list)
1416 free_reg_desc(desc);
1417
1418 list_for_each_entry_safe(desc, k, &arc->core_reg_descriptions, list)
1419 free_reg_desc(desc);
1420
1421 list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
1422 free_reg_desc(desc);
1423
1424 free(arc->actionpoints_list);
1425 free(arc);
1426 }
1427
1428
1429 static int arc_target_create(struct target *target, Jim_Interp *interp)
1430 {
1431 struct arc_common *arc = calloc(1, sizeof(*arc));
1432
1433 if (!arc) {
1434 LOG_ERROR("Unable to allocate memory");
1435 return ERROR_FAIL;
1436 }
1437
1438 LOG_DEBUG("Entering");
1439 CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
1440
1441 return ERROR_OK;
1442 }
1443
1444 /**
1445 * Write 4-byte instruction to memory. This is like target_write_u32, however
1446 * in case of little endian ARC instructions are in middle endian format, not
1447 * little endian, so different type of conversion should be done.
1448 * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
1449 */
1450 static int arc_write_instruction_u32(struct target *target, uint32_t address,
1451 uint32_t instr)
1452 {
1453 uint8_t value_buf[4];
1454 if (!target_was_examined(target)) {
1455 LOG_ERROR("Target not examined yet");
1456 return ERROR_FAIL;
1457 }
1458
1459 LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1460 instr);
1461
1462 if (target->endianness == TARGET_LITTLE_ENDIAN)
1463 arc_h_u32_to_me(value_buf, instr);
1464 else
1465 h_u32_to_be(value_buf, instr);
1466
1467 CHECK_RETVAL(target_write_buffer(target, address, 4, value_buf));
1468
1469 return ERROR_OK;
1470 }
1471
1472 /**
1473 * Read 32-bit instruction from memory. It is like target_read_u32, however in
1474 * case of little endian ARC instructions are in middle endian format, so
1475 * different type of conversion should be done.
1476 */
1477 static int arc_read_instruction_u32(struct target *target, uint32_t address,
1478 uint32_t *value)
1479 {
1480 uint8_t value_buf[4];
1481
1482 if (!target_was_examined(target)) {
1483 LOG_ERROR("Target not examined yet");
1484 return ERROR_FAIL;
1485 }
1486
1487 *value = 0;
1488 CHECK_RETVAL(target_read_buffer(target, address, 4, value_buf));
1489
1490 if (target->endianness == TARGET_LITTLE_ENDIAN)
1491 *value = arc_me_to_h_u32(value_buf);
1492 else
1493 *value = be_to_h_u32(value_buf);
1494
1495 LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
1496 *value);
1497
1498 return ERROR_OK;
1499 }
1500
1501 /* Actionpoint mechanism allows to setup HW breakpoints
1502 * and watchpoints. Each actionpoint is controlled by
1503 * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
1504 * and AP control(AC).
1505 * This function is for setting/unsetting actionpoints:
1506 * at - actionpoint target: trigger on mem/reg access
1507 * tt - transaction type : trigger on r/w. */
1508 static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
1509 uint32_t match_value, uint32_t control_tt, uint32_t control_at)
1510 {
1511 struct arc_common *arc = target_to_arc(target);
1512
1513 if (control_tt != AP_AC_TT_DISABLE) {
1514
1515 if (arc->actionpoints_num_avail < 1) {
1516 LOG_ERROR("No free actionpoints, maximum amount is %u",
1517 arc->actionpoints_num);
1518 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1519 }
1520
1521 /* Names of register to set - 24 chars should be enough. Looks a little
1522 * bit out-of-place for C code, but makes it aligned to the bigger
1523 * concept of "ARC registers are defined in TCL" as far as possible.
1524 */
1525 char ap_amv_reg_name[24], ap_amm_reg_name[24], ap_ac_reg_name[24];
1526 snprintf(ap_amv_reg_name, 24, "ap_amv%" PRIu32, ap_num);
1527 snprintf(ap_amm_reg_name, 24, "ap_amm%" PRIu32, ap_num);
1528 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1529 CHECK_RETVAL(arc_set_register_value(target, ap_amv_reg_name,
1530 match_value));
1531 CHECK_RETVAL(arc_set_register_value(target, ap_amm_reg_name, 0));
1532 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1533 control_tt | control_at));
1534 arc->actionpoints_num_avail--;
1535 } else {
1536 char ap_ac_reg_name[24];
1537 snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
1538 CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
1539 AP_AC_TT_DISABLE));
1540 arc->actionpoints_num_avail++;
1541 }
1542
1543 return ERROR_OK;
1544 }
1545
1546 static int arc_set_breakpoint(struct target *target,
1547 struct breakpoint *breakpoint)
1548 {
1549 if (breakpoint->is_set) {
1550 LOG_WARNING("breakpoint already set");
1551 return ERROR_OK;
1552 }
1553
1554 if (breakpoint->type == BKPT_SOFT) {
1555 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1556
1557 if (breakpoint->length == 4) {
1558 uint32_t verify = 0xffffffff;
1559
1560 CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1561 breakpoint->orig_instr));
1562
1563 CHECK_RETVAL(arc_write_instruction_u32(target, breakpoint->address,
1564 ARC_SDBBP_32));
1565
1566 CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
1567
1568 if (verify != ARC_SDBBP_32) {
1569 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1570 " - check that memory is read/writable", breakpoint->address);
1571 return ERROR_FAIL;
1572 }
1573 } else if (breakpoint->length == 2) {
1574 uint16_t verify = 0xffff;
1575
1576 CHECK_RETVAL(target_read_buffer(target, breakpoint->address, breakpoint->length,
1577 breakpoint->orig_instr));
1578 CHECK_RETVAL(target_write_u16(target, breakpoint->address, ARC_SDBBP_16));
1579
1580 CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
1581 if (verify != ARC_SDBBP_16) {
1582 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1583 " - check that memory is read/writable", breakpoint->address);
1584 return ERROR_FAIL;
1585 }
1586 } else {
1587 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1588 return ERROR_COMMAND_ARGUMENT_INVALID;
1589 }
1590
1591 breakpoint->is_set = true;
1592 } else if (breakpoint->type == BKPT_HARD) {
1593 struct arc_common *arc = target_to_arc(target);
1594 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1595 unsigned int bp_num;
1596
1597 for (bp_num = 0; bp_num < arc->actionpoints_num; bp_num++) {
1598 if (!ap_list[bp_num].used)
1599 break;
1600 }
1601
1602 if (bp_num >= arc->actionpoints_num) {
1603 LOG_ERROR("No free actionpoints, maximum amount is %u",
1604 arc->actionpoints_num);
1605 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1606 }
1607
1608 int retval = arc_configure_actionpoint(target, bp_num,
1609 breakpoint->address, AP_AC_TT_READWRITE, AP_AC_AT_INST_ADDR);
1610
1611 if (retval == ERROR_OK) {
1612 breakpoint_hw_set(breakpoint, bp_num);
1613 ap_list[bp_num].used = 1;
1614 ap_list[bp_num].bp_value = breakpoint->address;
1615 ap_list[bp_num].type = ARC_AP_BREAKPOINT;
1616
1617 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
1618 breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
1619 }
1620
1621 } else {
1622 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1623 return ERROR_FAIL;
1624 }
1625
1626 return ERROR_OK;
1627 }
1628
1629 static int arc_unset_breakpoint(struct target *target,
1630 struct breakpoint *breakpoint)
1631 {
1632 int retval = ERROR_OK;
1633
1634 if (!breakpoint->is_set) {
1635 LOG_WARNING("breakpoint not set");
1636 return ERROR_OK;
1637 }
1638
1639 if (breakpoint->type == BKPT_SOFT) {
1640 /* restore original instruction (kept in target endianness) */
1641 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
1642 if (breakpoint->length == 4) {
1643 uint32_t current_instr;
1644
1645 /* check that user program has not modified breakpoint instruction */
1646 CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &current_instr));
1647
1648 if (current_instr == ARC_SDBBP_32) {
1649 retval = target_write_buffer(target, breakpoint->address,
1650 breakpoint->length, breakpoint->orig_instr);
1651 if (retval != ERROR_OK)
1652 return retval;
1653 } else {
1654 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1655 " has been overwritten outside of debugger."
1656 "Expected: @0x%x, got: @0x%" PRIx32,
1657 breakpoint->address, ARC_SDBBP_32, current_instr);
1658 }
1659 } else if (breakpoint->length == 2) {
1660 uint16_t current_instr;
1661
1662 /* check that user program has not modified breakpoint instruction */
1663 CHECK_RETVAL(target_read_u16(target, breakpoint->address, &current_instr));
1664 if (current_instr == ARC_SDBBP_16) {
1665 retval = target_write_buffer(target, breakpoint->address,
1666 breakpoint->length, breakpoint->orig_instr);
1667 if (retval != ERROR_OK)
1668 return retval;
1669 } else {
1670 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1671 " has been overwritten outside of debugger. "
1672 "Expected: 0x%04x, got: 0x%04" PRIx16,
1673 breakpoint->address, ARC_SDBBP_16, current_instr);
1674 }
1675 } else {
1676 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1677 return ERROR_COMMAND_ARGUMENT_INVALID;
1678 }
1679 breakpoint->is_set = false;
1680
1681 } else if (breakpoint->type == BKPT_HARD) {
1682 struct arc_common *arc = target_to_arc(target);
1683 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1684 unsigned int bp_num = breakpoint->number;
1685
1686 if (bp_num >= arc->actionpoints_num) {
1687 LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
1688 bp_num, breakpoint->unique_id);
1689 return ERROR_OK;
1690 }
1691
1692 retval = arc_configure_actionpoint(target, bp_num,
1693 breakpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_INST_ADDR);
1694
1695 if (retval == ERROR_OK) {
1696 breakpoint->is_set = false;
1697 ap_list[bp_num].used = 0;
1698 ap_list[bp_num].bp_value = 0;
1699
1700 LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
1701 breakpoint->unique_id, bp_num);
1702 }
1703 } else {
1704 LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1705 return ERROR_FAIL;
1706 }
1707
1708 return retval;
1709 }
1710
1711 static int arc_enable_breakpoints(struct target *target)
1712 {
1713 struct breakpoint *breakpoint = target->breakpoints;
1714
1715 /* set any pending breakpoints */
1716 while (breakpoint) {
1717 if (!breakpoint->is_set)
1718 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
1719 breakpoint = breakpoint->next;
1720 }
1721
1722 return ERROR_OK;
1723 }
1724
1725 static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1726 {
1727 if (target->state == TARGET_HALTED) {
1728 return arc_set_breakpoint(target, breakpoint);
1729
1730 } else {
1731 LOG_TARGET_ERROR(target, "not halted (add breakpoint)");
1732 return ERROR_TARGET_NOT_HALTED;
1733 }
1734 }
1735
1736 static int arc_remove_breakpoint(struct target *target,
1737 struct breakpoint *breakpoint)
1738 {
1739 if (target->state == TARGET_HALTED) {
1740 if (breakpoint->is_set)
1741 CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
1742 } else {
1743 LOG_TARGET_ERROR(target, "not halted (remove breakpoint)");
1744 return ERROR_TARGET_NOT_HALTED;
1745 }
1746
1747 return ERROR_OK;
1748 }
1749
1750 static void arc_reset_actionpoints(struct target *target)
1751 {
1752 struct arc_common *arc = target_to_arc(target);
1753 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1754 struct breakpoint *next_b;
1755 struct watchpoint *next_w;
1756
1757 while (target->breakpoints) {
1758 next_b = target->breakpoints->next;
1759 arc_remove_breakpoint(target, target->breakpoints);
1760 free(target->breakpoints->orig_instr);
1761 free(target->breakpoints);
1762 target->breakpoints = next_b;
1763 }
1764 while (target->watchpoints) {
1765 next_w = target->watchpoints->next;
1766 arc_remove_watchpoint(target, target->watchpoints);
1767 free(target->watchpoints);
1768 target->watchpoints = next_w;
1769 }
1770 for (unsigned int i = 0; i < arc->actionpoints_num; i++) {
1771 if ((ap_list[i].used) && (ap_list[i].reg_address))
1772 arc_remove_auxreg_actionpoint(target, ap_list[i].reg_address);
1773 }
1774 }
1775
1776 int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
1777 {
1778 LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
1779 struct arc_common *arc = target_to_arc(target);
1780
1781 /* Make sure that there are no enabled actionpoints in target. */
1782 arc_reset_actionpoints(target);
1783
1784 /* Assume that all points have been removed from target. */
1785 free(arc->actionpoints_list);
1786
1787 arc->actionpoints_num_avail = ap_num;
1788 arc->actionpoints_num = ap_num;
1789 /* calloc can be safely called when ncount == 0. */
1790 arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
1791
1792 if (!arc->actionpoints_list) {
1793 LOG_ERROR("Unable to allocate memory");
1794 return ERROR_FAIL;
1795 }
1796 return ERROR_OK;
1797 }
1798
1799
1800 int arc_add_auxreg_actionpoint(struct target *target,
1801 uint32_t auxreg_addr, uint32_t transaction)
1802 {
1803 unsigned int ap_num = 0;
1804 int retval = ERROR_OK;
1805
1806 if (target->state != TARGET_HALTED)
1807 return ERROR_TARGET_NOT_HALTED;
1808
1809 struct arc_common *arc = target_to_arc(target);
1810 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1811
1812 while (ap_list[ap_num].used)
1813 ap_num++;
1814
1815 if (ap_num >= arc->actionpoints_num) {
1816 LOG_ERROR("No actionpoint free, maximum amount is %u",
1817 arc->actionpoints_num);
1818 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1819 }
1820
1821 retval = arc_configure_actionpoint(target, ap_num,
1822 auxreg_addr, transaction, AP_AC_AT_AUXREG_ADDR);
1823
1824 if (retval == ERROR_OK) {
1825 ap_list[ap_num].used = 1;
1826 ap_list[ap_num].reg_address = auxreg_addr;
1827 }
1828
1829 return retval;
1830 }
1831
1832 int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
1833 {
1834 int retval = ERROR_OK;
1835 bool ap_found = false;
1836 unsigned int ap_num = 0;
1837
1838 if (target->state != TARGET_HALTED)
1839 return ERROR_TARGET_NOT_HALTED;
1840
1841 struct arc_common *arc = target_to_arc(target);
1842 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1843
1844 while ((ap_list[ap_num].used) && (ap_num < arc->actionpoints_num)) {
1845 if (ap_list[ap_num].reg_address == auxreg_addr) {
1846 ap_found = true;
1847 break;
1848 }
1849 ap_num++;
1850 }
1851
1852 if (ap_found) {
1853 retval = arc_configure_actionpoint(target, ap_num,
1854 auxreg_addr, AP_AC_TT_DISABLE, AP_AC_AT_AUXREG_ADDR);
1855
1856 if (retval == ERROR_OK) {
1857 ap_list[ap_num].used = 0;
1858 ap_list[ap_num].bp_value = 0;
1859 }
1860 } else {
1861 LOG_ERROR("Register actionpoint not found");
1862 }
1863 return retval;
1864 }
1865
1866
1867 static int arc_set_watchpoint(struct target *target,
1868 struct watchpoint *watchpoint)
1869 {
1870 unsigned int wp_num;
1871 struct arc_common *arc = target_to_arc(target);
1872 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1873
1874 if (watchpoint->is_set) {
1875 LOG_WARNING("watchpoint already set");
1876 return ERROR_OK;
1877 }
1878
1879 for (wp_num = 0; wp_num < arc->actionpoints_num; wp_num++) {
1880 if (!ap_list[wp_num].used)
1881 break;
1882 }
1883
1884 if (wp_num >= arc->actionpoints_num) {
1885 LOG_ERROR("No free actionpoints, maximum amount is %u",
1886 arc->actionpoints_num);
1887 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1888 }
1889
1890 if (watchpoint->length != 4) {
1891 LOG_ERROR("Only watchpoints of length 4 are supported");
1892 return ERROR_TARGET_UNALIGNED_ACCESS;
1893 }
1894
1895 int enable = AP_AC_TT_DISABLE;
1896 switch (watchpoint->rw) {
1897 case WPT_READ:
1898 enable = AP_AC_TT_READ;
1899 break;
1900 case WPT_WRITE:
1901 enable = AP_AC_TT_WRITE;
1902 break;
1903 case WPT_ACCESS:
1904 enable = AP_AC_TT_READWRITE;
1905 break;
1906 default:
1907 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
1908 return ERROR_FAIL;
1909 }
1910
1911 int retval = arc_configure_actionpoint(target, wp_num,
1912 watchpoint->address, enable, AP_AC_AT_MEMORY_ADDR);
1913
1914 if (retval == ERROR_OK) {
1915 watchpoint_set(watchpoint, wp_num);
1916 ap_list[wp_num].used = 1;
1917 ap_list[wp_num].bp_value = watchpoint->address;
1918 ap_list[wp_num].type = ARC_AP_WATCHPOINT;
1919
1920 LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
1921 watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
1922 }
1923
1924 return retval;
1925 }
1926
1927 static int arc_unset_watchpoint(struct target *target,
1928 struct watchpoint *watchpoint)
1929 {
1930 /* get pointers to arch-specific information */
1931 struct arc_common *arc = target_to_arc(target);
1932 struct arc_actionpoint *ap_list = arc->actionpoints_list;
1933
1934 if (!watchpoint->is_set) {
1935 LOG_WARNING("watchpoint not set");
1936 return ERROR_OK;
1937 }
1938
1939 unsigned int wp_num = watchpoint->number;
1940 if (wp_num >= arc->actionpoints_num) {
1941 LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
1942 wp_num, watchpoint->unique_id);
1943 return ERROR_OK;
1944 }
1945
1946 int retval = arc_configure_actionpoint(target, wp_num,
1947 watchpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_MEMORY_ADDR);
1948
1949 if (retval == ERROR_OK) {
1950 watchpoint->is_set = false;
1951 ap_list[wp_num].used = 0;
1952 ap_list[wp_num].bp_value = 0;
1953
1954 LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
1955 watchpoint->unique_id, wp_num);
1956 }
1957
1958 return retval;
1959 }
1960
1961 static int arc_enable_watchpoints(struct target *target)
1962 {
1963 struct watchpoint *watchpoint = target->watchpoints;
1964
1965 /* set any pending watchpoints */
1966 while (watchpoint) {
1967 if (!watchpoint->is_set)
1968 CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
1969 watchpoint = watchpoint->next;
1970 }
1971
1972 return ERROR_OK;
1973 }
1974
1975 static int arc_add_watchpoint(struct target *target,
1976 struct watchpoint *watchpoint)
1977 {
1978 if (target->state != TARGET_HALTED) {
1979 LOG_TARGET_ERROR(target, "not halted");
1980 return ERROR_TARGET_NOT_HALTED;
1981 }
1982
1983 CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
1984
1985 return ERROR_OK;
1986 }
1987
1988 static int arc_remove_watchpoint(struct target *target,
1989 struct watchpoint *watchpoint)
1990 {
1991 if (target->state != TARGET_HALTED) {
1992 LOG_TARGET_ERROR(target, "not halted");
1993 return ERROR_TARGET_NOT_HALTED;
1994 }
1995
1996 if (watchpoint->is_set)
1997 CHECK_RETVAL(arc_unset_watchpoint(target, watchpoint));
1998
1999 return ERROR_OK;
2000 }
2001
2002 static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
2003 {
2004 assert(target);
2005 assert(hit_watchpoint);
2006
2007 struct arc_actionpoint *actionpoint = NULL;
2008 CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
2009
2010 if (actionpoint) {
2011 if (!actionpoint->used)
2012 LOG_WARNING("Target halted by unused actionpoint.");
2013
2014 /* If this check fails - that is some sort of an error in OpenOCD. */
2015 if (actionpoint->type != ARC_AP_WATCHPOINT)
2016 LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
2017
2018 for (struct watchpoint *watchpoint = target->watchpoints;
2019 watchpoint;
2020 watchpoint = watchpoint->next) {
2021 if (actionpoint->bp_value == watchpoint->address) {
2022 *hit_watchpoint = watchpoint;
2023 LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
2024 watchpoint->unique_id, watchpoint->number);
2025 return ERROR_OK;
2026 }
2027 }
2028 }
2029
2030 return ERROR_FAIL;
2031 }
2032
2033 /* Helper function which switches core to single_step mode by
2034 * doing aux r/w operations. */
2035 static int arc_config_step(struct target *target, int enable_step)
2036 {
2037 uint32_t value;
2038
2039 struct arc_common *arc = target_to_arc(target);
2040
2041 /* enable core debug step mode */
2042 if (enable_step) {
2043 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
2044 &value));
2045 value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
2046 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
2047 value));
2048 LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
2049
2050 /* Doing read-modify-write, because DEBUG might contain manually set
2051 * bits like UB or ED, which should be preserved. */
2052 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info,
2053 AUX_DEBUG_REG, &value));
2054 value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
2055 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
2056 value));
2057 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
2058
2059 } else { /* disable core debug step mode */
2060 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
2061 &value));
2062 value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
2063 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
2064 value));
2065 LOG_DEBUG("core debug step mode disabled");
2066 }
2067
2068 return ERROR_OK;
2069 }
2070
2071 static int arc_single_step_core(struct target *target)
2072 {
2073 CHECK_RETVAL(arc_debug_entry(target));
2074
2075 /* disable interrupts while stepping */
2076 CHECK_RETVAL(arc_enable_interrupts(target, 0));
2077
2078 /* configure single step mode */
2079 CHECK_RETVAL(arc_config_step(target, 1));
2080
2081 /* exit debug mode */
2082 CHECK_RETVAL(arc_exit_debug(target));
2083
2084 return ERROR_OK;
2085 }
2086
2087 static int arc_step(struct target *target, int current, target_addr_t address,
2088 int handle_breakpoints)
2089 {
2090 /* get pointers to arch-specific information */
2091 struct arc_common *arc = target_to_arc(target);
2092 struct breakpoint *breakpoint = NULL;
2093 struct reg *pc = &(arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache]);
2094
2095 if (target->state != TARGET_HALTED) {
2096 LOG_TARGET_ERROR(target, "not halted");
2097 return ERROR_TARGET_NOT_HALTED;
2098 }
2099
2100 /* current = 1: continue on current pc, otherwise continue at <address> */
2101 if (!current) {
2102 buf_set_u32(pc->value, 0, 32, address);
2103 pc->dirty = true;
2104 pc->valid = true;
2105 }
2106
2107 LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
2108 buf_get_u32(pc->value, 0, 32));
2109
2110 /* the front-end may request us not to handle breakpoints */
2111 if (handle_breakpoints) {
2112 breakpoint = breakpoint_find(target, buf_get_u32(pc->value, 0, 32));
2113 if (breakpoint)
2114 CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
2115 }
2116
2117 /* restore context */
2118 CHECK_RETVAL(arc_restore_context(target));
2119
2120 target->debug_reason = DBG_REASON_SINGLESTEP;
2121
2122 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
2123
2124 /* disable interrupts while stepping */
2125 CHECK_RETVAL(arc_enable_interrupts(target, 0));
2126
2127 /* do a single step */
2128 CHECK_RETVAL(arc_config_step(target, 1));
2129
2130 /* make sure we done our step */
2131 alive_sleep(1);
2132
2133 /* registers are now invalid */
2134 register_cache_invalidate(arc->core_and_aux_cache);
2135
2136 if (breakpoint)
2137 CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
2138
2139 LOG_DEBUG("target stepped ");
2140
2141 target->state = TARGET_HALTED;
2142
2143 /* Saving context */
2144 CHECK_RETVAL(arc_debug_entry(target));
2145 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
2146
2147 return ERROR_OK;
2148 }
2149
2150
2151 /* This function invalidates icache. */
2152 static int arc_icache_invalidate(struct target *target)
2153 {
2154 uint32_t value;
2155
2156 struct arc_common *arc = target_to_arc(target);
2157
2158 /* Don't waste time if already done. */
2159 if (!arc->has_icache || arc->icache_invalidated)
2160 return ERROR_OK;
2161
2162 LOG_DEBUG("Invalidating I$.");
2163
2164 value = IC_IVIC_INVALIDATE; /* invalidate I$ */
2165 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
2166
2167 arc->icache_invalidated = true;
2168
2169 return ERROR_OK;
2170 }
2171
2172 /* This function invalidates dcache */
2173 static int arc_dcache_invalidate(struct target *target)
2174 {
2175 uint32_t value, dc_ctrl_value;
2176
2177 struct arc_common *arc = target_to_arc(target);
2178
2179 if (!arc->has_dcache || arc->dcache_invalidated)
2180 return ERROR_OK;
2181
2182 LOG_DEBUG("Invalidating D$.");
2183
2184 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
2185 dc_ctrl_value = value;
2186 value &= ~DC_CTRL_IM;
2187
2188 /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
2189 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2190 value = DC_IVDC_INVALIDATE; /* invalidate D$ */
2191 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2192
2193 /* restore DC_CTRL invalidate mode */
2194 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2195
2196 arc->dcache_invalidated = true;
2197
2198 return ERROR_OK;
2199 }
2200
2201 /* This function invalidates l2 cache. */
2202 static int arc_l2cache_invalidate(struct target *target)
2203 {
2204 uint32_t value, slc_ctrl_value;
2205
2206 struct arc_common *arc = target_to_arc(target);
2207
2208 if (!arc->has_l2cache || arc->l2cache_invalidated)
2209 return ERROR_OK;
2210
2211 LOG_DEBUG("Invalidating L2$.");
2212
2213 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2214 slc_ctrl_value = value;
2215 value &= ~L2_CTRL_IM;
2216
2217 /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
2218 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
2219 /* invalidate L2$ */
2220 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
2221
2222 /* Wait until invalidate operation ends */
2223 do {
2224 LOG_DEBUG("Waiting for invalidation end.");
2225 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2226 } while (value & L2_CTRL_BS);
2227
2228 /* restore L2_CTRL invalidate mode */
2229 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
2230
2231 arc->l2cache_invalidated = true;
2232
2233 return ERROR_OK;
2234 }
2235
2236
2237 int arc_cache_invalidate(struct target *target)
2238 {
2239 CHECK_RETVAL(arc_icache_invalidate(target));
2240 CHECK_RETVAL(arc_dcache_invalidate(target));
2241 CHECK_RETVAL(arc_l2cache_invalidate(target));
2242
2243 return ERROR_OK;
2244 }
2245
2246 /* Flush data cache. This function is cheap to call and return quickly if D$
2247 * already has been flushed since target had been halted. JTAG debugger reads
2248 * values directly from memory, bypassing cache, so if there are unflushed
2249 * lines debugger will read invalid values, which will cause a lot of troubles.
2250 * */
2251 static int arc_dcache_flush(struct target *target)
2252 {
2253 uint32_t value, dc_ctrl_value;
2254 bool has_to_set_dc_ctrl_im;
2255
2256 struct arc_common *arc = target_to_arc(target);
2257
2258 /* Don't waste time if already done. */
2259 if (!arc->has_dcache || arc->dcache_flushed)
2260 return ERROR_OK;
2261
2262 LOG_DEBUG("Flushing D$.");
2263
2264 /* Store current value of DC_CTRL */
2265 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
2266
2267 /* Set DC_CTRL invalidate mode to flush (if not already set) */
2268 has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
2269 if (has_to_set_dc_ctrl_im) {
2270 value = dc_ctrl_value | DC_CTRL_IM;
2271 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
2272 }
2273
2274 /* Flush D$ */
2275 value = DC_IVDC_INVALIDATE;
2276 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
2277
2278 /* Restore DC_CTRL invalidate mode (even of flush failed) */
2279 if (has_to_set_dc_ctrl_im)
2280 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
2281
2282 arc->dcache_flushed = true;
2283
2284 return ERROR_OK;
2285 }
2286
2287 /* This function flushes l2cache. */
2288 static int arc_l2cache_flush(struct target *target)
2289 {
2290 uint32_t value;
2291
2292 struct arc_common *arc = target_to_arc(target);
2293
2294 /* Don't waste time if already done. */
2295 if (!arc->has_l2cache || arc->l2cache_flushed)
2296 return ERROR_OK;
2297
2298 LOG_DEBUG("Flushing L2$.");
2299
2300 /* Flush L2 cache */
2301 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
2302
2303 /* Wait until flush operation ends */
2304 do {
2305 LOG_DEBUG("Waiting for flushing end.");
2306 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
2307 } while (value & L2_CTRL_BS);
2308
2309 arc->l2cache_flushed = true;
2310
2311 return ERROR_OK;
2312 }
2313
2314 int arc_cache_flush(struct target *target)
2315 {
2316 CHECK_RETVAL(arc_dcache_flush(target));
2317 CHECK_RETVAL(arc_l2cache_flush(target));
2318
2319 return ERROR_OK;
2320 }
2321
2322 /* ARC v2 target */
2323 struct target_type arcv2_target = {
2324 .name = "arcv2",
2325
2326 .poll = arc_poll,
2327
2328 .arch_state = arc_arch_state,
2329
2330 /* TODO That seems like something similar to metaware hostlink, so perhaps
2331 * we can exploit this in the future. */
2332 .target_request_data = NULL,
2333
2334 .halt = arc_halt,
2335 .resume = arc_resume,
2336 .step = arc_step,
2337
2338 .assert_reset = arc_assert_reset,
2339 .deassert_reset = arc_deassert_reset,
2340
2341 /* TODO Implement soft_reset_halt */
2342 .soft_reset_halt = NULL,
2343
2344 .get_gdb_reg_list = arc_get_gdb_reg_list,
2345
2346 .read_memory = arc_mem_read,
2347 .write_memory = arc_mem_write,
2348 .checksum_memory = NULL,
2349 .blank_check_memory = NULL,
2350
2351 .add_breakpoint = arc_add_breakpoint,
2352 .add_context_breakpoint = NULL,
2353 .add_hybrid_breakpoint = NULL,
2354 .remove_breakpoint = arc_remove_breakpoint,
2355 .add_watchpoint = arc_add_watchpoint,
2356 .remove_watchpoint = arc_remove_watchpoint,
2357 .hit_watchpoint = arc_hit_watchpoint,
2358
2359 .run_algorithm = NULL,
2360 .start_algorithm = NULL,
2361 .wait_algorithm = NULL,
2362
2363 .commands = arc_monitor_command_handlers,
2364
2365 .target_create = arc_target_create,
2366 .init_target = arc_init_target,
2367 .deinit_target = arc_deinit_target,
2368 .examine = arc_examine,
2369
2370 .virt2phys = NULL,
2371 .read_phys_memory = NULL,
2372 .write_phys_memory = NULL,
2373 .mmu = NULL,
2374 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)