1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include <jtag/interface.h>
36 static uint8_t output_value
;
37 static int dev_mem_fd
;
38 static void *gpio_controller
;
39 static volatile uint8_t *gpio_data_register
;
40 static volatile uint8_t *gpio_data_direction_register
;
42 /* low level command set
44 static bb_value_t
ep93xx_read(void);
45 static int ep93xx_write(int tck
, int tms
, int tdi
);
46 static int ep93xx_reset(int trst
, int srst
);
48 static int ep93xx_init(void);
49 static int ep93xx_quit(void);
51 struct timespec ep93xx_zzzz
;
53 struct jtag_interface ep93xx_interface
= {
56 .supported
= DEBUG_CAP_TMS_SEQ
,
57 .execute_queue
= bitbang_execute_queue
,
63 static struct bitbang_interface ep93xx_bitbang
= {
65 .write
= ep93xx_write
,
66 .reset
= ep93xx_reset
,
70 static bb_value_t
ep93xx_read(void)
72 return (*gpio_data_register
& TDO_BIT
) ? BB_HIGH
: BB_LOW
;
75 static int ep93xx_write(int tck
, int tms
, int tdi
)
78 output_value
|= TCK_BIT
;
80 output_value
&= ~TCK_BIT
;
83 output_value
|= TMS_BIT
;
85 output_value
&= ~TMS_BIT
;
88 output_value
|= TDI_BIT
;
90 output_value
&= ~TDI_BIT
;
92 *gpio_data_register
= output_value
;
93 nanosleep(&ep93xx_zzzz
, NULL
);
98 /* (1) assert or (0) deassert reset lines */
99 static int ep93xx_reset(int trst
, int srst
)
102 output_value
|= TRST_BIT
;
104 output_value
&= ~TRST_BIT
;
107 output_value
|= SRST_BIT
;
109 output_value
&= ~SRST_BIT
;
111 *gpio_data_register
= output_value
;
112 nanosleep(&ep93xx_zzzz
, NULL
);
117 static int set_gonk_mode(void)
122 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
123 MAP_SHARED
, dev_mem_fd
, 0x80930000);
124 if (syscon
== MAP_FAILED
) {
126 return ERROR_JTAG_INIT_FAILED
;
129 devicecfg
= *((volatile int *)(syscon
+ 0x80));
130 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
131 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
133 munmap(syscon
, 4096);
138 static int ep93xx_init(void)
142 bitbang_interface
= &ep93xx_bitbang
;
144 ep93xx_zzzz
.tv_sec
= 0;
145 ep93xx_zzzz
.tv_nsec
= 10000000;
147 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
148 if (dev_mem_fd
< 0) {
150 return ERROR_JTAG_INIT_FAILED
;
153 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
154 MAP_SHARED
, dev_mem_fd
, 0x80840000);
155 if (gpio_controller
== MAP_FAILED
) {
158 return ERROR_JTAG_INIT_FAILED
;
161 ret
= set_gonk_mode();
162 if (ret
!= ERROR_OK
) {
163 munmap(gpio_controller
, 4096);
169 /* Use GPIO port A. */
170 gpio_data_register
= gpio_controller
+ 0x00;
171 gpio_data_direction_register
= gpio_controller
+ 0x10;
174 /* Use GPIO port B. */
175 gpio_data_register
= gpio_controller
+ 0x04;
176 gpio_data_direction_register
= gpio_controller
+ 0x14;
178 /* Use GPIO port C. */
179 gpio_data_register
= gpio_controller
+ 0x08;
180 gpio_data_direction_register
= gpio_controller
+ 0x18;
182 /* Use GPIO port D. */
183 gpio_data_register
= gpio_controller
+ 0x0c;
184 gpio_data_direction_register
= gpio_controller
+ 0x1c;
187 /* Use GPIO port C. */
188 gpio_data_register
= gpio_controller
+ 0x08;
189 gpio_data_direction_register
= gpio_controller
+ 0x18;
191 LOG_INFO("gpio_data_register = %p", gpio_data_register
);
192 LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register
);
194 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
195 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
196 * TMS/TRST/SRST high.
198 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
199 *gpio_data_register
= output_value
;
200 nanosleep(&ep93xx_zzzz
, NULL
);
203 * Configure the direction register. 1 = output, 0 = input.
205 *gpio_data_direction_register
=
206 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
208 nanosleep(&ep93xx_zzzz
, NULL
);
212 static int ep93xx_quit(void)
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