1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
22 #include <jtag/drivers/libusb_common.h>
23 #include <helper/log.h>
24 #include <helper/time_support.h>
25 #include <target/target.h>
26 #include <jtag/jtag.h>
27 #include <target/nds32_insn.h>
28 #include <target/nds32_reg.h>
32 /* Global USB buffers */
33 static uint8_t usb_in_buffer
[AICE_IN_BUFFER_SIZE
];
34 static uint8_t usb_out_buffer
[AICE_OUT_BUFFER_SIZE
];
35 static uint32_t jtag_clock
;
36 static struct aice_usb_handler_s aice_handler
;
37 /* AICE max retry times. If AICE command timeout, retry it. */
38 static int aice_max_retry_times
= 50;
39 /* Default endian is little endian. */
40 static enum aice_target_endian data_endian
;
42 /* Constants for AICE command format length */
43 static const int32_t AICE_FORMAT_HTDA
= 3;
44 static const int32_t AICE_FORMAT_HTDC
= 7;
45 static const int32_t AICE_FORMAT_HTDMA
= 4;
46 static const int32_t AICE_FORMAT_HTDMB
= 8;
47 static const int32_t AICE_FORMAT_HTDMC
= 8;
48 static const int32_t AICE_FORMAT_HTDMD
= 12;
49 static const int32_t AICE_FORMAT_DTHA
= 6;
50 static const int32_t AICE_FORMAT_DTHB
= 2;
51 static const int32_t AICE_FORMAT_DTHMA
= 8;
52 static const int32_t AICE_FORMAT_DTHMB
= 4;
54 /* Constants for AICE command */
55 static const uint8_t AICE_CMD_SCAN_CHAIN
= 0x00;
56 static const uint8_t AICE_CMD_T_READ_MISC
= 0x20;
57 static const uint8_t AICE_CMD_T_READ_EDMSR
= 0x21;
58 static const uint8_t AICE_CMD_T_READ_DTR
= 0x22;
59 static const uint8_t AICE_CMD_T_READ_MEM_B
= 0x24;
60 static const uint8_t AICE_CMD_T_READ_MEM_H
= 0x25;
61 static const uint8_t AICE_CMD_T_READ_MEM
= 0x26;
62 static const uint8_t AICE_CMD_T_FASTREAD_MEM
= 0x27;
63 static const uint8_t AICE_CMD_T_WRITE_MISC
= 0x28;
64 static const uint8_t AICE_CMD_T_WRITE_EDMSR
= 0x29;
65 static const uint8_t AICE_CMD_T_WRITE_DTR
= 0x2A;
66 static const uint8_t AICE_CMD_T_WRITE_DIM
= 0x2B;
67 static const uint8_t AICE_CMD_T_WRITE_MEM_B
= 0x2C;
68 static const uint8_t AICE_CMD_T_WRITE_MEM_H
= 0x2D;
69 static const uint8_t AICE_CMD_T_WRITE_MEM
= 0x2E;
70 static const uint8_t AICE_CMD_T_FASTWRITE_MEM
= 0x2F;
71 static const uint8_t AICE_CMD_T_EXECUTE
= 0x3E;
72 static const uint8_t AICE_CMD_READ_CTRL
= 0x50;
73 static const uint8_t AICE_CMD_WRITE_CTRL
= 0x51;
74 static const uint8_t AICE_CMD_BATCH_BUFFER_READ
= 0x60;
75 static const uint8_t AICE_CMD_READ_DTR_TO_BUFFER
= 0x61;
76 static const uint8_t AICE_CMD_BATCH_BUFFER_WRITE
= 0x68;
77 static const uint8_t AICE_CMD_WRITE_DTR_FROM_BUFFER
= 0x69;
79 /***************************************************************************/
80 /* AICE commands' pack/unpack functions */
81 static void aice_pack_htda(uint8_t cmd_code
, uint8_t extra_word_length
,
84 usb_out_buffer
[0] = cmd_code
;
85 usb_out_buffer
[1] = extra_word_length
;
86 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
89 static void aice_pack_htdc(uint8_t cmd_code
, uint8_t extra_word_length
,
90 uint32_t address
, uint32_t word
, enum aice_target_endian access_endian
)
92 usb_out_buffer
[0] = cmd_code
;
93 usb_out_buffer
[1] = extra_word_length
;
94 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
95 if (access_endian
== AICE_BIG_ENDIAN
) {
96 usb_out_buffer
[6] = (uint8_t)((word
>> 24) & 0xFF);
97 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
98 usb_out_buffer
[4] = (uint8_t)((word
>> 8) & 0xFF);
99 usb_out_buffer
[3] = (uint8_t)(word
& 0xFF);
101 usb_out_buffer
[3] = (uint8_t)((word
>> 24) & 0xFF);
102 usb_out_buffer
[4] = (uint8_t)((word
>> 16) & 0xFF);
103 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
104 usb_out_buffer
[6] = (uint8_t)(word
& 0xFF);
108 static void aice_pack_htdma(uint8_t cmd_code
, uint8_t target_id
,
109 uint8_t extra_word_length
, uint32_t address
)
111 usb_out_buffer
[0] = cmd_code
;
112 usb_out_buffer
[1] = target_id
;
113 usb_out_buffer
[2] = extra_word_length
;
114 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
117 static void aice_pack_htdmb(uint8_t cmd_code
, uint8_t target_id
,
118 uint8_t extra_word_length
, uint32_t address
)
120 usb_out_buffer
[0] = cmd_code
;
121 usb_out_buffer
[1] = target_id
;
122 usb_out_buffer
[2] = extra_word_length
;
123 usb_out_buffer
[3] = 0;
124 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
125 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
126 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
127 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
130 static void aice_pack_htdmc(uint8_t cmd_code
, uint8_t target_id
,
131 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
132 enum aice_target_endian access_endian
)
134 usb_out_buffer
[0] = cmd_code
;
135 usb_out_buffer
[1] = target_id
;
136 usb_out_buffer
[2] = extra_word_length
;
137 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
138 if (access_endian
== AICE_BIG_ENDIAN
) {
139 usb_out_buffer
[7] = (uint8_t)((word
>> 24) & 0xFF);
140 usb_out_buffer
[6] = (uint8_t)((word
>> 16) & 0xFF);
141 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
142 usb_out_buffer
[4] = (uint8_t)(word
& 0xFF);
144 usb_out_buffer
[4] = (uint8_t)((word
>> 24) & 0xFF);
145 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
146 usb_out_buffer
[6] = (uint8_t)((word
>> 8) & 0xFF);
147 usb_out_buffer
[7] = (uint8_t)(word
& 0xFF);
151 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
152 uint8_t extra_word_length
, uint32_t address
, uint32_t *word
,
153 uint8_t num_of_words
, enum aice_target_endian access_endian
)
155 usb_out_buffer
[0] = cmd_code
;
156 usb_out_buffer
[1] = target_id
;
157 usb_out_buffer
[2] = extra_word_length
;
158 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
161 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
162 if (access_endian
== AICE_BIG_ENDIAN
) {
163 usb_out_buffer
[7 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
164 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
165 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
166 usb_out_buffer
[4 + i
* 4] = (uint8_t)(*word
& 0xFF);
168 usb_out_buffer
[4 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
169 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
170 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
171 usb_out_buffer
[7 + i
* 4] = (uint8_t)(*word
& 0xFF);
176 static void aice_pack_htdmd(uint8_t cmd_code
, uint8_t target_id
,
177 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
178 enum aice_target_endian access_endian
)
180 usb_out_buffer
[0] = cmd_code
;
181 usb_out_buffer
[1] = target_id
;
182 usb_out_buffer
[2] = extra_word_length
;
183 usb_out_buffer
[3] = 0;
184 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
185 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
186 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
187 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
188 if (access_endian
== AICE_BIG_ENDIAN
) {
189 usb_out_buffer
[11] = (uint8_t)((word
>> 24) & 0xFF);
190 usb_out_buffer
[10] = (uint8_t)((word
>> 16) & 0xFF);
191 usb_out_buffer
[9] = (uint8_t)((word
>> 8) & 0xFF);
192 usb_out_buffer
[8] = (uint8_t)(word
& 0xFF);
194 usb_out_buffer
[8] = (uint8_t)((word
>> 24) & 0xFF);
195 usb_out_buffer
[9] = (uint8_t)((word
>> 16) & 0xFF);
196 usb_out_buffer
[10] = (uint8_t)((word
>> 8) & 0xFF);
197 usb_out_buffer
[11] = (uint8_t)(word
& 0xFF);
201 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
202 uint8_t extra_word_length
, uint32_t address
, const uint8_t *word
,
203 enum aice_target_endian access_endian
)
205 usb_out_buffer
[0] = cmd_code
;
206 usb_out_buffer
[1] = target_id
;
207 usb_out_buffer
[2] = extra_word_length
;
208 usb_out_buffer
[3] = 0;
209 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
210 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
211 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
212 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
215 /* num_of_words may be over 0xFF, so use uint32_t */
216 uint32_t num_of_words
= extra_word_length
+ 1;
218 for (i
= 0 ; i
< num_of_words
; i
++, word
+= 4) {
219 if (access_endian
== AICE_BIG_ENDIAN
) {
220 usb_out_buffer
[11 + i
* 4] = word
[3];
221 usb_out_buffer
[10 + i
* 4] = word
[2];
222 usb_out_buffer
[9 + i
* 4] = word
[1];
223 usb_out_buffer
[8 + i
* 4] = word
[0];
225 usb_out_buffer
[8 + i
* 4] = word
[3];
226 usb_out_buffer
[9 + i
* 4] = word
[2];
227 usb_out_buffer
[10 + i
* 4] = word
[1];
228 usb_out_buffer
[11 + i
* 4] = word
[0];
233 static void aice_unpack_dtha(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
,
234 uint32_t *word
, enum aice_target_endian access_endian
)
236 *cmd_ack_code
= usb_in_buffer
[0];
237 *extra_word_length
= usb_in_buffer
[1];
239 if (access_endian
== AICE_BIG_ENDIAN
) {
240 *word
= (usb_in_buffer
[5] << 24) |
241 (usb_in_buffer
[4] << 16) |
242 (usb_in_buffer
[3] << 8) |
245 *word
= (usb_in_buffer
[2] << 24) |
246 (usb_in_buffer
[3] << 16) |
247 (usb_in_buffer
[4] << 8) |
252 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code
,
253 uint8_t *extra_word_length
, uint32_t *word
, uint8_t num_of_words
,
254 enum aice_target_endian access_endian
)
256 *cmd_ack_code
= usb_in_buffer
[0];
257 *extra_word_length
= usb_in_buffer
[1];
260 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
261 if (access_endian
== AICE_BIG_ENDIAN
) {
262 *word
= (usb_in_buffer
[5 + i
* 4] << 24) |
263 (usb_in_buffer
[4 + i
* 4] << 16) |
264 (usb_in_buffer
[3 + i
* 4] << 8) |
265 (usb_in_buffer
[2 + i
* 4]);
267 *word
= (usb_in_buffer
[2 + i
* 4] << 24) |
268 (usb_in_buffer
[3 + i
* 4] << 16) |
269 (usb_in_buffer
[4 + i
* 4] << 8) |
270 (usb_in_buffer
[5 + i
* 4]);
275 static void aice_unpack_dthb(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
)
277 *cmd_ack_code
= usb_in_buffer
[0];
278 *extra_word_length
= usb_in_buffer
[1];
281 static void aice_unpack_dthma(uint8_t *cmd_ack_code
, uint8_t *target_id
,
282 uint8_t *extra_word_length
, uint32_t *word
,
283 enum aice_target_endian access_endian
)
285 *cmd_ack_code
= usb_in_buffer
[0];
286 *target_id
= usb_in_buffer
[1];
287 *extra_word_length
= usb_in_buffer
[2];
288 if (access_endian
== AICE_BIG_ENDIAN
) {
289 *word
= (usb_in_buffer
[7] << 24) |
290 (usb_in_buffer
[6] << 16) |
291 (usb_in_buffer
[5] << 8) |
294 *word
= (usb_in_buffer
[4] << 24) |
295 (usb_in_buffer
[5] << 16) |
296 (usb_in_buffer
[6] << 8) |
301 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code
,
302 uint8_t *target_id
, uint8_t *extra_word_length
, uint8_t *word
,
303 enum aice_target_endian access_endian
)
305 *cmd_ack_code
= usb_in_buffer
[0];
306 *target_id
= usb_in_buffer
[1];
307 *extra_word_length
= usb_in_buffer
[2];
308 if (access_endian
== AICE_BIG_ENDIAN
) {
309 word
[0] = usb_in_buffer
[4];
310 word
[1] = usb_in_buffer
[5];
311 word
[2] = usb_in_buffer
[6];
312 word
[3] = usb_in_buffer
[7];
314 word
[0] = usb_in_buffer
[7];
315 word
[1] = usb_in_buffer
[6];
316 word
[2] = usb_in_buffer
[5];
317 word
[3] = usb_in_buffer
[4];
322 for (i
= 0; i
< *extra_word_length
; i
++) {
323 if (access_endian
== AICE_BIG_ENDIAN
) {
324 word
[0] = usb_in_buffer
[8 + i
* 4];
325 word
[1] = usb_in_buffer
[9 + i
* 4];
326 word
[2] = usb_in_buffer
[10 + i
* 4];
327 word
[3] = usb_in_buffer
[11 + i
* 4];
329 word
[0] = usb_in_buffer
[11 + i
* 4];
330 word
[1] = usb_in_buffer
[10 + i
* 4];
331 word
[2] = usb_in_buffer
[9 + i
* 4];
332 word
[3] = usb_in_buffer
[8 + i
* 4];
338 static void aice_unpack_dthmb(uint8_t *cmd_ack_code
, uint8_t *target_id
,
339 uint8_t *extra_word_length
)
341 *cmd_ack_code
= usb_in_buffer
[0];
342 *target_id
= usb_in_buffer
[1];
343 *extra_word_length
= usb_in_buffer
[2];
346 /***************************************************************************/
347 /* End of AICE commands' pack/unpack functions */
349 /* calls the given usb_bulk_* function, allowing for the data to
350 * trickle in with some timeouts */
351 static int usb_bulk_with_retries(
352 int (*f
)(jtag_libusb_device_handle
*, int, char *, int, int),
353 jtag_libusb_device_handle
*dev
, int ep
,
354 char *bytes
, int size
, int timeout
)
356 int tries
= 3, count
= 0;
358 while (tries
&& (count
< size
)) {
359 int result
= f(dev
, ep
, bytes
+ count
, size
- count
, timeout
);
362 else if ((-ETIMEDOUT
!= result
) || !--tries
)
368 static int wrap_usb_bulk_write(jtag_libusb_device_handle
*dev
, int ep
,
369 char *buff
, int size
, int timeout
)
371 /* usb_bulk_write() takes const char *buff */
372 return jtag_libusb_bulk_write(dev
, ep
, buff
, size
, timeout
);
375 static inline int usb_bulk_write_ex(jtag_libusb_device_handle
*dev
, int ep
,
376 char *bytes
, int size
, int timeout
)
378 return usb_bulk_with_retries(&wrap_usb_bulk_write
,
379 dev
, ep
, bytes
, size
, timeout
);
382 static inline int usb_bulk_read_ex(jtag_libusb_device_handle
*dev
, int ep
,
383 char *bytes
, int size
, int timeout
)
385 return usb_bulk_with_retries(&jtag_libusb_bulk_read
,
386 dev
, ep
, bytes
, size
, timeout
);
389 /* Write data from out_buffer to USB. */
390 static int aice_usb_write(uint8_t *out_buffer
, int out_length
)
394 if (out_length
> AICE_OUT_BUFFER_SIZE
) {
395 LOG_ERROR("aice_write illegal out_length=%i (max=%i)",
396 out_length
, AICE_OUT_BUFFER_SIZE
);
400 result
= usb_bulk_write_ex(aice_handler
.usb_handle
, aice_handler
.usb_write_ep
,
401 (char *)out_buffer
, out_length
, AICE_USB_TIMEOUT
);
403 DEBUG_JTAG_IO("aice_usb_write, out_length = %i, result = %i",
409 /* Read data from USB into in_buffer. */
410 static int aice_usb_read(uint8_t *in_buffer
, int expected_size
)
412 int32_t result
= usb_bulk_read_ex(aice_handler
.usb_handle
, aice_handler
.usb_read_ep
,
413 (char *)in_buffer
, expected_size
, AICE_USB_TIMEOUT
);
415 DEBUG_JTAG_IO("aice_usb_read, result = %" PRId32
, result
);
420 static uint8_t usb_out_packets_buffer
[AICE_OUT_PACKETS_BUFFER_SIZE
];
421 static uint8_t usb_in_packets_buffer
[AICE_IN_PACKETS_BUFFER_SIZE
];
422 static uint32_t usb_out_packets_buffer_length
;
423 static uint32_t usb_in_packets_buffer_length
;
424 static enum aice_command_mode aice_command_mode
;
426 static int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
,
427 uint32_t num_of_words
);
429 static int aice_usb_packet_flush(void)
431 if (usb_out_packets_buffer_length
== 0)
434 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
435 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
437 if (aice_usb_write(usb_out_packets_buffer
,
438 usb_out_packets_buffer_length
) < 0)
441 if (aice_usb_read(usb_in_packets_buffer
,
442 usb_in_packets_buffer_length
) < 0)
445 usb_out_packets_buffer_length
= 0;
446 usb_in_packets_buffer_length
= 0;
448 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
449 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
451 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
452 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
453 usb_out_packets_buffer
,
454 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
457 usb_out_packets_buffer_length
= 0;
458 usb_in_packets_buffer_length
= 0;
460 /* enable BATCH command */
461 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
462 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
, 0x80000000) != ERROR_OK
)
464 aice_command_mode
= AICE_COMMAND_MODE_BATCH
;
466 /* wait 1 second (AICE bug, workaround) */
471 uint32_t batch_status
;
475 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
477 if (batch_status
& 0x1)
479 else if (batch_status
& 0xE)
492 static int aice_usb_packet_append(uint8_t *out_buffer
, int out_length
, int in_length
)
494 uint32_t max_packet_size
= AICE_OUT_PACKETS_BUFFER_SIZE
;
496 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
497 max_packet_size
= AICE_OUT_PACK_COMMAND_SIZE
;
498 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
499 max_packet_size
= AICE_OUT_BATCH_COMMAND_SIZE
;
501 /* AICE_COMMAND_MODE_NORMAL */
502 if (aice_usb_packet_flush() != ERROR_OK
)
506 if (usb_out_packets_buffer_length
+ out_length
> max_packet_size
)
507 if (aice_usb_packet_flush() != ERROR_OK
) {
508 LOG_DEBUG("Flush usb packets failed");
512 LOG_DEBUG("Append usb packets 0x%02x", out_buffer
[0]);
514 memcpy(usb_out_packets_buffer
+ usb_out_packets_buffer_length
, out_buffer
, out_length
);
515 usb_out_packets_buffer_length
+= out_length
;
516 usb_in_packets_buffer_length
+= in_length
;
521 /***************************************************************************/
523 static int aice_reset_box(void)
525 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
528 /* turn off FASTMODE */
530 if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
)
534 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x2))
541 static int aice_scan_chain(uint32_t *id_codes
, uint8_t *num_of_ids
)
546 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
547 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
548 aice_usb_packet_flush();
551 aice_pack_htda(AICE_CMD_SCAN_CHAIN
, 0x0F, 0x0);
553 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
555 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
557 /** TODO: modify receive length */
558 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
559 if (AICE_FORMAT_DTHA
!= result
) {
560 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32
", result=%" PRId32
")",
561 AICE_FORMAT_DTHA
, result
);
565 uint8_t cmd_ack_code
;
566 aice_unpack_dtha_multiple_data(&cmd_ack_code
, num_of_ids
, id_codes
,
567 0x10, AICE_LITTLE_ENDIAN
);
569 if (cmd_ack_code
!= AICE_CMD_SCAN_CHAIN
) {
571 if (retry_times
> aice_max_retry_times
) {
572 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
573 AICE_CMD_SCAN_CHAIN
, cmd_ack_code
);
577 /* clear timeout and retry */
578 if (aice_reset_box() != ERROR_OK
)
585 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %" PRIu8
, *num_of_ids
);
587 if (*num_of_ids
== 0xFF) {
588 LOG_ERROR("No target connected");
590 } else if (*num_of_ids
== AICE_MAX_NUM_CORE
) {
591 LOG_INFO("The ice chain over 16 targets");
601 int aice_read_ctrl(uint32_t address
, uint32_t *data
)
605 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
606 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
607 aice_usb_packet_flush();
609 aice_pack_htda(AICE_CMD_READ_CTRL
, 0, address
);
611 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
613 LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32
, address
);
615 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
616 if (AICE_FORMAT_DTHA
!= result
) {
617 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32
", result=%" PRId32
")",
618 AICE_FORMAT_DTHA
, result
);
622 uint8_t cmd_ack_code
;
623 uint8_t extra_length
;
624 aice_unpack_dtha(&cmd_ack_code
, &extra_length
, data
, AICE_LITTLE_ENDIAN
);
626 LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32
, *data
);
628 if (cmd_ack_code
!= AICE_CMD_READ_CTRL
) {
629 LOG_ERROR("aice command error (command=0x%" PRIx32
", response=0x%" PRIx8
")",
630 (uint32_t)AICE_CMD_READ_CTRL
, cmd_ack_code
);
637 int aice_write_ctrl(uint32_t address
, uint32_t data
)
641 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
642 aice_usb_packet_flush();
643 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
644 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
645 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDC
,
649 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
651 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDC
);
653 LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32
", data: 0x%" PRIx32
, address
, data
);
655 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHB
);
656 if (AICE_FORMAT_DTHB
!= result
) {
657 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32
", result=%" PRId32
")",
658 AICE_FORMAT_DTHB
, result
);
662 uint8_t cmd_ack_code
;
663 uint8_t extra_length
;
664 aice_unpack_dthb(&cmd_ack_code
, &extra_length
);
666 LOG_DEBUG("WRITE_CTRL response");
668 if (cmd_ack_code
!= AICE_CMD_WRITE_CTRL
) {
669 LOG_ERROR("aice command error (command=0x%" PRIx8
", response=0x%" PRIx8
")",
670 AICE_CMD_WRITE_CTRL
, cmd_ack_code
);
677 int aice_read_dtr(uint8_t target_id
, uint32_t *data
)
682 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
683 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
684 aice_usb_packet_flush();
687 aice_pack_htdma(AICE_CMD_T_READ_DTR
, target_id
, 0, 0);
689 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
691 LOG_DEBUG("READ_DTR, COREID: %" PRIu8
, target_id
);
693 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
694 if (AICE_FORMAT_DTHMA
!= result
) {
695 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
696 AICE_FORMAT_DTHMA
, result
);
700 uint8_t cmd_ack_code
;
701 uint8_t extra_length
;
702 uint8_t res_target_id
;
703 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
704 data
, AICE_LITTLE_ENDIAN
);
706 if (cmd_ack_code
== AICE_CMD_T_READ_DTR
) {
707 LOG_DEBUG("READ_DTR response, data: 0x%" PRIx32
, *data
);
711 if (retry_times
> aice_max_retry_times
) {
712 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
713 AICE_CMD_T_READ_DTR
, cmd_ack_code
);
717 /* clear timeout and retry */
718 if (aice_reset_box() != ERROR_OK
)
728 int aice_read_dtr_to_buffer(uint8_t target_id
, uint32_t buffer_idx
)
733 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
734 aice_usb_packet_flush();
735 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
736 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
737 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
742 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
744 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
746 LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8
, target_id
);
748 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
749 if (AICE_FORMAT_DTHMB
!= result
) {
750 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")", AICE_FORMAT_DTHMB
, result
);
754 uint8_t cmd_ack_code
;
755 uint8_t extra_length
;
756 uint8_t res_target_id
;
757 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
759 if (cmd_ack_code
== AICE_CMD_READ_DTR_TO_BUFFER
) {
762 if (retry_times
> aice_max_retry_times
) {
763 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
764 AICE_CMD_READ_DTR_TO_BUFFER
, cmd_ack_code
);
769 /* clear timeout and retry */
770 if (aice_reset_box() != ERROR_OK
)
780 int aice_write_dtr(uint8_t target_id
, uint32_t data
)
785 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
786 aice_usb_packet_flush();
787 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
788 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
789 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
794 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
796 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
798 LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8
", data: 0x%" PRIx32
, target_id
, data
);
800 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
801 if (AICE_FORMAT_DTHMB
!= result
) {
802 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")", AICE_FORMAT_DTHMB
, result
);
806 uint8_t cmd_ack_code
;
807 uint8_t extra_length
;
808 uint8_t res_target_id
;
809 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
811 if (cmd_ack_code
== AICE_CMD_T_WRITE_DTR
) {
812 LOG_DEBUG("WRITE_DTR response");
815 if (retry_times
> aice_max_retry_times
) {
816 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
817 AICE_CMD_T_WRITE_DTR
, cmd_ack_code
);
822 /* clear timeout and retry */
823 if (aice_reset_box() != ERROR_OK
)
833 int aice_write_dtr_from_buffer(uint8_t target_id
, uint32_t buffer_idx
)
838 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
839 aice_usb_packet_flush();
840 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
841 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
842 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
847 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
849 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
851 LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8
"", target_id
);
853 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
854 if (AICE_FORMAT_DTHMB
!= result
) {
855 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")", AICE_FORMAT_DTHMB
, result
);
859 uint8_t cmd_ack_code
;
860 uint8_t extra_length
;
861 uint8_t res_target_id
;
862 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
864 if (cmd_ack_code
== AICE_CMD_WRITE_DTR_FROM_BUFFER
) {
867 if (retry_times
> aice_max_retry_times
) {
868 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
869 AICE_CMD_WRITE_DTR_FROM_BUFFER
, cmd_ack_code
);
874 /* clear timeout and retry */
875 if (aice_reset_box() != ERROR_OK
)
885 int aice_read_misc(uint8_t target_id
, uint32_t address
, uint32_t *data
)
890 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
891 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
892 aice_usb_packet_flush();
895 aice_pack_htdma(AICE_CMD_T_READ_MISC
, target_id
, 0, address
);
897 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
899 LOG_DEBUG("READ_MISC, COREID: %" PRIu8
", address: 0x%" PRIx32
, target_id
, address
);
901 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
902 if (AICE_FORMAT_DTHMA
!= result
) {
903 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
904 AICE_FORMAT_DTHMA
, result
);
905 return ERROR_AICE_DISCONNECT
;
908 uint8_t cmd_ack_code
;
909 uint8_t extra_length
;
910 uint8_t res_target_id
;
911 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
912 data
, AICE_LITTLE_ENDIAN
);
914 if (cmd_ack_code
== AICE_CMD_T_READ_MISC
) {
915 LOG_DEBUG("READ_MISC response, data: 0x%" PRIx32
, *data
);
918 if (retry_times
> aice_max_retry_times
) {
919 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
920 AICE_CMD_T_READ_MISC
, cmd_ack_code
);
924 /* clear timeout and retry */
925 if (aice_reset_box() != ERROR_OK
)
935 int aice_write_misc(uint8_t target_id
, uint32_t address
, uint32_t data
)
940 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
941 aice_usb_packet_flush();
942 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
943 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
, data
,
945 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
950 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
,
951 data
, AICE_LITTLE_ENDIAN
);
953 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
955 LOG_DEBUG("WRITE_MISC, COREID: %" PRIu8
", address: 0x%" PRIx32
", data: 0x%" PRIx32
,
956 target_id
, address
, data
);
958 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
959 if (AICE_FORMAT_DTHMB
!= result
) {
960 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
961 AICE_FORMAT_DTHMB
, result
);
965 uint8_t cmd_ack_code
;
966 uint8_t extra_length
;
967 uint8_t res_target_id
;
968 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
970 if (cmd_ack_code
== AICE_CMD_T_WRITE_MISC
) {
971 LOG_DEBUG("WRITE_MISC response");
974 if (retry_times
> aice_max_retry_times
) {
975 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
976 AICE_CMD_T_WRITE_MISC
, cmd_ack_code
);
981 /* clear timeout and retry */
982 if (aice_reset_box() != ERROR_OK
)
992 int aice_read_edmsr(uint8_t target_id
, uint32_t address
, uint32_t *data
)
997 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
998 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
999 aice_usb_packet_flush();
1002 aice_pack_htdma(AICE_CMD_T_READ_EDMSR
, target_id
, 0, address
);
1004 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
1006 LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8
", address: 0x%" PRIx32
, target_id
, address
);
1008 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1009 if (AICE_FORMAT_DTHMA
!= result
) {
1010 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1011 AICE_FORMAT_DTHMA
, result
);
1015 uint8_t cmd_ack_code
;
1016 uint8_t extra_length
;
1017 uint8_t res_target_id
;
1018 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1019 data
, AICE_LITTLE_ENDIAN
);
1021 if (cmd_ack_code
== AICE_CMD_T_READ_EDMSR
) {
1022 LOG_DEBUG("READ_EDMSR response, data: 0x%" PRIx32
, *data
);
1025 if (retry_times
> aice_max_retry_times
) {
1026 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1027 AICE_CMD_T_READ_EDMSR
, cmd_ack_code
);
1032 /* clear timeout and retry */
1033 if (aice_reset_box() != ERROR_OK
)
1043 int aice_write_edmsr(uint8_t target_id
, uint32_t address
, uint32_t data
)
1046 int retry_times
= 0;
1048 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1049 aice_usb_packet_flush();
1050 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1051 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
, data
,
1052 AICE_LITTLE_ENDIAN
);
1053 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
1058 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
,
1059 data
, AICE_LITTLE_ENDIAN
);
1061 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1063 LOG_DEBUG("WRITE_EDMSR, COREID: %" PRIu8
", address: 0x%" PRIx32
", data: 0x%" PRIx32
,
1064 target_id
, address
, data
);
1066 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1067 if (AICE_FORMAT_DTHMB
!= result
) {
1068 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1069 AICE_FORMAT_DTHMB
, result
);
1073 uint8_t cmd_ack_code
;
1074 uint8_t extra_length
;
1075 uint8_t res_target_id
;
1076 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1078 if (cmd_ack_code
== AICE_CMD_T_WRITE_EDMSR
) {
1079 LOG_DEBUG("WRITE_EDMSR response");
1082 if (retry_times
> aice_max_retry_times
) {
1083 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1084 AICE_CMD_T_WRITE_EDMSR
, cmd_ack_code
);
1089 /* clear timeout and retry */
1090 if (aice_reset_box() != ERROR_OK
)
1100 static int aice_switch_to_big_endian(uint32_t *word
, uint8_t num_of_words
)
1104 for (uint8_t i
= 0 ; i
< num_of_words
; i
++) {
1105 tmp
= ((word
[i
] >> 24) & 0x000000FF) |
1106 ((word
[i
] >> 8) & 0x0000FF00) |
1107 ((word
[i
] << 8) & 0x00FF0000) |
1108 ((word
[i
] << 24) & 0xFF000000);
1115 static int aice_write_dim(uint8_t target_id
, uint32_t *word
, uint8_t num_of_words
)
1118 uint32_t big_endian_word
[4];
1119 int retry_times
= 0;
1121 /** instruction is big-endian */
1122 memcpy(big_endian_word
, word
, sizeof(big_endian_word
));
1123 aice_switch_to_big_endian(big_endian_word
, num_of_words
);
1125 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1126 aice_usb_packet_flush();
1127 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1128 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
,
1129 num_of_words
- 1, 0, big_endian_word
, num_of_words
,
1130 AICE_LITTLE_ENDIAN
);
1131 return aice_usb_packet_append(usb_out_buffer
,
1132 AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4,
1137 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
, num_of_words
- 1, 0,
1138 big_endian_word
, num_of_words
, AICE_LITTLE_ENDIAN
);
1140 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1142 LOG_DEBUG("WRITE_DIM, COREID: %" PRIu8
1143 ", data: 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
,
1148 big_endian_word
[3]);
1150 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1151 if (AICE_FORMAT_DTHMB
!= result
) {
1152 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")", AICE_FORMAT_DTHMB
, result
);
1156 uint8_t cmd_ack_code
;
1157 uint8_t extra_length
;
1158 uint8_t res_target_id
;
1159 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1162 if (cmd_ack_code
== AICE_CMD_T_WRITE_DIM
) {
1163 LOG_DEBUG("WRITE_DIM response");
1166 if (retry_times
> aice_max_retry_times
) {
1167 LOG_ERROR("aice command timeout (command=0x%" PRIx8
1168 ", response=0x%" PRIx8
")",
1169 AICE_CMD_T_WRITE_DIM
, cmd_ack_code
);
1174 /* clear timeout and retry */
1175 if (aice_reset_box() != ERROR_OK
)
1185 static int aice_do_execute(uint8_t target_id
)
1188 int retry_times
= 0;
1190 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1191 aice_usb_packet_flush();
1192 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1193 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1194 return aice_usb_packet_append(usb_out_buffer
,
1200 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1202 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1204 LOG_DEBUG("EXECUTE, COREID: %" PRIu8
"", target_id
);
1206 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1207 if (AICE_FORMAT_DTHMB
!= result
) {
1208 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1209 AICE_FORMAT_DTHMB
, result
);
1213 uint8_t cmd_ack_code
;
1214 uint8_t extra_length
;
1215 uint8_t res_target_id
;
1216 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1218 if (cmd_ack_code
== AICE_CMD_T_EXECUTE
) {
1219 LOG_DEBUG("EXECUTE response");
1222 if (retry_times
> aice_max_retry_times
) {
1223 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1224 AICE_CMD_T_EXECUTE
, cmd_ack_code
);
1229 /* clear timeout and retry */
1230 if (aice_reset_box() != ERROR_OK
)
1240 int aice_write_mem_b(uint8_t target_id
, uint32_t address
, uint32_t data
)
1243 int retry_times
= 0;
1245 LOG_DEBUG("WRITE_MEM_B, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1250 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1251 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1252 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0, address
,
1253 data
& 0x000000FF, data_endian
);
1254 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1258 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0,
1259 address
, data
& 0x000000FF, data_endian
);
1260 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1262 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1263 if (AICE_FORMAT_DTHMB
!= result
) {
1264 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
1265 ", result=%" PRId32
")", AICE_FORMAT_DTHMB
, result
);
1269 uint8_t cmd_ack_code
;
1270 uint8_t extra_length
;
1271 uint8_t res_target_id
;
1272 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1274 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_B
) {
1277 if (retry_times
> aice_max_retry_times
) {
1278 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1279 AICE_CMD_T_WRITE_MEM_B
, cmd_ack_code
);
1284 /* clear timeout and retry */
1285 if (aice_reset_box() != ERROR_OK
)
1296 int aice_write_mem_h(uint8_t target_id
, uint32_t address
, uint32_t data
)
1299 int retry_times
= 0;
1301 LOG_DEBUG("WRITE_MEM_H, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1306 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1307 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1308 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1309 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1310 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1314 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1315 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1316 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1318 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1319 if (AICE_FORMAT_DTHMB
!= result
) {
1320 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1321 AICE_FORMAT_DTHMB
, result
);
1325 uint8_t cmd_ack_code
;
1326 uint8_t extra_length
;
1327 uint8_t res_target_id
;
1328 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1330 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_H
) {
1333 if (retry_times
> aice_max_retry_times
) {
1334 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1335 AICE_CMD_T_WRITE_MEM_H
, cmd_ack_code
);
1340 /* clear timeout and retry */
1341 if (aice_reset_box() != ERROR_OK
)
1352 int aice_write_mem(uint8_t target_id
, uint32_t address
, uint32_t data
)
1355 int retry_times
= 0;
1357 LOG_DEBUG("WRITE_MEM, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1362 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1363 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
)) {
1364 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1365 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1366 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1370 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1371 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1372 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1374 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1375 if (AICE_FORMAT_DTHMB
!= result
) {
1376 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1377 AICE_FORMAT_DTHMB
, result
);
1381 uint8_t cmd_ack_code
;
1382 uint8_t extra_length
;
1383 uint8_t res_target_id
;
1384 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1386 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM
) {
1389 if (retry_times
> aice_max_retry_times
) {
1390 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1391 AICE_CMD_T_WRITE_MEM
, cmd_ack_code
);
1396 /* clear timeout and retry */
1397 if (aice_reset_box() != ERROR_OK
)
1408 int aice_fastread_mem(uint8_t target_id
, uint8_t *word
, uint32_t num_of_words
)
1411 int retry_times
= 0;
1413 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1414 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1415 aice_usb_packet_flush();
1418 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM
, target_id
, num_of_words
- 1, 0);
1420 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1422 LOG_DEBUG("FASTREAD_MEM, COREID: %" PRIu8
", # of DATA %08" PRIx32
,
1423 target_id
, num_of_words
);
1425 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1427 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1428 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1432 uint8_t cmd_ack_code
;
1433 uint8_t extra_length
;
1434 uint8_t res_target_id
;
1435 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1436 &extra_length
, word
, data_endian
);
1438 if (cmd_ack_code
== AICE_CMD_T_FASTREAD_MEM
) {
1441 if (retry_times
> aice_max_retry_times
) {
1442 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1443 AICE_CMD_T_FASTREAD_MEM
, cmd_ack_code
);
1448 /* clear timeout and retry */
1449 if (aice_reset_box() != ERROR_OK
)
1459 int aice_fastwrite_mem(uint8_t target_id
, const uint8_t *word
, uint32_t num_of_words
)
1462 int retry_times
= 0;
1464 if (AICE_COMMAND_MODE_PACK
== aice_command_mode
) {
1465 aice_usb_packet_flush();
1466 } else if (AICE_COMMAND_MODE_BATCH
== aice_command_mode
) {
1467 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1468 num_of_words
- 1, 0, word
, data_endian
);
1469 return aice_usb_packet_append(usb_out_buffer
,
1470 AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4,
1475 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1476 num_of_words
- 1, 0, word
, data_endian
);
1478 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4);
1480 LOG_DEBUG("FASTWRITE_MEM, COREID: %" PRIu8
", # of DATA %08" PRIx32
,
1481 target_id
, num_of_words
);
1483 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1484 if (AICE_FORMAT_DTHMB
!= result
) {
1485 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1486 AICE_FORMAT_DTHMB
, result
);
1490 uint8_t cmd_ack_code
;
1491 uint8_t extra_length
;
1492 uint8_t res_target_id
;
1493 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1495 if (cmd_ack_code
== AICE_CMD_T_FASTWRITE_MEM
) {
1498 if (retry_times
> aice_max_retry_times
) {
1499 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1500 AICE_CMD_T_FASTWRITE_MEM
, cmd_ack_code
);
1505 /* clear timeout and retry */
1506 if (aice_reset_box() != ERROR_OK
)
1516 int aice_read_mem_b(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1519 int retry_times
= 0;
1521 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1522 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1523 aice_usb_packet_flush();
1526 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B
, target_id
, 0, address
);
1528 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1530 LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8
"", target_id
);
1532 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1533 if (AICE_FORMAT_DTHMA
!= result
) {
1534 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1535 AICE_FORMAT_DTHMA
, result
);
1539 uint8_t cmd_ack_code
;
1540 uint8_t extra_length
;
1541 uint8_t res_target_id
;
1542 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1545 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_B
) {
1546 LOG_DEBUG("READ_MEM_B response, data: 0x%02" PRIx32
, *data
);
1549 if (retry_times
> aice_max_retry_times
) {
1550 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1551 AICE_CMD_T_READ_MEM_B
, cmd_ack_code
);
1556 /* clear timeout and retry */
1557 if (aice_reset_box() != ERROR_OK
)
1567 int aice_read_mem_h(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1570 int retry_times
= 0;
1572 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1573 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1574 aice_usb_packet_flush();
1577 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H
, target_id
, 0, (address
>> 1) & 0x7FFFFFFF);
1579 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1581 LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8
"", target_id
);
1583 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1584 if (AICE_FORMAT_DTHMA
!= result
) {
1585 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1586 AICE_FORMAT_DTHMA
, result
);
1590 uint8_t cmd_ack_code
;
1591 uint8_t extra_length
;
1592 uint8_t res_target_id
;
1593 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1596 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_H
) {
1597 LOG_DEBUG("READ_MEM_H response, data: 0x%" PRIx32
, *data
);
1600 if (retry_times
> aice_max_retry_times
) {
1601 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1602 AICE_CMD_T_READ_MEM_H
, cmd_ack_code
);
1607 /* clear timeout and retry */
1608 if (aice_reset_box() != ERROR_OK
)
1618 int aice_read_mem(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1621 int retry_times
= 0;
1623 if ((AICE_COMMAND_MODE_PACK
== aice_command_mode
) ||
1624 (AICE_COMMAND_MODE_BATCH
== aice_command_mode
))
1625 aice_usb_packet_flush();
1628 aice_pack_htdmb(AICE_CMD_T_READ_MEM
, target_id
, 0,
1629 (address
>> 2) & 0x3FFFFFFF);
1631 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1633 LOG_DEBUG("READ_MEM, COREID: %" PRIu8
"", target_id
);
1635 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1636 if (AICE_FORMAT_DTHMA
!= result
) {
1637 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1638 AICE_FORMAT_DTHMA
, result
);
1642 uint8_t cmd_ack_code
;
1643 uint8_t extra_length
;
1644 uint8_t res_target_id
;
1645 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1648 if (cmd_ack_code
== AICE_CMD_T_READ_MEM
) {
1649 LOG_DEBUG("READ_MEM response, data: 0x%" PRIx32
, *data
);
1652 if (retry_times
> aice_max_retry_times
) {
1653 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1654 AICE_CMD_T_READ_MEM
, cmd_ack_code
);
1659 /* clear timeout and retry */
1660 if (aice_reset_box() != ERROR_OK
)
1670 int aice_batch_buffer_read(uint8_t buf_index
, uint32_t *word
, uint32_t num_of_words
)
1673 int retry_times
= 0;
1676 aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ
, 0, num_of_words
- 1, buf_index
);
1678 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
1680 LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32
, num_of_words
);
1682 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1684 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1685 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1689 uint8_t cmd_ack_code
;
1690 uint8_t extra_length
;
1691 uint8_t res_target_id
;
1692 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1693 &extra_length
, (uint8_t *)word
, data_endian
);
1695 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_READ
) {
1698 if (retry_times
> aice_max_retry_times
) {
1699 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1700 AICE_CMD_BATCH_BUFFER_READ
, cmd_ack_code
);
1705 /* clear timeout and retry */
1706 if (aice_reset_box() != ERROR_OK
)
1716 int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
, uint32_t num_of_words
)
1719 int retry_times
= 0;
1721 if (num_of_words
== 0)
1725 /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */
1726 aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE
, 0, num_of_words
- 1, buf_index
,
1729 /* use append instead of pack */
1730 memcpy(usb_out_buffer
+ 4, word
, num_of_words
* 4);
1732 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1734 LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32
, num_of_words
);
1736 result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1737 if (AICE_FORMAT_DTHMB
!= result
) {
1738 LOG_ERROR("aice_usb_read failed (requested=%" PRId32
", result=%" PRId32
")",
1739 AICE_FORMAT_DTHMB
, result
);
1743 uint8_t cmd_ack_code
;
1744 uint8_t extra_length
;
1745 uint8_t res_target_id
;
1746 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1748 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_WRITE
) {
1751 if (retry_times
> aice_max_retry_times
) {
1752 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1753 AICE_CMD_BATCH_BUFFER_WRITE
, cmd_ack_code
);
1758 /* clear timeout and retry */
1759 if (aice_reset_box() != ERROR_OK
)
1769 /***************************************************************************/
1770 /* End of AICE commands */
1772 typedef int (*read_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t *data
);
1773 typedef int (*write_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t data
);
1775 struct aice_nds32_info core_info
[AICE_MAX_NUM_CORE
];
1776 static uint8_t total_num_of_core
;
1778 static char *custom_srst_script
;
1779 static char *custom_trst_script
;
1780 static char *custom_restart_script
;
1781 static uint32_t aice_count_to_check_dbger
= 30;
1783 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
);
1784 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
);
1786 static int check_suppressed_exception(uint32_t coreid
, uint32_t dbger_value
)
1790 /* the default value of handling_suppressed_exception is false */
1791 static bool handling_suppressed_exception
;
1793 if (handling_suppressed_exception
)
1796 if ((dbger_value
& NDS_DBGER_ALL_SUPRS_EX
) == NDS_DBGER_ALL_SUPRS_EX
) {
1797 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1798 handling_suppressed_exception
= true;
1800 aice_read_reg(coreid
, IR4
, &ir4_value
);
1801 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1802 aice_read_reg(coreid
, IR6
, &ir6_value
);
1804 * For MCU version(MSC_CFG.MCU == 1) like V3m
1805 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1806 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1808 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1809 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1810 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1812 LOG_INFO("EVA: 0x%08" PRIx32
, ir4_value
);
1813 LOG_INFO("ITYPE: 0x%08" PRIx32
, ir6_value
);
1815 ir6_value
= ir6_value
& (~0x300); /* for MCU */
1816 ir6_value
= ir6_value
& (~0x3000); /* for non-MCU */
1817 aice_write_reg(coreid
, IR6
, ir6_value
);
1819 handling_suppressed_exception
= false;
1825 static int check_privilege(uint32_t coreid
, uint32_t dbger_value
)
1827 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
1828 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1829 "to execute the debug operations. -->");
1831 /* Clear DBGER.ILL_SEC_ACC */
1832 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
1833 NDS_DBGER_ILL_SEC_ACC
) != ERROR_OK
)
1840 static int aice_check_dbger(uint32_t coreid
, uint32_t expect_status
)
1843 uint32_t value_dbger
;
1846 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &value_dbger
);
1848 if ((value_dbger
& expect_status
) == expect_status
) {
1849 if (ERROR_OK
!= check_suppressed_exception(coreid
, value_dbger
))
1851 if (ERROR_OK
!= check_privilege(coreid
, value_dbger
))
1860 if (i
== aice_count_to_check_dbger
)
1861 then
= timeval_ms();
1862 if (i
>= aice_count_to_check_dbger
) {
1863 if ((timeval_ms() - then
) > 1000) {
1864 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1865 "being 0x%08" PRIx32
, expect_status
);
1875 static int aice_execute_dim(uint32_t coreid
, uint32_t *insts
, uint8_t n_inst
)
1878 if (aice_write_dim(coreid
, insts
, n_inst
) != ERROR_OK
)
1881 /** clear DBGER.DPED */
1882 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
1886 if (aice_do_execute(coreid
) != ERROR_OK
)
1889 /** read DBGER.DPED */
1890 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
1891 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1892 "0x%08" PRIx32
"0x%08" PRIx32
"0x%08" PRIx32
"0x%08" PRIx32
". -->",
1903 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1905 LOG_DEBUG("aice_read_reg, reg_no: 0x%08" PRIx32
, num
);
1907 uint32_t instructions
[4]; /** execute instructions in DIM */
1909 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1910 instructions
[0] = MTSR_DTR(num
);
1911 instructions
[1] = DSB
;
1912 instructions
[2] = NOP
;
1913 instructions
[3] = BEQ_MINUS_12
;
1914 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1915 instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(num
));
1916 instructions
[1] = MTSR_DTR(0);
1917 instructions
[2] = DSB
;
1918 instructions
[3] = BEQ_MINUS_12
;
1919 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1920 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1921 instructions
[0] = AMFAR2(0, nds32_reg_sr_index(num
));
1922 instructions
[1] = MTSR_DTR(0);
1923 instructions
[2] = DSB
;
1924 instructions
[3] = BEQ_MINUS_12
;
1926 instructions
[0] = AMFAR(0, nds32_reg_sr_index(num
));
1927 instructions
[1] = MTSR_DTR(0);
1928 instructions
[2] = DSB
;
1929 instructions
[3] = BEQ_MINUS_12
;
1931 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1933 instructions
[0] = FMFCSR
;
1934 instructions
[1] = MTSR_DTR(0);
1935 instructions
[2] = DSB
;
1936 instructions
[3] = BEQ_MINUS_12
;
1937 } else if (FPCFG
== num
) {
1938 instructions
[0] = FMFCFG
;
1939 instructions
[1] = MTSR_DTR(0);
1940 instructions
[2] = DSB
;
1941 instructions
[3] = BEQ_MINUS_12
;
1943 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
1944 instructions
[0] = FMFSR(0, nds32_reg_sr_index(num
));
1945 instructions
[1] = MTSR_DTR(0);
1946 instructions
[2] = DSB
;
1947 instructions
[3] = BEQ_MINUS_12
;
1948 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
1949 instructions
[0] = FMFDR(0, nds32_reg_sr_index(num
));
1950 instructions
[1] = MTSR_DTR(0);
1951 instructions
[2] = DSB
;
1952 instructions
[3] = BEQ_MINUS_12
;
1955 } else { /* system registers */
1956 instructions
[0] = MFSR(0, nds32_reg_sr_index(num
));
1957 instructions
[1] = MTSR_DTR(0);
1958 instructions
[2] = DSB
;
1959 instructions
[3] = BEQ_MINUS_12
;
1962 aice_execute_dim(coreid
, instructions
, 4);
1964 uint32_t value_edmsw
;
1965 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1966 if (value_edmsw
& NDS_EDMSW_WDV
)
1967 aice_read_dtr(coreid
, val
);
1969 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1970 "the DTR register. -->");
1977 static int aice_usb_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1979 LOG_DEBUG("aice_usb_read_reg");
1982 *val
= core_info
[coreid
].r0_backup
;
1983 } else if (num
== R1
) {
1984 *val
= core_info
[coreid
].r1_backup
;
1985 } else if (num
== DR41
) {
1986 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1987 * As user wants to read these registers, OpenOCD should return
1988 * the backup values, instead of reading the real values.
1989 * As user wants to write these registers, OpenOCD should write
1990 * to the backup values, instead of writing to real registers. */
1991 *val
= core_info
[coreid
].edmsw_backup
;
1992 } else if (num
== DR42
) {
1993 *val
= core_info
[coreid
].edm_ctl_backup
;
1994 } else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
)) {
1995 *val
= core_info
[coreid
].target_dtr_backup
;
1997 if (ERROR_OK
!= aice_read_reg(coreid
, num
, val
))
2004 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
2006 LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32
", value: 0x%08" PRIx32
, num
, val
);
2008 uint32_t instructions
[4]; /** execute instructions in DIM */
2009 uint32_t value_edmsw
;
2011 aice_write_dtr(coreid
, val
);
2012 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2013 if (0 == (value_edmsw
& NDS_EDMSW_RDV
)) {
2014 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
2018 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
2019 instructions
[0] = MFSR_DTR(num
);
2020 instructions
[1] = DSB
;
2021 instructions
[2] = NOP
;
2022 instructions
[3] = BEQ_MINUS_12
;
2023 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
2024 instructions
[0] = MFSR_DTR(0);
2025 instructions
[1] = MTUSR_G0(0, nds32_reg_sr_index(num
));
2026 instructions
[2] = DSB
;
2027 instructions
[3] = BEQ_MINUS_12
;
2028 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
2029 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
2030 instructions
[0] = MFSR_DTR(0);
2031 instructions
[1] = AMTAR2(0, nds32_reg_sr_index(num
));
2032 instructions
[2] = DSB
;
2033 instructions
[3] = BEQ_MINUS_12
;
2035 instructions
[0] = MFSR_DTR(0);
2036 instructions
[1] = AMTAR(0, nds32_reg_sr_index(num
));
2037 instructions
[2] = DSB
;
2038 instructions
[3] = BEQ_MINUS_12
;
2040 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
2042 instructions
[0] = MFSR_DTR(0);
2043 instructions
[1] = FMTCSR
;
2044 instructions
[2] = DSB
;
2045 instructions
[3] = BEQ_MINUS_12
;
2046 } else if (FPCFG
== num
) {
2047 /* FPCFG is readonly */
2049 if (FS0
<= num
&& num
<= FS31
) { /* single precision */
2050 instructions
[0] = MFSR_DTR(0);
2051 instructions
[1] = FMTSR(0, nds32_reg_sr_index(num
));
2052 instructions
[2] = DSB
;
2053 instructions
[3] = BEQ_MINUS_12
;
2054 } else if (FD0
<= num
&& num
<= FD31
) { /* double precision */
2055 instructions
[0] = MFSR_DTR(0);
2056 instructions
[1] = FMTDR(0, nds32_reg_sr_index(num
));
2057 instructions
[2] = DSB
;
2058 instructions
[3] = BEQ_MINUS_12
;
2062 instructions
[0] = MFSR_DTR(0);
2063 instructions
[1] = MTSR(0, nds32_reg_sr_index(num
));
2064 instructions
[2] = DSB
;
2065 instructions
[3] = BEQ_MINUS_12
;
2068 return aice_execute_dim(coreid
, instructions
, 4);
2071 static int aice_usb_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
2073 LOG_DEBUG("aice_usb_write_reg");
2076 core_info
[coreid
].r0_backup
= val
;
2078 core_info
[coreid
].r1_backup
= val
;
2079 else if (num
== DR42
)
2080 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
2081 * As user wants to read these registers, OpenOCD should return
2082 * the backup values, instead of reading the real values.
2083 * As user wants to write these registers, OpenOCD should write
2084 * to the backup values, instead of writing to real registers. */
2085 core_info
[coreid
].edm_ctl_backup
= val
;
2086 else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
))
2087 core_info
[coreid
].target_dtr_backup
= val
;
2089 return aice_write_reg(coreid
, num
, val
);
2094 static int aice_usb_open(struct aice_port_param_s
*param
)
2096 const uint16_t vids
[] = { param
->vid
, 0 };
2097 const uint16_t pids
[] = { param
->pid
, 0 };
2098 struct jtag_libusb_device_handle
*devh
;
2100 if (jtag_libusb_open(vids
, pids
, NULL
, &devh
) != ERROR_OK
)
2103 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
2104 * AREA!!!!!!!!!!! The behavior of libusb is not completely
2105 * consistent across Windows, Linux, and Mac OS X platforms.
2106 * The actions taken in the following compiler conditionals may
2107 * not agree with published documentation for libusb, but were
2108 * found to be necessary through trials and tribulations. Even
2109 * little tweaks can break one or more platforms, so if you do
2110 * make changes test them carefully on all platforms before
2116 jtag_libusb_reset_device(devh
);
2121 /* reopen jlink after usb_reset
2122 * on win32 this may take a second or two to re-enumerate */
2124 while ((retval
= jtag_libusb_open(vids
, pids
, NULL
, &devh
)) != ERROR_OK
) {
2130 if (ERROR_OK
!= retval
)
2136 /* usb_set_configuration required under win32 */
2137 jtag_libusb_set_configuration(devh
, 0);
2139 unsigned int aice_read_ep
;
2140 unsigned int aice_write_ep
;
2141 jtag_libusb_choose_interface(devh
, &aice_read_ep
, &aice_write_ep
, -1, -1, -1);
2143 aice_handler
.usb_read_ep
= aice_read_ep
;
2144 aice_handler
.usb_write_ep
= aice_write_ep
;
2145 aice_handler
.usb_handle
= devh
;
2150 static int aice_usb_read_reg_64(uint32_t coreid
, uint32_t num
, uint64_t *val
)
2152 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num
));
2155 uint32_t high_value
;
2157 if (ERROR_OK
!= aice_read_reg(coreid
, num
, &value
))
2160 aice_read_reg(coreid
, R1
, &high_value
);
2162 LOG_DEBUG("low: 0x%08" PRIx32
", high: 0x%08" PRIx32
"\n", value
, high_value
);
2164 if (data_endian
== AICE_BIG_ENDIAN
)
2165 *val
= (((uint64_t)high_value
) << 32) | value
;
2167 *val
= (((uint64_t)value
) << 32) | high_value
;
2172 static int aice_usb_write_reg_64(uint32_t coreid
, uint32_t num
, uint64_t val
)
2175 uint32_t high_value
;
2177 if (data_endian
== AICE_BIG_ENDIAN
) {
2178 value
= val
& 0xFFFFFFFF;
2179 high_value
= (val
>> 32) & 0xFFFFFFFF;
2181 high_value
= val
& 0xFFFFFFFF;
2182 value
= (val
>> 32) & 0xFFFFFFFF;
2185 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08" PRIx32
", high: 0x%08" PRIx32
"\n",
2186 nds32_reg_simple_name(num
), value
, high_value
);
2188 aice_write_reg(coreid
, R1
, high_value
);
2189 return aice_write_reg(coreid
, num
, value
);
2192 static int aice_get_version_info(void)
2194 uint32_t hardware_version
;
2195 uint32_t firmware_version
;
2196 uint32_t fpga_version
;
2198 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION
, &hardware_version
) != ERROR_OK
)
2201 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION
, &firmware_version
) != ERROR_OK
)
2204 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION
, &fpga_version
) != ERROR_OK
)
2207 LOG_INFO("AICE version: hw_ver = 0x%" PRIx32
", fw_ver = 0x%" PRIx32
", fpga_ver = 0x%" PRIx32
,
2208 hardware_version
, firmware_version
, fpga_version
);
2213 #define LINE_BUFFER_SIZE 1024
2215 static int aice_execute_custom_script(const char *script
)
2218 char line_buffer
[LINE_BUFFER_SIZE
];
2222 uint32_t write_ctrl_value
;
2225 script_fd
= fopen(script
, "r");
2226 if (script_fd
== NULL
) {
2229 while (fgets(line_buffer
, LINE_BUFFER_SIZE
, script_fd
) != NULL
) {
2230 /* execute operations */
2232 op_str
= strstr(line_buffer
, "set");
2233 if (op_str
!= NULL
) {
2235 goto get_reset_type
;
2238 op_str
= strstr(line_buffer
, "clear");
2242 reset_str
= strstr(op_str
, "srst");
2243 if (reset_str
!= NULL
) {
2245 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2247 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2250 reset_str
= strstr(op_str
, "dbgi");
2251 if (reset_str
!= NULL
) {
2253 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_DBGI
;
2255 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_DBGI
;
2258 reset_str
= strstr(op_str
, "trst");
2259 if (reset_str
!= NULL
) {
2261 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_TRST
;
2263 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_TRST
;
2269 delay
= strtoul(reset_str
+ 4, NULL
, 0);
2270 write_ctrl_value
|= (delay
<< 16);
2272 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2273 write_ctrl_value
) != ERROR_OK
) {
2284 static int aice_usb_set_clock(int set_clock
)
2286 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
,
2287 AICE_TCK_CONTROL_TCK_SCAN
) != ERROR_OK
)
2290 /* Read out TCK_SCAN clock value */
2291 uint32_t scan_clock
;
2292 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &scan_clock
) != ERROR_OK
)
2297 uint32_t scan_base_freq
;
2298 if (scan_clock
& 0x8)
2299 scan_base_freq
= 48000; /* 48 MHz */
2301 scan_base_freq
= 30000; /* 30 MHz */
2303 uint32_t set_base_freq
;
2304 if (set_clock
& 0x8)
2305 set_base_freq
= 48000;
2307 set_base_freq
= 30000;
2311 set_freq
= set_base_freq
>> (set_clock
& 0x7);
2312 scan_freq
= scan_base_freq
>> (scan_clock
& 0x7);
2314 if (scan_freq
< set_freq
) {
2315 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
2319 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
, set_clock
) != ERROR_OK
)
2322 uint32_t check_speed
;
2323 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &check_speed
) != ERROR_OK
)
2326 if (((int)check_speed
& 0x0F) != set_clock
) {
2327 LOG_ERROR("Set jtag clock failed");
2334 static int aice_edm_init(uint32_t coreid
)
2336 aice_write_edmsr(coreid
, NDS_EDM_SR_DIMBR
, 0xFFFF0000);
2337 aice_write_misc(coreid
, NDS_EDM_MISC_DIMIR
, 0);
2339 /* unconditionally try to turn on V3_EDM_MODE */
2340 uint32_t edm_ctl_value
;
2341 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2342 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
| 0x00000040);
2345 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2346 NDS_DBGER_DPED
| NDS_DBGER_CRST
| NDS_DBGER_AT_MAX
);
2348 /* get EDM version */
2349 uint32_t value_edmcfg
;
2350 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CFG
, &value_edmcfg
);
2351 core_info
[coreid
].edm_version
= (value_edmcfg
>> 16) & 0xFFFF;
2356 static bool is_v2_edm(uint32_t coreid
)
2358 if ((core_info
[coreid
].edm_version
& 0x1000) == 0)
2364 static int aice_init_edm_registers(uint32_t coreid
, bool clear_dex_use_psw
)
2366 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2367 uint32_t host_edm_ctl
= core_info
[coreid
].edm_ctl_backup
| 0xA000004F;
2368 if (clear_dex_use_psw
)
2369 /* After entering debug mode, OpenOCD may set
2370 * DEX_USE_PSW accidentally through backup value
2371 * of target EDM_CTL.
2372 * So, clear DEX_USE_PSW by force. */
2373 host_edm_ctl
&= ~(0x40000000);
2375 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08" PRIx32
, host_edm_ctl
);
2377 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, host_edm_ctl
);
2383 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2384 * responsibility to keep EDM_CTL untouched after debugging.
2386 * There are two scenarios to consider:
2387 * 1. single step/running as debugging (running under debug session)
2388 * 2. detached from gdb (exit debug session)
2390 * So, we need to bakcup EDM_CTL before halted and restore it after
2391 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2392 * is on for scenario 1, and off for scenario 2.
2394 static int aice_backup_edm_registers(uint32_t coreid
)
2396 int result
= aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2397 &core_info
[coreid
].edm_ctl_backup
);
2399 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2400 * may be not correct. (For example, hit breakpoint, then backup
2401 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2402 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2403 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2404 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2405 if (core_info
[coreid
].edm_ctl_backup
& 0x40000000)
2406 core_info
[coreid
].dex_use_psw_on
= true;
2408 core_info
[coreid
].dex_use_psw_on
= false;
2410 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08" PRIx32
", DEX_USE_PSW: %s",
2411 core_info
[coreid
].edm_ctl_backup
,
2412 core_info
[coreid
].dex_use_psw_on
? "on" : "off");
2417 static int aice_restore_edm_registers(uint32_t coreid
)
2419 LOG_DEBUG("aice_restore_edm_registers -");
2421 /* set DEH_SEL, because target still under EDM control */
2422 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2423 core_info
[coreid
].edm_ctl_backup
| 0x80000000);
2428 static int aice_backup_tmp_registers(uint32_t coreid
)
2430 LOG_DEBUG("backup_tmp_registers -");
2432 /* backup target DTR first(if the target DTR is valid) */
2433 uint32_t value_edmsw
;
2434 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2435 core_info
[coreid
].edmsw_backup
= value_edmsw
;
2436 if (value_edmsw
& 0x1) { /* EDMSW.WDV == 1 */
2437 aice_read_dtr(coreid
, &core_info
[coreid
].target_dtr_backup
);
2438 core_info
[coreid
].target_dtr_valid
= true;
2440 LOG_DEBUG("Backup target DTR: 0x%08" PRIx32
, core_info
[coreid
].target_dtr_backup
);
2442 core_info
[coreid
].target_dtr_valid
= false;
2445 /* Target DTR has been backup, then backup $R0 and $R1 */
2446 aice_read_reg(coreid
, R0
, &core_info
[coreid
].r0_backup
);
2447 aice_read_reg(coreid
, R1
, &core_info
[coreid
].r1_backup
);
2449 /* backup host DTR(if the host DTR is valid) */
2450 if (value_edmsw
& 0x2) { /* EDMSW.RDV == 1*/
2451 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2453 uint32_t instructions
[4] = {
2454 MFSR_DTR(R0
), /* R0 has already been backup */
2459 aice_execute_dim(coreid
, instructions
, 4);
2461 aice_read_dtr(coreid
, &core_info
[coreid
].host_dtr_backup
);
2462 core_info
[coreid
].host_dtr_valid
= true;
2464 LOG_DEBUG("Backup host DTR: 0x%08" PRIx32
, core_info
[coreid
].host_dtr_backup
);
2466 core_info
[coreid
].host_dtr_valid
= false;
2469 LOG_DEBUG("r0: 0x%08" PRIx32
", r1: 0x%08" PRIx32
,
2470 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2475 static int aice_restore_tmp_registers(uint32_t coreid
)
2477 LOG_DEBUG("restore_tmp_registers - r0: 0x%08" PRIx32
", r1: 0x%08" PRIx32
,
2478 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2480 if (core_info
[coreid
].target_dtr_valid
) {
2481 uint32_t instructions
[4] = {
2482 SETHI(R0
, core_info
[coreid
].target_dtr_backup
>> 12),
2483 ORI(R0
, R0
, core_info
[coreid
].target_dtr_backup
& 0x00000FFF),
2487 aice_execute_dim(coreid
, instructions
, 4);
2489 instructions
[0] = MTSR_DTR(R0
);
2490 instructions
[1] = DSB
;
2491 instructions
[2] = NOP
;
2492 instructions
[3] = BEQ_MINUS_12
;
2493 aice_execute_dim(coreid
, instructions
, 4);
2495 LOG_DEBUG("Restore target DTR: 0x%08" PRIx32
, core_info
[coreid
].target_dtr_backup
);
2498 aice_write_reg(coreid
, R0
, core_info
[coreid
].r0_backup
);
2499 aice_write_reg(coreid
, R1
, core_info
[coreid
].r1_backup
);
2501 if (core_info
[coreid
].host_dtr_valid
) {
2502 aice_write_dtr(coreid
, core_info
[coreid
].host_dtr_backup
);
2504 LOG_DEBUG("Restore host DTR: 0x%08" PRIx32
, core_info
[coreid
].host_dtr_backup
);
2510 static int aice_open_device(struct aice_port_param_s
*param
)
2512 if (ERROR_OK
!= aice_usb_open(param
))
2515 if (ERROR_FAIL
== aice_get_version_info()) {
2516 LOG_ERROR("Cannot get AICE version!");
2520 LOG_INFO("AICE initialization started");
2522 /* attempt to reset Andes EDM */
2523 if (ERROR_FAIL
== aice_reset_box()) {
2524 LOG_ERROR("Cannot initial AICE box!");
2531 static int aice_usb_set_jtag_clock(uint32_t a_clock
)
2533 jtag_clock
= a_clock
;
2535 if (ERROR_OK
!= aice_usb_set_clock(a_clock
)) {
2536 LOG_ERROR("Cannot set AICE JTAG clock!");
2543 static int aice_usb_close(void)
2545 jtag_libusb_close(aice_handler
.usb_handle
);
2547 if (custom_srst_script
)
2548 free(custom_srst_script
);
2550 if (custom_trst_script
)
2551 free(custom_trst_script
);
2553 if (custom_restart_script
)
2554 free(custom_restart_script
);
2559 static int aice_core_init(uint32_t coreid
)
2561 core_info
[coreid
].access_channel
= NDS_MEMORY_ACC_CPU
;
2562 core_info
[coreid
].memory_select
= NDS_MEMORY_SELECT_AUTO
;
2563 core_info
[coreid
].core_state
= AICE_TARGET_UNKNOWN
;
2568 static int aice_usb_idcode(uint32_t *idcode
, uint8_t *num_of_idcode
)
2572 retval
= aice_scan_chain(idcode
, num_of_idcode
);
2573 if (ERROR_OK
== retval
) {
2574 for (int i
= 0; i
< *num_of_idcode
; i
++) {
2578 total_num_of_core
= *num_of_idcode
;
2584 static int aice_usb_halt(uint32_t coreid
)
2586 if (core_info
[coreid
].core_state
== AICE_TARGET_HALTED
) {
2587 LOG_DEBUG("aice_usb_halt check halted");
2591 LOG_DEBUG("aice_usb_halt");
2593 /** backup EDM registers */
2594 aice_backup_edm_registers(coreid
);
2595 /** init EDM for host debugging */
2596 /** no need to clear dex_use_psw, because dbgi will clear it */
2597 aice_init_edm_registers(coreid
, false);
2599 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2600 uint32_t edm_ctl_value
;
2601 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2602 if (edm_ctl_value
& 0x3)
2603 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
& ~(0x3));
2606 uint32_t acc_ctl_value
;
2608 core_info
[coreid
].debug_under_dex_on
= false;
2609 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger
);
2611 if (dbger
& NDS_DBGER_AT_MAX
)
2612 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2614 if (dbger
& NDS_DBGER_DEX
) {
2615 if (is_v2_edm(coreid
) == false) {
2616 /** debug 'debug mode'. use force_debug to issue dbgi */
2617 aice_read_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, &acc_ctl_value
);
2618 acc_ctl_value
|= 0x8;
2619 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, acc_ctl_value
);
2620 core_info
[coreid
].debug_under_dex_on
= true;
2622 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2623 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2624 if (dbger
& NDS_DBGER_AT_MAX
)
2625 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2628 /** Issue DBGI normally */
2629 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2630 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2631 if (dbger
& NDS_DBGER_AT_MAX
)
2632 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2635 if (aice_check_dbger(coreid
, NDS_DBGER_DEX
) != ERROR_OK
) {
2636 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2640 if (core_info
[coreid
].debug_under_dex_on
) {
2641 if (core_info
[coreid
].dex_use_psw_on
== false) {
2642 /* under debug 'debug mode', force $psw to 'debug mode' bahavior */
2643 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2644 * it is only for debugging 'debug exception handler' purpose.
2645 * after openocd detaches from target, target behavior is
2648 uint32_t debug_mode_ir0_value
;
2649 aice_read_reg(coreid
, IR0
, &ir0_value
);
2650 debug_mode_ir0_value
= ir0_value
| 0x408; /* turn on DEX, set POM = 1 */
2651 debug_mode_ir0_value
&= ~(0x000000C1); /* turn off DT/IT/GIE */
2652 aice_write_reg(coreid
, IR0
, debug_mode_ir0_value
);
2656 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2657 if (edm_ctl_value
& 0x3)
2658 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
);
2660 /* backup r0 & r1 */
2661 aice_backup_tmp_registers(coreid
);
2662 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2667 static int aice_usb_state(uint32_t coreid
, enum aice_target_state_s
*state
)
2669 uint32_t dbger_value
;
2672 int result
= aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger_value
);
2674 if (ERROR_AICE_TIMEOUT
== result
) {
2675 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &ice_state
) != ERROR_OK
) {
2676 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2680 if ((ice_state
& 0x20) == 0) {
2681 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2686 } else if (ERROR_AICE_DISCONNECT
== result
) {
2687 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2691 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
2692 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2694 /* Clear ILL_SEC_ACC */
2695 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_ILL_SEC_ACC
);
2697 *state
= AICE_TARGET_RUNNING
;
2698 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2699 } else if ((dbger_value
& NDS_DBGER_AT_MAX
) == NDS_DBGER_AT_MAX
) {
2700 /* Issue DBGI to exit cpu stall */
2701 aice_usb_halt(coreid
);
2703 /* Read OIPC to find out the trigger point */
2704 uint32_t ir11_value
;
2705 aice_read_reg(coreid
, IR11
, &ir11_value
);
2707 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2708 "CPU is stalled at 0x%08" PRIx32
" for debugging. -->", ir11_value
);
2710 *state
= AICE_TARGET_HALTED
;
2711 } else if ((dbger_value
& NDS_DBGER_CRST
) == NDS_DBGER_CRST
) {
2712 LOG_DEBUG("DBGER.CRST is on.");
2714 *state
= AICE_TARGET_RESET
;
2715 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2718 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
);
2719 } else if ((dbger_value
& NDS_DBGER_DEX
) == NDS_DBGER_DEX
) {
2720 if (AICE_TARGET_RUNNING
== core_info
[coreid
].core_state
) {
2721 /* enter debug mode, init EDM registers */
2722 /* backup EDM registers */
2723 aice_backup_edm_registers(coreid
);
2724 /* init EDM for host debugging */
2725 aice_init_edm_registers(coreid
, true);
2726 aice_backup_tmp_registers(coreid
);
2727 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2728 } else if (AICE_TARGET_UNKNOWN
== core_info
[coreid
].core_state
) {
2729 /* debug 'debug mode', use force debug to halt core */
2730 aice_usb_halt(coreid
);
2732 *state
= AICE_TARGET_HALTED
;
2734 *state
= AICE_TARGET_RUNNING
;
2735 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2741 static int aice_usb_reset(void)
2743 if (aice_reset_box() != ERROR_OK
)
2747 if (custom_trst_script
== NULL
) {
2748 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2749 AICE_JTAG_PIN_CONTROL_TRST
) != ERROR_OK
)
2752 /* custom trst operations */
2753 if (aice_execute_custom_script(custom_trst_script
) != ERROR_OK
)
2757 if (aice_usb_set_clock(jtag_clock
) != ERROR_OK
)
2763 static int aice_issue_srst(uint32_t coreid
)
2765 LOG_DEBUG("aice_issue_srst");
2767 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2768 aice_restore_edm_registers(coreid
);
2770 if (custom_srst_script
== NULL
) {
2771 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2772 AICE_JTAG_PIN_CONTROL_SRST
) != ERROR_OK
)
2775 /* custom srst operations */
2776 if (aice_execute_custom_script(custom_srst_script
) != ERROR_OK
)
2780 /* wait CRST infinitely */
2781 uint32_t dbger_value
;
2784 if (aice_read_misc(coreid
,
2785 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2788 if (dbger_value
& NDS_DBGER_CRST
)
2796 core_info
[coreid
].host_dtr_valid
= false;
2797 core_info
[coreid
].target_dtr_valid
= false;
2799 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2803 static int aice_issue_reset_hold(uint32_t coreid
)
2805 LOG_DEBUG("aice_issue_reset_hold");
2807 /* set no_dbgi_pin to 0 */
2808 uint32_t pin_status
;
2809 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
);
2810 if (pin_status
| 0x4)
2811 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x4));
2814 if (custom_restart_script
== NULL
) {
2815 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2816 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2819 /* custom restart operations */
2820 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2824 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2825 aice_backup_tmp_registers(coreid
);
2826 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2830 /* set no_dbgi_pin to 1 */
2831 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
| 0x4);
2833 /* issue restart again */
2834 if (custom_restart_script
== NULL
) {
2835 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2836 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2839 /* custom restart operations */
2840 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2844 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2845 aice_backup_tmp_registers(coreid
);
2846 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2851 /* do software reset-and-hold */
2852 aice_issue_srst(coreid
);
2853 aice_usb_halt(coreid
);
2856 aice_read_reg(coreid
, IR3
, &value_ir3
);
2857 aice_write_reg(coreid
, PC
, value_ir3
& 0xFFFF0000);
2863 static int aice_issue_reset_hold_multi(void)
2865 uint32_t write_ctrl_value
= 0;
2868 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2869 write_ctrl_value
|= (0x200 << 16);
2870 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2871 write_ctrl_value
) != ERROR_OK
)
2874 for (uint8_t i
= 0 ; i
< total_num_of_core
; i
++)
2875 aice_write_misc(i
, NDS_EDM_MISC_EDM_CMDR
, 0);
2878 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2879 write_ctrl_value
|= (0x200 << 16);
2880 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2881 write_ctrl_value
) != ERROR_OK
)
2884 for (uint8_t i
= 0; i
< total_num_of_core
; i
++)
2890 static int aice_usb_assert_srst(uint32_t coreid
, enum aice_srst_type_s srst
)
2892 if ((AICE_SRST
!= srst
) && (AICE_RESET_HOLD
!= srst
))
2896 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2897 NDS_DBGER_CLEAR_ALL
) != ERROR_OK
)
2900 int result
= ERROR_OK
;
2901 if (AICE_SRST
== srst
)
2902 result
= aice_issue_srst(coreid
);
2904 if (1 == total_num_of_core
)
2905 result
= aice_issue_reset_hold(coreid
);
2907 result
= aice_issue_reset_hold_multi();
2910 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2911 * assert_srst is user-intentional reset behavior, so we could
2912 * clear DBGER.CRST safely.
2914 if (aice_write_misc(coreid
,
2915 NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
) != ERROR_OK
)
2921 static int aice_usb_run(uint32_t coreid
)
2923 LOG_DEBUG("aice_usb_run");
2925 uint32_t dbger_value
;
2926 if (aice_read_misc(coreid
,
2927 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2930 if ((dbger_value
& NDS_DBGER_DEX
) != NDS_DBGER_DEX
) {
2931 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2932 "the debug mode unexpectedly. -->");
2936 /* restore r0 & r1 before free run */
2937 aice_restore_tmp_registers(coreid
);
2938 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2941 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2942 NDS_DBGER_CLEAR_ALL
);
2944 /** restore EDM registers */
2945 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2946 * Otherwise, following instruction will read wrong EDM_CTL value.
2948 * pc -> mfsr $p0, EDM_CTL (single step)
2952 aice_restore_edm_registers(coreid
);
2954 /** execute instructions in DIM */
2955 uint32_t instructions
[4] = {
2961 int result
= aice_execute_dim(coreid
, instructions
, 4);
2966 static int aice_usb_step(uint32_t coreid
)
2968 LOG_DEBUG("aice_usb_step");
2971 uint32_t ir0_reg_num
;
2973 if (is_v2_edm(coreid
) == true)
2974 /* V2 EDM will push interrupt stack as debug exception */
2980 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
2981 if ((ir0_value
& 0x800) == 0) {
2983 ir0_value
|= (0x01 << 11);
2984 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
2987 if (ERROR_FAIL
== aice_usb_run(coreid
))
2991 enum aice_target_state_s state
;
2994 if (aice_usb_state(coreid
, &state
) != ERROR_OK
)
2997 if (AICE_TARGET_HALTED
== state
)
3002 then
= timeval_ms();
3005 if ((timeval_ms() - then
) > 1000)
3006 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
3014 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
3015 ir0_value
&= ~(0x01 << 11);
3016 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
3021 static int aice_usb_read_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3023 return aice_read_mem_b(coreid
, address
, data
);
3026 static int aice_usb_read_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3028 return aice_read_mem_h(coreid
, address
, data
);
3031 static int aice_usb_read_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3033 return aice_read_mem(coreid
, address
, data
);
3036 static int aice_usb_read_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3039 uint32_t instructions
[4] = {
3046 aice_execute_dim(coreid
, instructions
, 4);
3048 aice_read_dtr(coreid
, &value
);
3049 *data
= value
& 0xFF;
3054 static int aice_usb_read_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3057 uint32_t instructions
[4] = {
3064 aice_execute_dim(coreid
, instructions
, 4);
3066 aice_read_dtr(coreid
, &value
);
3067 *data
= value
& 0xFFFF;
3072 static int aice_usb_read_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3074 uint32_t instructions
[4] = {
3081 aice_execute_dim(coreid
, instructions
, 4);
3083 aice_read_dtr(coreid
, data
);
3088 static int aice_usb_set_address_dim(uint32_t coreid
, uint32_t address
)
3090 uint32_t instructions
[4] = {
3091 SETHI(R0
, address
>> 12),
3092 ORI(R0
, R0
, address
& 0x00000FFF),
3097 return aice_execute_dim(coreid
, instructions
, 4);
3100 static int aice_usb_read_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3101 uint32_t count
, uint8_t *buffer
)
3103 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08" PRIx32
3104 ", size: %" PRIu32
", count: %" PRIu32
"",
3107 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3108 aice_usb_set_address_dim(coreid
, addr
);
3112 read_mem_func_t read_mem_func
;
3116 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3117 read_mem_func
= aice_usb_read_mem_b_bus
;
3119 read_mem_func
= aice_usb_read_mem_b_dim
;
3121 for (i
= 0; i
< count
; i
++) {
3122 read_mem_func(coreid
, addr
, &value
);
3123 *buffer
++ = (uint8_t)value
;
3128 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3129 read_mem_func
= aice_usb_read_mem_h_bus
;
3131 read_mem_func
= aice_usb_read_mem_h_dim
;
3133 for (i
= 0; i
< count
; i
++) {
3134 read_mem_func(coreid
, addr
, &value
);
3135 uint16_t svalue
= value
;
3136 memcpy(buffer
, &svalue
, sizeof(uint16_t));
3142 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3143 read_mem_func
= aice_usb_read_mem_w_bus
;
3145 read_mem_func
= aice_usb_read_mem_w_dim
;
3147 for (i
= 0; i
< count
; i
++) {
3148 read_mem_func(coreid
, addr
, &value
);
3149 memcpy(buffer
, &value
, sizeof(uint32_t));
3159 static int aice_usb_write_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3161 return aice_write_mem_b(coreid
, address
, data
);
3164 static int aice_usb_write_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3166 return aice_write_mem_h(coreid
, address
, data
);
3169 static int aice_usb_write_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3171 return aice_write_mem(coreid
, address
, data
);
3174 static int aice_usb_write_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3176 uint32_t instructions
[4] = {
3183 aice_write_dtr(coreid
, data
& 0xFF);
3184 aice_execute_dim(coreid
, instructions
, 4);
3189 static int aice_usb_write_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3191 uint32_t instructions
[4] = {
3198 aice_write_dtr(coreid
, data
& 0xFFFF);
3199 aice_execute_dim(coreid
, instructions
, 4);
3204 static int aice_usb_write_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3206 uint32_t instructions
[4] = {
3213 aice_write_dtr(coreid
, data
);
3214 aice_execute_dim(coreid
, instructions
, 4);
3219 static int aice_usb_write_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3220 uint32_t count
, const uint8_t *buffer
)
3222 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08" PRIx32
3223 ", size: %" PRIu32
", count: %" PRIu32
"",
3226 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3227 aice_usb_set_address_dim(coreid
, addr
);
3230 write_mem_func_t write_mem_func
;
3234 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3235 write_mem_func
= aice_usb_write_mem_b_bus
;
3237 write_mem_func
= aice_usb_write_mem_b_dim
;
3239 for (i
= 0; i
< count
; i
++) {
3240 write_mem_func(coreid
, addr
, *buffer
);
3246 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3247 write_mem_func
= aice_usb_write_mem_h_bus
;
3249 write_mem_func
= aice_usb_write_mem_h_dim
;
3251 for (i
= 0; i
< count
; i
++) {
3253 memcpy(&value
, buffer
, sizeof(uint16_t));
3255 write_mem_func(coreid
, addr
, value
);
3261 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3262 write_mem_func
= aice_usb_write_mem_w_bus
;
3264 write_mem_func
= aice_usb_write_mem_w_dim
;
3266 for (i
= 0; i
< count
; i
++) {
3268 memcpy(&value
, buffer
, sizeof(uint32_t));
3270 write_mem_func(coreid
, addr
, value
);
3280 static int aice_bulk_read_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3283 uint32_t packet_size
;
3286 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3290 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
) != ERROR_OK
)
3293 if (aice_fastread_mem(coreid
, buffer
,
3294 packet_size
) != ERROR_OK
)
3297 buffer
+= (packet_size
* 4);
3298 addr
+= (packet_size
* 4);
3299 count
-= packet_size
;
3305 static int aice_bulk_write_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3306 const uint8_t *buffer
)
3308 uint32_t packet_size
;
3311 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3315 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
| 1) != ERROR_OK
)
3318 if (aice_fastwrite_mem(coreid
, buffer
,
3319 packet_size
) != ERROR_OK
)
3322 buffer
+= (packet_size
* 4);
3323 addr
+= (packet_size
* 4);
3324 count
-= packet_size
;
3330 static int aice_usb_bulk_read_mem(uint32_t coreid
, uint32_t addr
,
3331 uint32_t length
, uint8_t *buffer
)
3333 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08" PRIx32
", length: 0x%08" PRIx32
, addr
, length
);
3337 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3338 aice_usb_set_address_dim(coreid
, addr
);
3340 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3341 retval
= aice_usb_read_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3343 retval
= aice_bulk_read_mem(coreid
, addr
, length
/ 4, buffer
);
3348 static int aice_usb_bulk_write_mem(uint32_t coreid
, uint32_t addr
,
3349 uint32_t length
, const uint8_t *buffer
)
3351 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08" PRIx32
", length: 0x%08" PRIx32
, addr
, length
);
3355 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3356 aice_usb_set_address_dim(coreid
, addr
);
3358 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3359 retval
= aice_usb_write_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3361 retval
= aice_bulk_write_mem(coreid
, addr
, length
/ 4, buffer
);
3366 static int aice_usb_read_debug_reg(uint32_t coreid
, uint32_t addr
, uint32_t *val
)
3368 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3369 if (NDS_EDM_SR_EDMSW
== addr
) {
3370 *val
= core_info
[coreid
].edmsw_backup
;
3371 } else if (NDS_EDM_SR_EDM_DTR
== addr
) {
3372 if (core_info
[coreid
].target_dtr_valid
) {
3373 /* if EDM_DTR has read out, clear it. */
3374 *val
= core_info
[coreid
].target_dtr_backup
;
3375 core_info
[coreid
].edmsw_backup
&= (~0x1);
3376 core_info
[coreid
].target_dtr_valid
= false;
3383 return aice_read_edmsr(coreid
, addr
, val
);
3386 static int aice_usb_write_debug_reg(uint32_t coreid
, uint32_t addr
, const uint32_t val
)
3388 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3389 if (NDS_EDM_SR_EDM_DTR
== addr
) {
3390 core_info
[coreid
].host_dtr_backup
= val
;
3391 core_info
[coreid
].edmsw_backup
|= 0x2;
3392 core_info
[coreid
].host_dtr_valid
= true;
3396 return aice_write_edmsr(coreid
, addr
, val
);
3399 static int aice_usb_memory_access(uint32_t coreid
, enum nds_memory_access channel
)
3401 LOG_DEBUG("aice_usb_memory_access, access channel: %u", channel
);
3403 core_info
[coreid
].access_channel
= channel
;
3408 static int aice_usb_memory_mode(uint32_t coreid
, enum nds_memory_select mem_select
)
3410 if (core_info
[coreid
].memory_select
== mem_select
)
3413 LOG_DEBUG("aice_usb_memory_mode, memory select: %u", mem_select
);
3415 core_info
[coreid
].memory_select
= mem_select
;
3417 if (NDS_MEMORY_SELECT_AUTO
!= core_info
[coreid
].memory_select
)
3418 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3419 core_info
[coreid
].memory_select
- 1);
3421 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3422 NDS_MEMORY_SELECT_MEM
- 1);
3427 static int aice_usb_read_tlb(uint32_t coreid
, uint32_t virtual_address
,
3428 uint32_t *physical_address
)
3430 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08" PRIx32
, virtual_address
);
3432 uint32_t instructions
[4];
3433 uint32_t probe_result
;
3436 uint32_t access_page_size
;
3437 uint32_t virtual_offset
;
3438 uint32_t physical_page_number
;
3440 aice_write_dtr(coreid
, virtual_address
);
3442 /* probe TLB first */
3443 instructions
[0] = MFSR_DTR(R0
);
3444 instructions
[1] = TLBOP_TARGET_PROBE(R1
, R0
);
3445 instructions
[2] = DSB
;
3446 instructions
[3] = BEQ_MINUS_12
;
3447 aice_execute_dim(coreid
, instructions
, 4);
3449 aice_read_reg(coreid
, R1
, &probe_result
);
3451 if (probe_result
& 0x80000000)
3454 /* read TLB entry */
3455 aice_write_dtr(coreid
, probe_result
& 0x7FF);
3457 /* probe TLB first */
3458 instructions
[0] = MFSR_DTR(R0
);
3459 instructions
[1] = TLBOP_TARGET_READ(R0
);
3460 instructions
[2] = DSB
;
3461 instructions
[3] = BEQ_MINUS_12
;
3462 aice_execute_dim(coreid
, instructions
, 4);
3464 /* TODO: it should backup mr3, mr4 */
3465 aice_read_reg(coreid
, MR3
, &value_mr3
);
3466 aice_read_reg(coreid
, MR4
, &value_mr4
);
3468 access_page_size
= value_mr4
& 0xF;
3469 if (0 == access_page_size
) { /* 4K page */
3470 virtual_offset
= virtual_address
& 0x00000FFF;
3471 physical_page_number
= value_mr3
& 0xFFFFF000;
3472 } else if (1 == access_page_size
) { /* 8K page */
3473 virtual_offset
= virtual_address
& 0x00001FFF;
3474 physical_page_number
= value_mr3
& 0xFFFFE000;
3475 } else if (5 == access_page_size
) { /* 1M page */
3476 virtual_offset
= virtual_address
& 0x000FFFFF;
3477 physical_page_number
= value_mr3
& 0xFFF00000;
3482 *physical_address
= physical_page_number
| virtual_offset
;
3487 static int aice_usb_init_cache(uint32_t coreid
)
3489 LOG_DEBUG("aice_usb_init_cache");
3494 aice_read_reg(coreid
, CR1
, &value_cr1
);
3495 aice_read_reg(coreid
, CR2
, &value_cr2
);
3497 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3499 icache
->set
= value_cr1
& 0x7;
3500 icache
->log2_set
= icache
->set
+ 6;
3501 icache
->set
= 64 << icache
->set
;
3502 icache
->way
= ((value_cr1
>> 3) & 0x7) + 1;
3503 icache
->line_size
= (value_cr1
>> 6) & 0x7;
3504 if (icache
->line_size
!= 0) {
3505 icache
->log2_line_size
= icache
->line_size
+ 2;
3506 icache
->line_size
= 8 << (icache
->line_size
- 1);
3508 icache
->log2_line_size
= 0;
3511 LOG_DEBUG("\ticache set: %" PRIu32
", way: %" PRIu32
", line size: %" PRIu32
", "
3512 "log2(set): %" PRIu32
", log2(line_size): %" PRIu32
"",
3513 icache
->set
, icache
->way
, icache
->line_size
,
3514 icache
->log2_set
, icache
->log2_line_size
);
3516 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3518 dcache
->set
= value_cr2
& 0x7;
3519 dcache
->log2_set
= dcache
->set
+ 6;
3520 dcache
->set
= 64 << dcache
->set
;
3521 dcache
->way
= ((value_cr2
>> 3) & 0x7) + 1;
3522 dcache
->line_size
= (value_cr2
>> 6) & 0x7;
3523 if (dcache
->line_size
!= 0) {
3524 dcache
->log2_line_size
= dcache
->line_size
+ 2;
3525 dcache
->line_size
= 8 << (dcache
->line_size
- 1);
3527 dcache
->log2_line_size
= 0;
3530 LOG_DEBUG("\tdcache set: %" PRIu32
", way: %" PRIu32
", line size: %" PRIu32
", "
3531 "log2(set): %" PRIu32
", log2(line_size): %" PRIu32
"",
3532 dcache
->set
, dcache
->way
, dcache
->line_size
,
3533 dcache
->log2_set
, dcache
->log2_line_size
);
3535 core_info
[coreid
].cache_init
= true;
3540 static int aice_usb_dcache_inval_all(uint32_t coreid
)
3542 LOG_DEBUG("aice_usb_dcache_inval_all");
3546 uint32_t cache_index
;
3547 uint32_t instructions
[4];
3549 instructions
[0] = MFSR_DTR(R0
);
3550 instructions
[1] = L1D_IX_INVAL(R0
);
3551 instructions
[2] = DSB
;
3552 instructions
[3] = BEQ_MINUS_12
;
3554 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3556 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3557 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3558 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3559 (set_index
<< dcache
->log2_line_size
);
3561 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3564 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3572 static int aice_usb_dcache_va_inval(uint32_t coreid
, uint32_t address
)
3574 LOG_DEBUG("aice_usb_dcache_va_inval");
3576 uint32_t instructions
[4];
3578 aice_write_dtr(coreid
, address
);
3580 instructions
[0] = MFSR_DTR(R0
);
3581 instructions
[1] = L1D_VA_INVAL(R0
);
3582 instructions
[2] = DSB
;
3583 instructions
[3] = BEQ_MINUS_12
;
3585 return aice_execute_dim(coreid
, instructions
, 4);
3588 static int aice_usb_dcache_wb_all(uint32_t coreid
)
3590 LOG_DEBUG("aice_usb_dcache_wb_all");
3594 uint32_t cache_index
;
3595 uint32_t instructions
[4];
3597 instructions
[0] = MFSR_DTR(R0
);
3598 instructions
[1] = L1D_IX_WB(R0
);
3599 instructions
[2] = DSB
;
3600 instructions
[3] = BEQ_MINUS_12
;
3602 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3604 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3605 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3606 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3607 (set_index
<< dcache
->log2_line_size
);
3609 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3612 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3620 static int aice_usb_dcache_va_wb(uint32_t coreid
, uint32_t address
)
3622 LOG_DEBUG("aice_usb_dcache_va_wb");
3624 uint32_t instructions
[4];
3626 aice_write_dtr(coreid
, address
);
3628 instructions
[0] = MFSR_DTR(R0
);
3629 instructions
[1] = L1D_VA_WB(R0
);
3630 instructions
[2] = DSB
;
3631 instructions
[3] = BEQ_MINUS_12
;
3633 return aice_execute_dim(coreid
, instructions
, 4);
3636 static int aice_usb_icache_inval_all(uint32_t coreid
)
3638 LOG_DEBUG("aice_usb_icache_inval_all");
3642 uint32_t cache_index
;
3643 uint32_t instructions
[4];
3645 instructions
[0] = MFSR_DTR(R0
);
3646 instructions
[1] = L1I_IX_INVAL(R0
);
3647 instructions
[2] = ISB
;
3648 instructions
[3] = BEQ_MINUS_12
;
3650 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3652 for (set_index
= 0; set_index
< icache
->set
; set_index
++) {
3653 for (way_index
= 0; way_index
< icache
->way
; way_index
++) {
3654 cache_index
= (way_index
<< (icache
->log2_set
+ icache
->log2_line_size
)) |
3655 (set_index
<< icache
->log2_line_size
);
3657 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3660 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3668 static int aice_usb_icache_va_inval(uint32_t coreid
, uint32_t address
)
3670 LOG_DEBUG("aice_usb_icache_va_inval");
3672 uint32_t instructions
[4];
3674 aice_write_dtr(coreid
, address
);
3676 instructions
[0] = MFSR_DTR(R0
);
3677 instructions
[1] = L1I_VA_INVAL(R0
);
3678 instructions
[2] = ISB
;
3679 instructions
[3] = BEQ_MINUS_12
;
3681 return aice_execute_dim(coreid
, instructions
, 4);
3684 static int aice_usb_cache_ctl(uint32_t coreid
, uint32_t subtype
, uint32_t address
)
3686 LOG_DEBUG("aice_usb_cache_ctl");
3690 if (core_info
[coreid
].cache_init
== false)
3691 aice_usb_init_cache(coreid
);
3694 case AICE_CACHE_CTL_L1D_INVALALL
:
3695 result
= aice_usb_dcache_inval_all(coreid
);
3697 case AICE_CACHE_CTL_L1D_VA_INVAL
:
3698 result
= aice_usb_dcache_va_inval(coreid
, address
);
3700 case AICE_CACHE_CTL_L1D_WBALL
:
3701 result
= aice_usb_dcache_wb_all(coreid
);
3703 case AICE_CACHE_CTL_L1D_VA_WB
:
3704 result
= aice_usb_dcache_va_wb(coreid
, address
);
3706 case AICE_CACHE_CTL_L1I_INVALALL
:
3707 result
= aice_usb_icache_inval_all(coreid
);
3709 case AICE_CACHE_CTL_L1I_VA_INVAL
:
3710 result
= aice_usb_icache_va_inval(coreid
, address
);
3713 result
= ERROR_FAIL
;
3720 static int aice_usb_set_retry_times(uint32_t a_retry_times
)
3722 aice_max_retry_times
= a_retry_times
;
3726 static int aice_usb_program_edm(uint32_t coreid
, char *command_sequence
)
3731 uint32_t data_value
;
3735 command_str
= strtok(command_sequence
, ";");
3736 if (command_str
== NULL
)
3741 /* process one command */
3742 while (command_str
[i
] == ' ' ||
3743 command_str
[i
] == '\n' ||
3744 command_str
[i
] == '\r' ||
3745 command_str
[i
] == '\t')
3748 /* skip ' ', '\r', '\n', '\t' */
3749 command_str
= command_str
+ i
;
3751 if (strncmp(command_str
, "write_misc", 10) == 0) {
3752 reg_name_0
= strstr(command_str
, "gen_port0");
3753 reg_name_1
= strstr(command_str
, "gen_port1");
3755 if (reg_name_0
!= NULL
) {
3756 data_value
= strtoul(reg_name_0
+ 9, NULL
, 0);
3758 if (aice_write_misc(coreid
,
3759 NDS_EDM_MISC_GEN_PORT0
, data_value
) != ERROR_OK
)
3762 } else if (reg_name_1
!= NULL
) {
3763 data_value
= strtoul(reg_name_1
+ 9, NULL
, 0);
3765 if (aice_write_misc(coreid
,
3766 NDS_EDM_MISC_GEN_PORT1
, data_value
) != ERROR_OK
)
3769 LOG_ERROR("program EDM, unsupported misc register: %s", command_str
);
3772 LOG_ERROR("program EDM, unsupported command: %s", command_str
);
3775 /* update command_str */
3776 command_str
= strtok(NULL
, ";");
3778 } while (command_str
!= NULL
);
3783 static int aice_usb_set_command_mode(enum aice_command_mode command_mode
)
3785 int retval
= ERROR_OK
;
3787 /* flush usb_packets_buffer as users change mode */
3788 retval
= aice_usb_packet_flush();
3790 if (AICE_COMMAND_MODE_BATCH
== command_mode
) {
3791 /* reset batch buffer */
3792 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3793 retval
= aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL
, 0x40000);
3796 aice_command_mode
= command_mode
;
3801 static int aice_usb_execute(uint32_t coreid
, uint32_t *instructions
,
3802 uint32_t instruction_num
)
3805 uint8_t current_instruction_num
;
3806 uint32_t dim_instructions
[4] = {NOP
, NOP
, NOP
, BEQ_MINUS_12
};
3808 /* To execute 4 instructions as a special case */
3809 if (instruction_num
== 4)
3810 return aice_execute_dim(coreid
, instructions
, 4);
3812 for (i
= 0 ; i
< instruction_num
; i
+= 3) {
3813 if (instruction_num
- i
< 3) {
3814 current_instruction_num
= instruction_num
- i
;
3815 for (j
= current_instruction_num
; j
< 3 ; j
++)
3816 dim_instructions
[j
] = NOP
;
3818 current_instruction_num
= 3;
3821 memcpy(dim_instructions
, instructions
+ i
,
3822 current_instruction_num
* sizeof(uint32_t));
3825 if (aice_write_dim(coreid
,
3830 /** clear DBGER.DPED */
3831 if (aice_write_misc(coreid
,
3832 NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
3836 if (aice_do_execute(coreid
) != ERROR_OK
)
3839 /** check DBGER.DPED */
3840 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
3842 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3843 "0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
". -->",
3844 dim_instructions
[0],
3845 dim_instructions
[1],
3846 dim_instructions
[2],
3847 dim_instructions
[3]);
3855 static int aice_usb_set_custom_srst_script(const char *script
)
3857 custom_srst_script
= strdup(script
);
3862 static int aice_usb_set_custom_trst_script(const char *script
)
3864 custom_trst_script
= strdup(script
);
3869 static int aice_usb_set_custom_restart_script(const char *script
)
3871 custom_restart_script
= strdup(script
);
3876 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check
)
3878 aice_count_to_check_dbger
= count_to_check
;
3883 static int aice_usb_set_data_endian(uint32_t coreid
,
3884 enum aice_target_endian target_data_endian
)
3886 data_endian
= target_data_endian
;
3891 static int fill_profiling_batch_commands(uint32_t coreid
, uint32_t reg_no
)
3893 uint32_t dim_instructions
[4];
3895 aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH
);
3898 if (aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0) != ERROR_OK
)
3902 dim_instructions
[0] = MTSR_DTR(0);
3903 dim_instructions
[1] = DSB
;
3904 dim_instructions
[2] = NOP
;
3905 dim_instructions
[3] = BEQ_MINUS_12
;
3906 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3908 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3911 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(reg_no
)) {
3912 /* general registers */
3913 dim_instructions
[0] = MTSR_DTR(reg_no
);
3914 dim_instructions
[1] = DSB
;
3915 dim_instructions
[2] = NOP
;
3916 dim_instructions
[3] = BEQ_MINUS_12
;
3917 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(reg_no
)) {
3918 /* user special registers */
3919 dim_instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no
));
3920 dim_instructions
[1] = MTSR_DTR(0);
3921 dim_instructions
[2] = DSB
;
3922 dim_instructions
[3] = BEQ_MINUS_12
;
3923 } else { /* system registers */
3924 dim_instructions
[0] = MFSR(0, nds32_reg_sr_index(reg_no
));
3925 dim_instructions
[1] = MTSR_DTR(0);
3926 dim_instructions
[2] = DSB
;
3927 dim_instructions
[3] = BEQ_MINUS_12
;
3929 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3931 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_1
);
3934 aice_write_dtr_from_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3935 dim_instructions
[0] = MFSR_DTR(0);
3936 dim_instructions
[1] = DSB
;
3937 dim_instructions
[2] = NOP
;
3938 dim_instructions
[3] = IRET
; /* free run */
3939 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3942 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3944 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
3945 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
3946 usb_out_packets_buffer
,
3947 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
3950 usb_out_packets_buffer_length
= 0;
3951 usb_in_packets_buffer_length
= 0;
3956 static int aice_usb_profiling(uint32_t coreid
, uint32_t interval
, uint32_t iteration
,
3957 uint32_t reg_no
, uint32_t *samples
, uint32_t *num_samples
)
3959 uint32_t iteration_count
;
3960 uint32_t this_iteration
;
3961 int retval
= ERROR_OK
;
3962 const uint32_t MAX_ITERATION
= 250;
3967 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE
, 4) != ERROR_OK
)
3970 /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR.
3971 * Set it to circular buffer */
3972 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL
, 0xC0000) != ERROR_OK
)
3975 fill_profiling_batch_commands(coreid
, reg_no
);
3977 iteration_count
= 0;
3978 while (iteration_count
< iteration
) {
3979 if (iteration
- iteration_count
< MAX_ITERATION
)
3980 this_iteration
= iteration
- iteration_count
;
3982 this_iteration
= MAX_ITERATION
;
3984 /* set number of iterations */
3985 uint32_t val_iteration
;
3986 val_iteration
= interval
<< 16 | this_iteration
;
3987 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION
,
3988 val_iteration
) != ERROR_OK
) {
3989 retval
= ERROR_FAIL
;
3993 /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */
3994 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL
,
3995 0x40000) != ERROR_OK
) {
3996 retval
= ERROR_FAIL
;
4000 aice_usb_run(coreid
);
4002 /* enable BATCH command */
4003 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
,
4004 0x80000000) != ERROR_OK
) {
4005 aice_usb_halt(coreid
);
4006 retval
= ERROR_FAIL
;
4010 /* wait a while (AICE bug, workaround) */
4011 alive_sleep(this_iteration
);
4015 uint32_t batch_status
;
4019 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
4021 if (batch_status
& 0x1) {
4023 } else if (batch_status
& 0xE) {
4024 aice_usb_halt(coreid
);
4025 retval
= ERROR_FAIL
;
4035 aice_usb_halt(coreid
);
4037 /* get samples from batch data buffer */
4038 if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1
,
4039 samples
+ iteration_count
, this_iteration
) != ERROR_OK
) {
4040 retval
= ERROR_FAIL
;
4044 iteration_count
+= this_iteration
;
4048 *num_samples
= iteration_count
;
4054 struct aice_port_api_s aice_usb_api
= {
4056 .open
= aice_open_device
,
4058 .close
= aice_usb_close
,
4060 .idcode
= aice_usb_idcode
,
4062 .state
= aice_usb_state
,
4064 .reset
= aice_usb_reset
,
4066 .assert_srst
= aice_usb_assert_srst
,
4068 .run
= aice_usb_run
,
4070 .halt
= aice_usb_halt
,
4072 .step
= aice_usb_step
,
4074 .read_reg
= aice_usb_read_reg
,
4076 .write_reg
= aice_usb_write_reg
,
4078 .read_reg_64
= aice_usb_read_reg_64
,
4080 .write_reg_64
= aice_usb_write_reg_64
,
4082 .read_mem_unit
= aice_usb_read_memory_unit
,
4084 .write_mem_unit
= aice_usb_write_memory_unit
,
4086 .read_mem_bulk
= aice_usb_bulk_read_mem
,
4088 .write_mem_bulk
= aice_usb_bulk_write_mem
,
4090 .read_debug_reg
= aice_usb_read_debug_reg
,
4092 .write_debug_reg
= aice_usb_write_debug_reg
,
4094 .set_jtag_clock
= aice_usb_set_jtag_clock
,
4096 .memory_access
= aice_usb_memory_access
,
4098 .memory_mode
= aice_usb_memory_mode
,
4100 .read_tlb
= aice_usb_read_tlb
,
4102 .cache_ctl
= aice_usb_cache_ctl
,
4104 .set_retry_times
= aice_usb_set_retry_times
,
4106 .program_edm
= aice_usb_program_edm
,
4108 .set_command_mode
= aice_usb_set_command_mode
,
4110 .execute
= aice_usb_execute
,
4112 .set_custom_srst_script
= aice_usb_set_custom_srst_script
,
4114 .set_custom_trst_script
= aice_usb_set_custom_trst_script
,
4116 .set_custom_restart_script
= aice_usb_set_custom_restart_script
,
4118 .set_count_to_check_dbger
= aice_usb_set_count_to_check_dbger
,
4120 .set_data_endian
= aice_usb_set_data_endian
,
4122 .profiling
= aice_usb_profiling
,