1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
31 NRF5_FLASH_BASE
= 0x00000000,
34 enum nrf5_ficr_registers
{
35 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
37 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
39 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
40 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
41 NRF5_FICR_CLENR0
= NRF5_FICR_REG(0x028),
42 NRF5_FICR_PPFC
= NRF5_FICR_REG(0x02C),
43 NRF5_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
44 NRF5_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
45 NRF5_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
46 NRF5_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
47 NRF5_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
48 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
49 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
50 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
51 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
52 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
53 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
54 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
55 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
56 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
57 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
58 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
59 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
60 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
61 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
62 NRF5_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
63 NRF5_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
64 NRF5_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
65 NRF5_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
66 NRF5_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
67 NRF5_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
68 NRF5_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
69 NRF5_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
70 NRF5_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
71 NRF5_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
72 NRF5_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
75 enum nrf5_uicr_registers
{
76 NRF5_UICR_BASE
= 0x10001000, /* User Information
77 * Configuration Regsters */
79 NRF5_UICR_SIZE
= 0x100,
81 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
83 NRF5_UICR_CLENR0
= NRF5_UICR_REG(0x000),
84 NRF5_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
85 NRF5_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
86 NRF5_UICR_FWID
= NRF5_UICR_REG(0x010),
89 enum nrf5_nvmc_registers
{
90 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
91 * Controller Regsters */
93 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
95 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
96 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
97 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
98 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
99 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
102 enum nrf5_nvmc_config_bits
{
103 NRF5_NVMC_CONFIG_REN
= 0x00,
104 NRF5_NVMC_CONFIG_WEN
= 0x01,
105 NRF5_NVMC_CONFIG_EEN
= 0x02,
110 uint32_t code_page_size
;
114 int (*write
) (struct flash_bank
*bank
,
115 struct nrf5_info
*chip
,
116 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
118 struct target
*target
;
121 struct nrf5_device_spec
{
125 const char *build_code
;
126 unsigned int flash_size_kb
;
129 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
134 .build_code = bcode, \
135 .flash_size_kb = (fsize), \
138 /* The known devices table below is derived from the "nRF51 Series
139 * Compatibility Matrix" document, which can be found by searching for
140 * ATTN-51 on the Nordic Semi website:
142 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
144 * Up to date with Matrix v2.0, plus some additional HWIDs.
146 * The additional HWIDs apply where the build code in the matrix is
147 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
148 * for x==0, x!=0 means different (unspecified) HWIDs.
150 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
151 /* nRF51822 Devices (IC rev 1). */
152 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
153 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
154 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
155 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
156 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
158 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
159 with built-in jlink seem to use engineering samples not listed
160 in the nRF51 Series Compatibility Matrix V1.0. */
161 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
163 /* nRF51822 Devices (IC rev 2). */
164 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
165 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
166 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
167 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
168 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
169 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
170 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
171 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
172 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
174 /* nRF51822 Devices (IC rev 3). */
175 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
176 NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
177 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
178 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
179 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
180 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
181 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
182 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
183 NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
185 /* nRF51422 Devices (IC rev 1). */
186 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
187 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
188 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
190 /* nRF51422 Devices (IC rev 2). */
191 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
192 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
193 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
194 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
196 /* nRF51422 Devices (IC rev 3). */
197 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
198 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
199 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
200 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
201 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
202 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
203 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
205 /* nRF52832 Devices */
206 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
209 static int nrf5_bank_is_probed(struct flash_bank
*bank
)
211 struct nrf5_info
*chip
= bank
->driver_priv
;
213 assert(chip
!= NULL
);
215 return chip
->bank
[bank
->bank_number
].probed
;
217 static int nrf5_probe(struct flash_bank
*bank
);
219 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
221 if (bank
->target
->state
!= TARGET_HALTED
) {
222 LOG_ERROR("Target not halted");
223 return ERROR_TARGET_NOT_HALTED
;
226 *chip
= bank
->driver_priv
;
228 int probed
= nrf5_bank_is_probed(bank
);
232 return nrf5_probe(bank
);
237 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
244 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
245 if (res
!= ERROR_OK
) {
246 LOG_ERROR("Couldn't read NVMC_READY register");
250 if (ready
== 0x00000001)
256 LOG_DEBUG("Timed out waiting for NVMC_READY");
257 return ERROR_FLASH_BUSY
;
260 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
263 res
= target_write_u32(chip
->target
,
265 NRF5_NVMC_CONFIG_EEN
);
267 if (res
!= ERROR_OK
) {
268 LOG_ERROR("Failed to enable erase operation");
273 According to NVMC examples in Nordic SDK busy status must be
274 checked after writing to NVMC_CONFIG
276 res
= nrf5_wait_for_nvmc(chip
);
278 LOG_ERROR("Erase enable did not complete");
283 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
286 res
= target_write_u32(chip
->target
,
288 NRF5_NVMC_CONFIG_WEN
);
290 if (res
!= ERROR_OK
) {
291 LOG_ERROR("Failed to enable write operation");
296 According to NVMC examples in Nordic SDK busy status must be
297 checked after writing to NVMC_CONFIG
299 res
= nrf5_wait_for_nvmc(chip
);
301 LOG_ERROR("Write enable did not complete");
306 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
309 res
= target_write_u32(chip
->target
,
311 NRF5_NVMC_CONFIG_REN
);
313 if (res
!= ERROR_OK
) {
314 LOG_ERROR("Failed to enable read-only operation");
318 According to NVMC examples in Nordic SDK busy status must be
319 checked after writing to NVMC_CONFIG
321 res
= nrf5_wait_for_nvmc(chip
);
323 LOG_ERROR("Read only enable did not complete");
328 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
329 uint32_t erase_register
, uint32_t erase_value
)
333 res
= nrf5_nvmc_erase_enable(chip
);
337 res
= target_write_u32(chip
->target
,
343 res
= nrf5_wait_for_nvmc(chip
);
347 return nrf5_nvmc_read_only(chip
);
350 nrf5_nvmc_read_only(chip
);
352 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
353 erase_register
, erase_value
);
357 static int nrf5_protect_check(struct flash_bank
*bank
)
362 /* UICR cannot be write protected so just return early */
363 if (bank
->base
== NRF5_UICR_BASE
)
366 struct nrf5_info
*chip
= bank
->driver_priv
;
368 assert(chip
!= NULL
);
370 res
= target_read_u32(chip
->target
, NRF5_FICR_CLENR0
,
372 if (res
!= ERROR_OK
) {
373 LOG_ERROR("Couldn't read code region 0 size[FICR]");
377 if (clenr0
== 0xFFFFFFFF) {
378 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
380 if (res
!= ERROR_OK
) {
381 LOG_ERROR("Couldn't read code region 0 size[UICR]");
386 for (int i
= 0; i
< bank
->num_sectors
; i
++)
387 bank
->sectors
[i
].is_protected
=
388 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
393 static int nrf5_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
396 uint32_t clenr0
, ppfc
;
397 struct nrf5_info
*chip
;
399 /* UICR cannot be write protected so just bail out early */
400 if (bank
->base
== NRF5_UICR_BASE
)
403 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
408 LOG_ERROR("Code region 0 must start at the begining of the bank");
412 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
414 if (res
!= ERROR_OK
) {
415 LOG_ERROR("Couldn't read PPFC register");
419 if ((ppfc
& 0xFF) == 0x00) {
420 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
424 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
426 if (res
!= ERROR_OK
) {
427 LOG_ERROR("Couldn't read code region 0 size[UICR]");
431 if (clenr0
== 0xFFFFFFFF) {
432 res
= target_write_u32(chip
->target
, NRF5_UICR_CLENR0
,
434 if (res
!= ERROR_OK
) {
435 LOG_ERROR("Couldn't write code region 0 size[UICR]");
440 LOG_ERROR("You need to perform chip erase before changing the protection settings");
443 nrf5_protect_check(bank
);
448 static int nrf5_probe(struct flash_bank
*bank
)
452 struct nrf5_info
*chip
= bank
->driver_priv
;
454 res
= target_read_u32(chip
->target
, NRF5_FICR_CONFIGID
, &hwid
);
455 if (res
!= ERROR_OK
) {
456 LOG_ERROR("Couldn't read CONFIGID register");
460 hwid
&= 0xFFFF; /* HWID is stored in the lower two
461 * bytes of the CONFIGID register */
463 const struct nrf5_device_spec
*spec
= NULL
;
464 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
465 if (hwid
== nrf5_known_devices_table
[i
].hwid
) {
466 spec
= &nrf5_known_devices_table
[i
];
471 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
473 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
474 spec
->part
, spec
->variant
, spec
->build_code
,
475 spec
->flash_size_kb
);
477 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
480 if (bank
->base
== NRF5_FLASH_BASE
) {
481 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
482 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
483 &chip
->code_page_size
);
484 if (res
!= ERROR_OK
) {
485 LOG_ERROR("Couldn't read code page size");
489 /* Note the register name is misleading,
490 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
491 uint32_t num_sectors
;
492 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
493 if (res
!= ERROR_OK
) {
494 LOG_ERROR("Couldn't read code memory size");
498 bank
->num_sectors
= num_sectors
;
499 bank
->size
= num_sectors
* chip
->code_page_size
;
501 if (spec
&& bank
->size
/ 1024 != spec
->flash_size_kb
)
502 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
504 bank
->sectors
= calloc(bank
->num_sectors
,
505 sizeof((bank
->sectors
)[0]));
507 return ERROR_FLASH_BANK_NOT_PROBED
;
509 /* Fill out the sector information: all NRF5 sectors are the same size and
510 * there is always a fixed number of them. */
511 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
512 bank
->sectors
[i
].size
= chip
->code_page_size
;
513 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
515 /* mark as unknown */
516 bank
->sectors
[i
].is_erased
= -1;
517 bank
->sectors
[i
].is_protected
= -1;
520 nrf5_protect_check(bank
);
522 chip
->bank
[0].probed
= true;
524 bank
->size
= NRF5_UICR_SIZE
;
525 bank
->num_sectors
= 1;
526 bank
->sectors
= calloc(bank
->num_sectors
,
527 sizeof((bank
->sectors
)[0]));
529 return ERROR_FLASH_BANK_NOT_PROBED
;
531 bank
->sectors
[0].size
= bank
->size
;
532 bank
->sectors
[0].offset
= 0;
534 bank
->sectors
[0].is_erased
= 0;
535 bank
->sectors
[0].is_protected
= 0;
537 chip
->bank
[1].probed
= true;
543 static int nrf5_auto_probe(struct flash_bank
*bank
)
545 int probed
= nrf5_bank_is_probed(bank
);
552 return nrf5_probe(bank
);
555 static int nrf5_erase_all(struct nrf5_info
*chip
)
557 LOG_DEBUG("Erasing all non-volatile memory");
558 return nrf5_nvmc_generic_erase(chip
,
563 static int nrf5_erase_page(struct flash_bank
*bank
,
564 struct nrf5_info
*chip
,
565 struct flash_sector
*sector
)
569 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
570 if (sector
->is_protected
) {
571 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
575 if (bank
->base
== NRF5_UICR_BASE
) {
577 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
579 if (res
!= ERROR_OK
) {
580 LOG_ERROR("Couldn't read PPFC register");
584 if ((ppfc
& 0xFF) == 0xFF) {
585 /* We can't erase the UICR. Double-check to
586 see if it's already erased before complaining. */
587 default_flash_blank_check(bank
);
588 if (sector
->is_erased
== 1)
591 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
595 res
= nrf5_nvmc_generic_erase(chip
,
601 res
= nrf5_nvmc_generic_erase(chip
,
609 static const uint8_t nrf5_flash_write_code
[] = {
610 /* See contrib/loaders/flash/cortex-m0.S */
612 0x0d, 0x68, /* ldr r5, [r1, #0] */
613 0x00, 0x2d, /* cmp r5, #0 */
614 0x0b, 0xd0, /* beq.n 1e <exit> */
615 0x4c, 0x68, /* ldr r4, [r1, #4] */
616 0xac, 0x42, /* cmp r4, r5 */
617 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
618 0x20, 0xcc, /* ldmia r4!, {r5} */
619 0x20, 0xc3, /* stmia r3!, {r5} */
620 0x94, 0x42, /* cmp r4, r2 */
621 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
622 0x0c, 0x46, /* mov r4, r1 */
623 0x08, 0x34, /* adds r4, #8 */
625 0x4c, 0x60, /* str r4, [r1, #4] */
626 0x04, 0x38, /* subs r0, #4 */
627 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
629 0x00, 0xbe /* bkpt 0x0000 */
633 /* Start a low level flash write for the specified region */
634 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
636 struct target
*target
= chip
->target
;
637 uint32_t buffer_size
= 8192;
638 struct working_area
*write_algorithm
;
639 struct working_area
*source
;
640 uint32_t address
= NRF5_FLASH_BASE
+ offset
;
641 struct reg_param reg_params
[4];
642 struct armv7m_algorithm armv7m_info
;
643 int retval
= ERROR_OK
;
646 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
647 assert(bytes
% 4 == 0);
649 /* allocate working area with flash programming code */
650 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
651 &write_algorithm
) != ERROR_OK
) {
652 LOG_WARNING("no working area available, falling back to slow memory writes");
654 for (; bytes
> 0; bytes
-= 4) {
655 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
656 if (retval
!= ERROR_OK
)
659 retval
= nrf5_wait_for_nvmc(chip
);
660 if (retval
!= ERROR_OK
)
670 LOG_WARNING("using fast async flash loader. This is currently supported");
671 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
672 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
674 retval
= target_write_buffer(target
, write_algorithm
->address
,
675 sizeof(nrf5_flash_write_code
),
676 nrf5_flash_write_code
);
677 if (retval
!= ERROR_OK
)
681 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
683 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
684 if (buffer_size
<= 256) {
685 /* free working area, write algorithm already allocated */
686 target_free_working_area(target
, write_algorithm
);
688 LOG_WARNING("No large enough working area available, can't do block memory writes");
689 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
693 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
694 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
696 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
697 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
698 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
699 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
701 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
702 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
703 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
704 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
706 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
709 source
->address
, source
->size
,
710 write_algorithm
->address
, 0,
713 target_free_working_area(target
, source
);
714 target_free_working_area(target
, write_algorithm
);
716 destroy_reg_param(®_params
[0]);
717 destroy_reg_param(®_params
[1]);
718 destroy_reg_param(®_params
[2]);
719 destroy_reg_param(®_params
[3]);
724 /* Check and erase flash sectors in specified range then start a low level page write.
725 start/end must be sector aligned.
727 static int nrf5_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
729 int res
= ERROR_FAIL
;
730 struct nrf5_info
*chip
= bank
->driver_priv
;
732 assert(start
% chip
->code_page_size
== 0);
733 assert(end
% chip
->code_page_size
== 0);
735 res
= nrf5_nvmc_write_enable(chip
);
739 res
= nrf5_ll_flash_write(chip
, start
, buffer
, (end
- start
));
743 return nrf5_nvmc_read_only(chip
);
746 nrf5_nvmc_read_only(chip
);
747 LOG_ERROR("Failed to write to nrf5 flash");
751 static int nrf5_erase(struct flash_bank
*bank
, int first
, int last
)
754 struct nrf5_info
*chip
;
756 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
760 /* For each sector to be erased */
761 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
762 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
767 static int nrf5_code_flash_write(struct flash_bank
*bank
,
768 struct nrf5_info
*chip
,
769 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
773 /* Need to perform reads to fill any gaps we need to preserve in the first page,
774 before the start of buffer, or in the last page, after the end of buffer */
775 uint32_t first_page
= offset
/chip
->code_page_size
;
776 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
778 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
779 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
781 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
782 offset
, offset
+count
, first_page_offset
, last_page_offset
);
784 uint32_t page_cnt
= last_page
- first_page
;
785 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
787 /* Fill in any space between start of first page and start of buffer */
788 uint32_t pre
= offset
- first_page_offset
;
790 res
= target_read_memory(bank
->target
,
799 /* Fill in main contents of buffer */
800 memcpy(buffer_to_flash
+pre
, buffer
, count
);
802 /* Fill in any space between end of buffer and end of last page */
803 uint32_t post
= last_page_offset
- (offset
+count
);
805 /* Retrieve the full row contents from Flash */
806 res
= target_read_memory(bank
->target
,
810 buffer_to_flash
+pre
+count
);
815 return nrf5_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
818 static int nrf5_uicr_flash_write(struct flash_bank
*bank
,
819 struct nrf5_info
*chip
,
820 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
823 uint8_t uicr
[NRF5_UICR_SIZE
];
824 struct flash_sector
*sector
= &bank
->sectors
[0];
826 if ((offset
+ count
) > NRF5_UICR_SIZE
)
829 res
= target_read_memory(bank
->target
,
838 res
= nrf5_erase_page(bank
, chip
, sector
);
842 res
= nrf5_nvmc_write_enable(chip
);
846 memcpy(&uicr
[offset
], buffer
, count
);
848 res
= nrf5_ll_flash_write(chip
, NRF5_UICR_BASE
, uicr
, NRF5_UICR_SIZE
);
849 if (res
!= ERROR_OK
) {
850 nrf5_nvmc_read_only(chip
);
854 return nrf5_nvmc_read_only(chip
);
858 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
859 uint32_t offset
, uint32_t count
)
862 struct nrf5_info
*chip
;
864 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
868 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
872 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
874 static struct nrf5_info
*chip
;
876 switch (bank
->base
) {
877 case NRF5_FLASH_BASE
:
878 bank
->bank_number
= 0;
881 bank
->bank_number
= 1;
884 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
889 /* Create a new chip */
890 chip
= calloc(1, sizeof(*chip
));
894 chip
->target
= bank
->target
;
897 switch (bank
->base
) {
898 case NRF5_FLASH_BASE
:
899 chip
->bank
[bank
->bank_number
].write
= nrf5_code_flash_write
;
902 chip
->bank
[bank
->bank_number
].write
= nrf5_uicr_flash_write
;
906 chip
->bank
[bank
->bank_number
].probed
= false;
907 bank
->driver_priv
= chip
;
912 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
915 struct flash_bank
*bank
= NULL
;
916 struct target
*target
= get_current_target(CMD_CTX
);
918 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
922 assert(bank
!= NULL
);
924 struct nrf5_info
*chip
;
926 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
932 res
= target_read_u32(target
, NRF5_FICR_PPFC
,
934 if (res
!= ERROR_OK
) {
935 LOG_ERROR("Couldn't read PPFC register");
939 if ((ppfc
& 0xFF) == 0x00) {
940 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
941 "mass erase command won't work.");
945 res
= nrf5_erase_all(chip
);
946 if (res
!= ERROR_OK
) {
947 LOG_ERROR("Failed to erase the chip");
948 nrf5_protect_check(bank
);
952 res
= nrf5_protect_check(bank
);
953 if (res
!= ERROR_OK
) {
954 LOG_ERROR("Failed to check chip's write protection");
958 res
= get_flash_bank_by_addr(target
, NRF5_UICR_BASE
, true, &bank
);
965 static int nrf5_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
969 struct nrf5_info
*chip
;
971 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
976 const uint32_t address
;
979 { .address
= NRF5_FICR_CODEPAGESIZE
},
980 { .address
= NRF5_FICR_CODESIZE
},
981 { .address
= NRF5_FICR_CLENR0
},
982 { .address
= NRF5_FICR_PPFC
},
983 { .address
= NRF5_FICR_NUMRAMBLOCK
},
984 { .address
= NRF5_FICR_SIZERAMBLOCK0
},
985 { .address
= NRF5_FICR_SIZERAMBLOCK1
},
986 { .address
= NRF5_FICR_SIZERAMBLOCK2
},
987 { .address
= NRF5_FICR_SIZERAMBLOCK3
},
988 { .address
= NRF5_FICR_CONFIGID
},
989 { .address
= NRF5_FICR_DEVICEID0
},
990 { .address
= NRF5_FICR_DEVICEID1
},
991 { .address
= NRF5_FICR_ER0
},
992 { .address
= NRF5_FICR_ER1
},
993 { .address
= NRF5_FICR_ER2
},
994 { .address
= NRF5_FICR_ER3
},
995 { .address
= NRF5_FICR_IR0
},
996 { .address
= NRF5_FICR_IR1
},
997 { .address
= NRF5_FICR_IR2
},
998 { .address
= NRF5_FICR_IR3
},
999 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1000 { .address
= NRF5_FICR_DEVICEADDR0
},
1001 { .address
= NRF5_FICR_DEVICEADDR1
},
1002 { .address
= NRF5_FICR_OVERRIDEN
},
1003 { .address
= NRF5_FICR_NRF_1MBIT0
},
1004 { .address
= NRF5_FICR_NRF_1MBIT1
},
1005 { .address
= NRF5_FICR_NRF_1MBIT2
},
1006 { .address
= NRF5_FICR_NRF_1MBIT3
},
1007 { .address
= NRF5_FICR_NRF_1MBIT4
},
1008 { .address
= NRF5_FICR_BLE_1MBIT0
},
1009 { .address
= NRF5_FICR_BLE_1MBIT1
},
1010 { .address
= NRF5_FICR_BLE_1MBIT2
},
1011 { .address
= NRF5_FICR_BLE_1MBIT3
},
1012 { .address
= NRF5_FICR_BLE_1MBIT4
},
1014 { .address
= NRF5_UICR_CLENR0
, },
1015 { .address
= NRF5_UICR_RBPCONF
},
1016 { .address
= NRF5_UICR_XTALFREQ
},
1017 { .address
= NRF5_UICR_FWID
},
1020 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1021 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1023 if (res
!= ERROR_OK
) {
1024 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1029 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1030 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1032 if (res
!= ERROR_OK
) {
1033 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1038 snprintf(buf
, buf_size
,
1039 "\n[factory information control block]\n\n"
1040 "code page size: %"PRIu32
"B\n"
1041 "code memory size: %"PRIu32
"kB\n"
1042 "code region 0 size: %"PRIu32
"kB\n"
1043 "pre-programmed code: %s\n"
1044 "number of ram blocks: %"PRIu32
"\n"
1045 "ram block 0 size: %"PRIu32
"B\n"
1046 "ram block 1 size: %"PRIu32
"B\n"
1047 "ram block 2 size: %"PRIu32
"B\n"
1048 "ram block 3 size: %"PRIu32
"B\n"
1049 "config id: %" PRIx32
"\n"
1050 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1051 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1052 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1053 "device address type: 0x%"PRIx32
"\n"
1054 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1055 "override enable: %"PRIx32
"\n"
1056 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1057 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1058 "\n[user information control block]\n\n"
1059 "code region 0 size: %"PRIu32
"kB\n"
1060 "read back protection configuration: %"PRIx32
"\n"
1061 "reset value for XTALFREQ: %"PRIx32
"\n"
1062 "firmware id: 0x%04"PRIx32
,
1064 (ficr
[1].value
* ficr
[0].value
) / 1024,
1065 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1066 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1069 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1070 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1071 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1073 ficr
[10].value
, ficr
[11].value
,
1074 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1075 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1077 ficr
[21].value
, ficr
[22].value
,
1079 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1080 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1081 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1082 uicr
[1].value
& 0xFFFF,
1083 uicr
[2].value
& 0xFF,
1084 uicr
[3].value
& 0xFFFF);
1089 static const struct command_registration nrf5_exec_command_handlers
[] = {
1091 .name
= "mass_erase",
1092 .handler
= nrf5_handle_mass_erase_command
,
1093 .mode
= COMMAND_EXEC
,
1094 .help
= "Erase all flash contents of the chip.",
1096 COMMAND_REGISTRATION_DONE
1099 static const struct command_registration nrf5_command_handlers
[] = {
1102 .mode
= COMMAND_ANY
,
1103 .help
= "nrf5 flash command group",
1105 .chain
= nrf5_exec_command_handlers
,
1109 .mode
= COMMAND_ANY
,
1110 .help
= "nrf51 flash command group",
1112 .chain
= nrf5_exec_command_handlers
,
1114 COMMAND_REGISTRATION_DONE
1117 struct flash_driver nrf5_flash
= {
1119 .commands
= nrf5_command_handlers
,
1120 .flash_bank_command
= nrf5_flash_bank_command
,
1122 .erase
= nrf5_erase
,
1123 .protect
= nrf5_protect
,
1124 .write
= nrf5_write
,
1125 .read
= default_flash_read
,
1126 .probe
= nrf5_probe
,
1127 .auto_probe
= nrf5_auto_probe
,
1128 .erase_check
= default_flash_blank_check
,
1129 .protect_check
= nrf5_protect_check
,
1132 /* We need to retain the flash-driver name as well as the commands
1133 * for backwards compatability */
1134 struct flash_driver nrf51_flash
= {
1136 .commands
= nrf5_command_handlers
,
1137 .flash_bank_command
= nrf5_flash_bank_command
,
1139 .erase
= nrf5_erase
,
1140 .protect
= nrf5_protect
,
1141 .write
= nrf5_write
,
1142 .read
= default_flash_read
,
1143 .probe
= nrf5_probe
,
1144 .auto_probe
= nrf5_auto_probe
,
1145 .erase_check
= default_flash_blank_check
,
1146 .protect_check
= nrf5_protect_check
,
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