1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ****************************************************************************/
24 /* Some of the the lower level code was based on code supplied by
25 * ATMEL under this copyright. */
27 /* BEGIN ATMEL COPYRIGHT */
28 /* ----------------------------------------------------------------------------
29 * ATMEL Microcontroller Software Support
30 * ----------------------------------------------------------------------------
31 * Copyright (c) 2009, Atmel Corporation
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions are met:
38 * - Redistributions of source code must retain the above copyright notice,
39 * this list of conditions and the disclaimer below.
41 * Atmel's name may not be used to endorse or promote products derived from
42 * this software without specific prior written permission.
44 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
47 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
50 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
51 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
52 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
53 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * ----------------------------------------------------------------------------
56 /* END ATMEL COPYRIGHT */
63 #include <helper/time_support.h>
65 #define REG_NAME_WIDTH (12)
67 /* at91sam3u series (has one or two flash banks) */
68 #define FLASH_BANK0_BASE_U 0x00080000
69 #define FLASH_BANK1_BASE_U 0x00100000
71 /* at91sam3s series (has always one flash bank) */
72 #define FLASH_BANK_BASE_S 0x00400000
74 /* at91sam3sd series (has always two flash banks) */
75 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
76 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
79 /* at91sam3n series (has always one flash bank) */
80 #define FLASH_BANK_BASE_N 0x00400000
82 /* at91sam3a/x series has two flash banks*/
83 #define FLASH_BANK0_BASE_AX 0x00080000
84 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
85 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
86 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
88 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
89 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
90 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
91 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
92 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
93 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
94 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
95 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
96 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
98 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
99 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
100 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
101 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
102 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
103 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
104 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
105 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
107 #define offset_EFC_FMR 0
108 #define offset_EFC_FCR 4
109 #define offset_EFC_FSR 8
110 #define offset_EFC_FRR 12
112 extern struct flash_driver at91sam3_flash
;
114 static float _tomhz(uint32_t freq_hz
)
118 f
= ((float)(freq_hz
)) / 1000000.0;
122 /* How the chip is configured. */
124 uint32_t unique_id
[4];
128 uint32_t mainosc_freq
;
138 #define SAM3_CHIPID_CIDR (0x400E0740)
139 uint32_t CHIPID_CIDR
;
140 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
141 uint32_t CHIPID_CIDR2
;
142 #define SAM3_CHIPID_EXID (0x400E0744)
143 uint32_t CHIPID_EXID
;
144 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
145 uint32_t CHIPID_EXID2
;
148 #define SAM3_PMC_BASE (0x400E0400)
149 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
151 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
153 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
155 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
157 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
159 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
161 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
163 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
165 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
167 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
169 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
171 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
173 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
175 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
180 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
181 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
182 * the flash wait state (FWS) should be set to 6. It seems like that the
183 * cause of the problem is not the flash itself, but the flash write
184 * buffer. Ie the wait states have to be set before writing into the
186 * Tested and confirmed with SAM3N and SAM3U
189 struct sam3_bank_private
{
191 /* DANGER: THERE ARE DRAGONS HERE.. */
192 /* NOTE: If you add more 'ghost' pointers */
193 /* be aware that you must *manually* update */
194 /* these pointers in the function sam3_GetDetails() */
195 /* See the comment "Here there be dragons" */
197 /* so we can find the chip we belong to */
198 struct sam3_chip
*pChip
;
199 /* so we can find the original bank pointer */
200 struct flash_bank
*pBank
;
201 unsigned bank_number
;
202 uint32_t controller_address
;
203 uint32_t base_address
;
204 uint32_t flash_wait_states
;
208 unsigned sector_size
;
212 struct sam3_chip_details
{
213 /* THERE ARE DRAGONS HERE.. */
214 /* note: If you add pointers here */
215 /* be careful about them as they */
216 /* may need to be updated inside */
217 /* the function: "sam3_GetDetails() */
218 /* which copy/overwrites the */
219 /* 'runtime' copy of this structure */
220 uint32_t chipid_cidr
;
224 #define SAM3_N_NVM_BITS 3
225 unsigned gpnvm
[SAM3_N_NVM_BITS
];
226 unsigned total_flash_size
;
227 unsigned total_sram_size
;
229 #define SAM3_MAX_FLASH_BANKS 2
230 /* these are "initialized" from the global const data */
231 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
235 struct sam3_chip
*next
;
238 /* this is "initialized" from the global const structure */
239 struct sam3_chip_details details
;
240 struct target
*target
;
245 struct sam3_reg_list
{
246 uint32_t address
; size_t struct_offset
; const char *name
;
247 void (*explain_func
)(struct sam3_chip
*pInfo
);
250 static struct sam3_chip
*all_sam3_chips
;
252 static struct sam3_chip
*get_current_sam3(struct command_context
*cmd_ctx
)
255 static struct sam3_chip
*p
;
257 t
= get_current_target(cmd_ctx
);
259 command_print(cmd_ctx
, "No current target?");
265 /* this should not happen */
266 /* the command is not registered until the chip is created? */
267 command_print(cmd_ctx
, "No SAM3 chips exist?");
276 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
280 /* these are used to *initialize* the "pChip->details" structure. */
281 static const struct sam3_chip_details all_sam3_details
[] = {
282 /* Start at91sam3u* series */
284 .chipid_cidr
= 0x28100960,
285 .name
= "at91sam3u4e",
286 .total_flash_size
= 256 * 1024,
287 .total_sram_size
= 52 * 1024,
291 /* System boots at address 0x0 */
292 /* gpnvm[1] = selects boot code */
293 /* if gpnvm[1] == 0 */
294 /* boot is via "SAMBA" (rom) */
296 /* boot is via FLASH */
297 /* Selection is via gpnvm[2] */
300 /* NOTE: banks 0 & 1 switch places */
301 /* if gpnvm[2] == 0 */
302 /* Bank0 is the boot rom */
304 /* Bank1 is the boot rom */
313 .base_address
= FLASH_BANK0_BASE_U
,
314 .controller_address
= 0x400e0800,
315 .flash_wait_states
= 6, /* workaround silicon bug */
317 .size_bytes
= 128 * 1024,
329 .base_address
= FLASH_BANK1_BASE_U
,
330 .controller_address
= 0x400e0a00,
331 .flash_wait_states
= 6, /* workaround silicon bug */
333 .size_bytes
= 128 * 1024,
342 .chipid_cidr
= 0x281a0760,
343 .name
= "at91sam3u2e",
344 .total_flash_size
= 128 * 1024,
345 .total_sram_size
= 36 * 1024,
349 /* System boots at address 0x0 */
350 /* gpnvm[1] = selects boot code */
351 /* if gpnvm[1] == 0 */
352 /* boot is via "SAMBA" (rom) */
354 /* boot is via FLASH */
355 /* Selection is via gpnvm[2] */
364 .base_address
= FLASH_BANK0_BASE_U
,
365 .controller_address
= 0x400e0800,
366 .flash_wait_states
= 6, /* workaround silicon bug */
368 .size_bytes
= 128 * 1024,
382 .chipid_cidr
= 0x28190560,
383 .name
= "at91sam3u1e",
384 .total_flash_size
= 64 * 1024,
385 .total_sram_size
= 20 * 1024,
389 /* System boots at address 0x0 */
390 /* gpnvm[1] = selects boot code */
391 /* if gpnvm[1] == 0 */
392 /* boot is via "SAMBA" (rom) */
394 /* boot is via FLASH */
395 /* Selection is via gpnvm[2] */
406 .base_address
= FLASH_BANK0_BASE_U
,
407 .controller_address
= 0x400e0800,
408 .flash_wait_states
= 6, /* workaround silicon bug */
410 .size_bytes
= 64 * 1024,
426 .chipid_cidr
= 0x28000960,
427 .name
= "at91sam3u4c",
428 .total_flash_size
= 256 * 1024,
429 .total_sram_size
= 52 * 1024,
433 /* System boots at address 0x0 */
434 /* gpnvm[1] = selects boot code */
435 /* if gpnvm[1] == 0 */
436 /* boot is via "SAMBA" (rom) */
438 /* boot is via FLASH */
439 /* Selection is via gpnvm[2] */
442 /* NOTE: banks 0 & 1 switch places */
443 /* if gpnvm[2] == 0 */
444 /* Bank0 is the boot rom */
446 /* Bank1 is the boot rom */
455 .base_address
= FLASH_BANK0_BASE_U
,
456 .controller_address
= 0x400e0800,
457 .flash_wait_states
= 6, /* workaround silicon bug */
459 .size_bytes
= 128 * 1024,
470 .base_address
= FLASH_BANK1_BASE_U
,
471 .controller_address
= 0x400e0a00,
472 .flash_wait_states
= 6, /* workaround silicon bug */
474 .size_bytes
= 128 * 1024,
483 .chipid_cidr
= 0x280a0760,
484 .name
= "at91sam3u2c",
485 .total_flash_size
= 128 * 1024,
486 .total_sram_size
= 36 * 1024,
490 /* System boots at address 0x0 */
491 /* gpnvm[1] = selects boot code */
492 /* if gpnvm[1] == 0 */
493 /* boot is via "SAMBA" (rom) */
495 /* boot is via FLASH */
496 /* Selection is via gpnvm[2] */
505 .base_address
= FLASH_BANK0_BASE_U
,
506 .controller_address
= 0x400e0800,
507 .flash_wait_states
= 6, /* workaround silicon bug */
509 .size_bytes
= 128 * 1024,
523 .chipid_cidr
= 0x28090560,
524 .name
= "at91sam3u1c",
525 .total_flash_size
= 64 * 1024,
526 .total_sram_size
= 20 * 1024,
530 /* System boots at address 0x0 */
531 /* gpnvm[1] = selects boot code */
532 /* if gpnvm[1] == 0 */
533 /* boot is via "SAMBA" (rom) */
535 /* boot is via FLASH */
536 /* Selection is via gpnvm[2] */
547 .base_address
= FLASH_BANK0_BASE_U
,
548 .controller_address
= 0x400e0800,
549 .flash_wait_states
= 6, /* workaround silicon bug */
551 .size_bytes
= 64 * 1024,
566 /* Start at91sam3s* series */
568 /* Note: The preliminary at91sam3s datasheet says on page 302 */
569 /* that the flash controller is at address 0x400E0800. */
570 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
572 .chipid_cidr
= 0x28A00960,
573 .name
= "at91sam3s4c",
574 .total_flash_size
= 256 * 1024,
575 .total_sram_size
= 48 * 1024,
585 .base_address
= FLASH_BANK_BASE_S
,
586 .controller_address
= 0x400e0a00,
587 .flash_wait_states
= 6, /* workaround silicon bug */
589 .size_bytes
= 256 * 1024,
591 .sector_size
= 16384,
605 .chipid_cidr
= 0x28900960,
606 .name
= "at91sam3s4b",
607 .total_flash_size
= 256 * 1024,
608 .total_sram_size
= 48 * 1024,
618 .base_address
= FLASH_BANK_BASE_S
,
619 .controller_address
= 0x400e0a00,
620 .flash_wait_states
= 6, /* workaround silicon bug */
622 .size_bytes
= 256 * 1024,
624 .sector_size
= 16384,
637 .chipid_cidr
= 0x28800960,
638 .name
= "at91sam3s4a",
639 .total_flash_size
= 256 * 1024,
640 .total_sram_size
= 48 * 1024,
650 .base_address
= FLASH_BANK_BASE_S
,
651 .controller_address
= 0x400e0a00,
652 .flash_wait_states
= 6, /* workaround silicon bug */
654 .size_bytes
= 256 * 1024,
656 .sector_size
= 16384,
669 .chipid_cidr
= 0x28AA0760,
670 .name
= "at91sam3s2c",
671 .total_flash_size
= 128 * 1024,
672 .total_sram_size
= 32 * 1024,
682 .base_address
= FLASH_BANK_BASE_S
,
683 .controller_address
= 0x400e0a00,
684 .flash_wait_states
= 6, /* workaround silicon bug */
686 .size_bytes
= 128 * 1024,
688 .sector_size
= 16384,
701 .chipid_cidr
= 0x289A0760,
702 .name
= "at91sam3s2b",
703 .total_flash_size
= 128 * 1024,
704 .total_sram_size
= 32 * 1024,
714 .base_address
= FLASH_BANK_BASE_S
,
715 .controller_address
= 0x400e0a00,
716 .flash_wait_states
= 6, /* workaround silicon bug */
718 .size_bytes
= 128 * 1024,
720 .sector_size
= 16384,
733 .chipid_cidr
= 0x298B0A60,
734 .name
= "at91sam3sd8a",
735 .total_flash_size
= 512 * 1024,
736 .total_sram_size
= 64 * 1024,
746 .base_address
= FLASH_BANK0_BASE_SD
,
747 .controller_address
= 0x400e0a00,
748 .flash_wait_states
= 6, /* workaround silicon bug */
750 .size_bytes
= 256 * 1024,
752 .sector_size
= 32768,
761 .base_address
= FLASH_BANK1_BASE_512K_SD
,
762 .controller_address
= 0x400e0a00,
763 .flash_wait_states
= 6, /* workaround silicon bug */
765 .size_bytes
= 256 * 1024,
767 .sector_size
= 32768,
773 .chipid_cidr
= 0x299B0A60,
774 .name
= "at91sam3sd8b",
775 .total_flash_size
= 512 * 1024,
776 .total_sram_size
= 64 * 1024,
786 .base_address
= FLASH_BANK0_BASE_SD
,
787 .controller_address
= 0x400e0a00,
788 .flash_wait_states
= 6, /* workaround silicon bug */
790 .size_bytes
= 256 * 1024,
792 .sector_size
= 32768,
801 .base_address
= FLASH_BANK1_BASE_512K_SD
,
802 .controller_address
= 0x400e0a00,
803 .flash_wait_states
= 6, /* workaround silicon bug */
805 .size_bytes
= 256 * 1024,
807 .sector_size
= 32768,
813 .chipid_cidr
= 0x29ab0a60,
814 .name
= "at91sam3sd8c",
815 .total_flash_size
= 512 * 1024,
816 .total_sram_size
= 64 * 1024,
826 .base_address
= FLASH_BANK0_BASE_SD
,
827 .controller_address
= 0x400e0a00,
828 .flash_wait_states
= 6, /* workaround silicon bug */
830 .size_bytes
= 256 * 1024,
832 .sector_size
= 32768,
841 .base_address
= FLASH_BANK1_BASE_512K_SD
,
842 .controller_address
= 0x400e0a00,
843 .flash_wait_states
= 6, /* workaround silicon bug */
845 .size_bytes
= 256 * 1024,
847 .sector_size
= 32768,
853 .chipid_cidr
= 0x288A0760,
854 .name
= "at91sam3s2a",
855 .total_flash_size
= 128 * 1024,
856 .total_sram_size
= 32 * 1024,
866 .base_address
= FLASH_BANK_BASE_S
,
867 .controller_address
= 0x400e0a00,
868 .flash_wait_states
= 6, /* workaround silicon bug */
870 .size_bytes
= 128 * 1024,
872 .sector_size
= 16384,
885 .chipid_cidr
= 0x28A90560,
886 .name
= "at91sam3s1c",
887 .total_flash_size
= 64 * 1024,
888 .total_sram_size
= 16 * 1024,
898 .base_address
= FLASH_BANK_BASE_S
,
899 .controller_address
= 0x400e0a00,
900 .flash_wait_states
= 6, /* workaround silicon bug */
902 .size_bytes
= 64 * 1024,
904 .sector_size
= 16384,
917 .chipid_cidr
= 0x28990560,
918 .name
= "at91sam3s1b",
919 .total_flash_size
= 64 * 1024,
920 .total_sram_size
= 16 * 1024,
930 .base_address
= FLASH_BANK_BASE_S
,
931 .controller_address
= 0x400e0a00,
932 .flash_wait_states
= 6, /* workaround silicon bug */
934 .size_bytes
= 64 * 1024,
936 .sector_size
= 16384,
949 .chipid_cidr
= 0x28890560,
950 .name
= "at91sam3s1a",
951 .total_flash_size
= 64 * 1024,
952 .total_sram_size
= 16 * 1024,
962 .base_address
= FLASH_BANK_BASE_S
,
963 .controller_address
= 0x400e0a00,
964 .flash_wait_states
= 6, /* workaround silicon bug */
966 .size_bytes
= 64 * 1024,
968 .sector_size
= 16384,
981 .chipid_cidr
= 0x288B0A60,
982 .name
= "at91sam3s8a",
983 .total_flash_size
= 256 * 2048,
984 .total_sram_size
= 64 * 1024,
994 .base_address
= FLASH_BANK_BASE_S
,
995 .controller_address
= 0x400e0a00,
996 .flash_wait_states
= 6, /* workaround silicon bug */
998 .size_bytes
= 256 * 2048,
1000 .sector_size
= 32768,
1013 .chipid_cidr
= 0x289B0A60,
1014 .name
= "at91sam3s8b",
1015 .total_flash_size
= 256 * 2048,
1016 .total_sram_size
= 64 * 1024,
1026 .base_address
= FLASH_BANK_BASE_S
,
1027 .controller_address
= 0x400e0a00,
1028 .flash_wait_states
= 6, /* workaround silicon bug */
1030 .size_bytes
= 256 * 2048,
1032 .sector_size
= 32768,
1045 .chipid_cidr
= 0x28AB0A60,
1046 .name
= "at91sam3s8c",
1047 .total_flash_size
= 256 * 2048,
1048 .total_sram_size
= 64 * 1024,
1058 .base_address
= FLASH_BANK_BASE_S
,
1059 .controller_address
= 0x400e0a00,
1060 .flash_wait_states
= 6, /* workaround silicon bug */
1062 .size_bytes
= 256 * 2048,
1064 .sector_size
= 32768,
1077 /* Start at91sam3n* series */
1079 .chipid_cidr
= 0x29540960,
1080 .name
= "at91sam3n4c",
1081 .total_flash_size
= 256 * 1024,
1082 .total_sram_size
= 24 * 1024,
1086 /* System boots at address 0x0 */
1087 /* gpnvm[1] = selects boot code */
1088 /* if gpnvm[1] == 0 */
1089 /* boot is via "SAMBA" (rom) */
1091 /* boot is via FLASH */
1092 /* Selection is via gpnvm[2] */
1095 /* NOTE: banks 0 & 1 switch places */
1096 /* if gpnvm[2] == 0 */
1097 /* Bank0 is the boot rom */
1099 /* Bank1 is the boot rom */
1108 .base_address
= FLASH_BANK_BASE_N
,
1109 .controller_address
= 0x400e0A00,
1110 .flash_wait_states
= 6, /* workaround silicon bug */
1112 .size_bytes
= 256 * 1024,
1114 .sector_size
= 16384,
1128 .chipid_cidr
= 0x29440960,
1129 .name
= "at91sam3n4b",
1130 .total_flash_size
= 256 * 1024,
1131 .total_sram_size
= 24 * 1024,
1135 /* System boots at address 0x0 */
1136 /* gpnvm[1] = selects boot code */
1137 /* if gpnvm[1] == 0 */
1138 /* boot is via "SAMBA" (rom) */
1140 /* boot is via FLASH */
1141 /* Selection is via gpnvm[2] */
1144 /* NOTE: banks 0 & 1 switch places */
1145 /* if gpnvm[2] == 0 */
1146 /* Bank0 is the boot rom */
1148 /* Bank1 is the boot rom */
1157 .base_address
= FLASH_BANK_BASE_N
,
1158 .controller_address
= 0x400e0A00,
1159 .flash_wait_states
= 6, /* workaround silicon bug */
1161 .size_bytes
= 256 * 1024,
1163 .sector_size
= 16384,
1177 .chipid_cidr
= 0x29340960,
1178 .name
= "at91sam3n4a",
1179 .total_flash_size
= 256 * 1024,
1180 .total_sram_size
= 24 * 1024,
1184 /* System boots at address 0x0 */
1185 /* gpnvm[1] = selects boot code */
1186 /* if gpnvm[1] == 0 */
1187 /* boot is via "SAMBA" (rom) */
1189 /* boot is via FLASH */
1190 /* Selection is via gpnvm[2] */
1193 /* NOTE: banks 0 & 1 switch places */
1194 /* if gpnvm[2] == 0 */
1195 /* Bank0 is the boot rom */
1197 /* Bank1 is the boot rom */
1206 .base_address
= FLASH_BANK_BASE_N
,
1207 .controller_address
= 0x400e0A00,
1208 .flash_wait_states
= 6, /* workaround silicon bug */
1210 .size_bytes
= 256 * 1024,
1212 .sector_size
= 16384,
1226 .chipid_cidr
= 0x29590760,
1227 .name
= "at91sam3n2c",
1228 .total_flash_size
= 128 * 1024,
1229 .total_sram_size
= 16 * 1024,
1233 /* System boots at address 0x0 */
1234 /* gpnvm[1] = selects boot code */
1235 /* if gpnvm[1] == 0 */
1236 /* boot is via "SAMBA" (rom) */
1238 /* boot is via FLASH */
1239 /* Selection is via gpnvm[2] */
1242 /* NOTE: banks 0 & 1 switch places */
1243 /* if gpnvm[2] == 0 */
1244 /* Bank0 is the boot rom */
1246 /* Bank1 is the boot rom */
1255 .base_address
= FLASH_BANK_BASE_N
,
1256 .controller_address
= 0x400e0A00,
1257 .flash_wait_states
= 6, /* workaround silicon bug */
1259 .size_bytes
= 128 * 1024,
1261 .sector_size
= 16384,
1275 .chipid_cidr
= 0x29490760,
1276 .name
= "at91sam3n2b",
1277 .total_flash_size
= 128 * 1024,
1278 .total_sram_size
= 16 * 1024,
1282 /* System boots at address 0x0 */
1283 /* gpnvm[1] = selects boot code */
1284 /* if gpnvm[1] == 0 */
1285 /* boot is via "SAMBA" (rom) */
1287 /* boot is via FLASH */
1288 /* Selection is via gpnvm[2] */
1291 /* NOTE: banks 0 & 1 switch places */
1292 /* if gpnvm[2] == 0 */
1293 /* Bank0 is the boot rom */
1295 /* Bank1 is the boot rom */
1304 .base_address
= FLASH_BANK_BASE_N
,
1305 .controller_address
= 0x400e0A00,
1306 .flash_wait_states
= 6, /* workaround silicon bug */
1308 .size_bytes
= 128 * 1024,
1310 .sector_size
= 16384,
1324 .chipid_cidr
= 0x29390760,
1325 .name
= "at91sam3n2a",
1326 .total_flash_size
= 128 * 1024,
1327 .total_sram_size
= 16 * 1024,
1331 /* System boots at address 0x0 */
1332 /* gpnvm[1] = selects boot code */
1333 /* if gpnvm[1] == 0 */
1334 /* boot is via "SAMBA" (rom) */
1336 /* boot is via FLASH */
1337 /* Selection is via gpnvm[2] */
1340 /* NOTE: banks 0 & 1 switch places */
1341 /* if gpnvm[2] == 0 */
1342 /* Bank0 is the boot rom */
1344 /* Bank1 is the boot rom */
1353 .base_address
= FLASH_BANK_BASE_N
,
1354 .controller_address
= 0x400e0A00,
1355 .flash_wait_states
= 6, /* workaround silicon bug */
1357 .size_bytes
= 128 * 1024,
1359 .sector_size
= 16384,
1373 .chipid_cidr
= 0x29580560,
1374 .name
= "at91sam3n1c",
1375 .total_flash_size
= 64 * 1024,
1376 .total_sram_size
= 8 * 1024,
1380 /* System boots at address 0x0 */
1381 /* gpnvm[1] = selects boot code */
1382 /* if gpnvm[1] == 0 */
1383 /* boot is via "SAMBA" (rom) */
1385 /* boot is via FLASH */
1386 /* Selection is via gpnvm[2] */
1389 /* NOTE: banks 0 & 1 switch places */
1390 /* if gpnvm[2] == 0 */
1391 /* Bank0 is the boot rom */
1393 /* Bank1 is the boot rom */
1402 .base_address
= FLASH_BANK_BASE_N
,
1403 .controller_address
= 0x400e0A00,
1404 .flash_wait_states
= 6, /* workaround silicon bug */
1406 .size_bytes
= 64 * 1024,
1408 .sector_size
= 16384,
1422 .chipid_cidr
= 0x29480560,
1423 .name
= "at91sam3n1b",
1424 .total_flash_size
= 64 * 1024,
1425 .total_sram_size
= 8 * 1024,
1429 /* System boots at address 0x0 */
1430 /* gpnvm[1] = selects boot code */
1431 /* if gpnvm[1] == 0 */
1432 /* boot is via "SAMBA" (rom) */
1434 /* boot is via FLASH */
1435 /* Selection is via gpnvm[2] */
1438 /* NOTE: banks 0 & 1 switch places */
1439 /* if gpnvm[2] == 0 */
1440 /* Bank0 is the boot rom */
1442 /* Bank1 is the boot rom */
1451 .base_address
= FLASH_BANK_BASE_N
,
1452 .controller_address
= 0x400e0A00,
1453 .flash_wait_states
= 6, /* workaround silicon bug */
1455 .size_bytes
= 64 * 1024,
1457 .sector_size
= 16384,
1471 .chipid_cidr
= 0x29380560,
1472 .name
= "at91sam3n1a",
1473 .total_flash_size
= 64 * 1024,
1474 .total_sram_size
= 8 * 1024,
1478 /* System boots at address 0x0 */
1479 /* gpnvm[1] = selects boot code */
1480 /* if gpnvm[1] == 0 */
1481 /* boot is via "SAMBA" (rom) */
1483 /* boot is via FLASH */
1484 /* Selection is via gpnvm[2] */
1487 /* NOTE: banks 0 & 1 switch places */
1488 /* if gpnvm[2] == 0 */
1489 /* Bank0 is the boot rom */
1491 /* Bank1 is the boot rom */
1500 .base_address
= FLASH_BANK_BASE_N
,
1501 .controller_address
= 0x400e0A00,
1502 .flash_wait_states
= 6, /* workaround silicon bug */
1504 .size_bytes
= 64 * 1024,
1506 .sector_size
= 16384,
1520 .chipid_cidr
= 0x29480360,
1521 .name
= "at91sam3n0b",
1522 .total_flash_size
= 32 * 1024,
1523 .total_sram_size
= 8 * 1024,
1534 .base_address
= FLASH_BANK_BASE_N
,
1535 .controller_address
= 0x400e0A00,
1536 .flash_wait_states
= 6, /* workaround silicon bug */
1538 .size_bytes
= 32 * 1024,
1540 .sector_size
= 16384,
1554 .chipid_cidr
= 0x29380360,
1555 .name
= "at91sam3n0a",
1556 .total_flash_size
= 32 * 1024,
1557 .total_sram_size
= 8 * 1024,
1568 .base_address
= FLASH_BANK_BASE_N
,
1569 .controller_address
= 0x400e0A00,
1570 .flash_wait_states
= 6, /* workaround silicon bug */
1572 .size_bytes
= 32 * 1024,
1574 .sector_size
= 16384,
1588 .chipid_cidr
= 0x29450260,
1589 .name
= "at91sam3n00b",
1590 .total_flash_size
= 16 * 1024,
1591 .total_sram_size
= 4 * 1024,
1602 .base_address
= FLASH_BANK_BASE_N
,
1603 .controller_address
= 0x400e0A00,
1604 .flash_wait_states
= 6, /* workaround silicon bug */
1606 .size_bytes
= 16 * 1024,
1608 .sector_size
= 16384,
1622 .chipid_cidr
= 0x29350260,
1623 .name
= "at91sam3n00a",
1624 .total_flash_size
= 16 * 1024,
1625 .total_sram_size
= 4 * 1024,
1636 .base_address
= FLASH_BANK_BASE_N
,
1637 .controller_address
= 0x400e0A00,
1638 .flash_wait_states
= 6, /* workaround silicon bug */
1640 .size_bytes
= 16 * 1024,
1642 .sector_size
= 16384,
1656 /* Start at91sam3a series*/
1657 /* System boots at address 0x0 */
1658 /* gpnvm[1] = selects boot code */
1659 /* if gpnvm[1] == 0 */
1660 /* boot is via "SAMBA" (rom) */
1662 /* boot is via FLASH */
1663 /* Selection is via gpnvm[2] */
1666 /* NOTE: banks 0 & 1 switch places */
1667 /* if gpnvm[2] == 0 */
1668 /* Bank0 is the boot rom */
1670 /* Bank1 is the boot rom */
1674 .chipid_cidr
= 0x283E0A60,
1675 .name
= "at91sam3a8c",
1676 .total_flash_size
= 512 * 1024,
1677 .total_sram_size
= 96 * 1024,
1687 .base_address
= FLASH_BANK0_BASE_AX
,
1688 .controller_address
= 0x400e0a00,
1689 .flash_wait_states
= 6, /* workaround silicon bug */
1691 .size_bytes
= 256 * 1024,
1693 .sector_size
= 16384,
1702 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1703 .controller_address
= 0x400e0c00,
1704 .flash_wait_states
= 6, /* workaround silicon bug */
1706 .size_bytes
= 256 * 1024,
1708 .sector_size
= 16384,
1715 .chipid_cidr
= 0x283B0960,
1716 .name
= "at91sam3a4c",
1717 .total_flash_size
= 256 * 1024,
1718 .total_sram_size
= 64 * 1024,
1728 .base_address
= FLASH_BANK0_BASE_AX
,
1729 .controller_address
= 0x400e0a00,
1730 .flash_wait_states
= 6, /* workaround silicon bug */
1732 .size_bytes
= 128 * 1024,
1734 .sector_size
= 16384,
1743 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1744 .controller_address
= 0x400e0c00,
1745 .flash_wait_states
= 6, /* workaround silicon bug */
1747 .size_bytes
= 128 * 1024,
1749 .sector_size
= 16384,
1756 /* Start at91sam3x* series */
1757 /* System boots at address 0x0 */
1758 /* gpnvm[1] = selects boot code */
1759 /* if gpnvm[1] == 0 */
1760 /* boot is via "SAMBA" (rom) */
1762 /* boot is via FLASH */
1763 /* Selection is via gpnvm[2] */
1766 /* NOTE: banks 0 & 1 switch places */
1767 /* if gpnvm[2] == 0 */
1768 /* Bank0 is the boot rom */
1770 /* Bank1 is the boot rom */
1772 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1774 .chipid_cidr
= 0x286E0A20,
1775 .name
= "at91sam3x8h - ES",
1776 .total_flash_size
= 512 * 1024,
1777 .total_sram_size
= 96 * 1024,
1787 .base_address
= FLASH_BANK0_BASE_AX
,
1788 .controller_address
= 0x400e0a00,
1789 .flash_wait_states
= 6, /* workaround silicon bug */
1791 .size_bytes
= 256 * 1024,
1793 .sector_size
= 16384,
1802 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1803 .controller_address
= 0x400e0c00,
1804 .flash_wait_states
= 6, /* workaround silicon bug */
1806 .size_bytes
= 256 * 1024,
1808 .sector_size
= 16384,
1814 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1816 .chipid_cidr
= 0x286E0A60,
1817 .name
= "at91sam3x8h",
1818 .total_flash_size
= 512 * 1024,
1819 .total_sram_size
= 96 * 1024,
1829 .base_address
= FLASH_BANK0_BASE_AX
,
1830 .controller_address
= 0x400e0a00,
1831 .flash_wait_states
= 6, /* workaround silicon bug */
1833 .size_bytes
= 256 * 1024,
1835 .sector_size
= 16384,
1844 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1845 .controller_address
= 0x400e0c00,
1846 .flash_wait_states
= 6, /* workaround silicon bug */
1848 .size_bytes
= 256 * 1024,
1850 .sector_size
= 16384,
1857 .chipid_cidr
= 0x285E0A60,
1858 .name
= "at91sam3x8e",
1859 .total_flash_size
= 512 * 1024,
1860 .total_sram_size
= 96 * 1024,
1870 .base_address
= FLASH_BANK0_BASE_AX
,
1871 .controller_address
= 0x400e0a00,
1872 .flash_wait_states
= 6, /* workaround silicon bug */
1874 .size_bytes
= 256 * 1024,
1876 .sector_size
= 16384,
1885 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1886 .controller_address
= 0x400e0c00,
1887 .flash_wait_states
= 6, /* workaround silicon bug */
1889 .size_bytes
= 256 * 1024,
1891 .sector_size
= 16384,
1898 .chipid_cidr
= 0x284E0A60,
1899 .name
= "at91sam3x8c",
1900 .total_flash_size
= 512 * 1024,
1901 .total_sram_size
= 96 * 1024,
1911 .base_address
= FLASH_BANK0_BASE_AX
,
1912 .controller_address
= 0x400e0a00,
1913 .flash_wait_states
= 6, /* workaround silicon bug */
1915 .size_bytes
= 256 * 1024,
1917 .sector_size
= 16384,
1926 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1927 .controller_address
= 0x400e0c00,
1928 .flash_wait_states
= 6, /* workaround silicon bug */
1930 .size_bytes
= 256 * 1024,
1932 .sector_size
= 16384,
1939 .chipid_cidr
= 0x285B0960,
1940 .name
= "at91sam3x4e",
1941 .total_flash_size
= 256 * 1024,
1942 .total_sram_size
= 64 * 1024,
1952 .base_address
= FLASH_BANK0_BASE_AX
,
1953 .controller_address
= 0x400e0a00,
1954 .flash_wait_states
= 6, /* workaround silicon bug */
1956 .size_bytes
= 128 * 1024,
1958 .sector_size
= 16384,
1967 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1968 .controller_address
= 0x400e0c00,
1969 .flash_wait_states
= 6, /* workaround silicon bug */
1971 .size_bytes
= 128 * 1024,
1973 .sector_size
= 16384,
1980 .chipid_cidr
= 0x284B0960,
1981 .name
= "at91sam3x4c",
1982 .total_flash_size
= 256 * 1024,
1983 .total_sram_size
= 64 * 1024,
1993 .base_address
= FLASH_BANK0_BASE_AX
,
1994 .controller_address
= 0x400e0a00,
1995 .flash_wait_states
= 6, /* workaround silicon bug */
1997 .size_bytes
= 128 * 1024,
1999 .sector_size
= 16384,
2008 .base_address
= FLASH_BANK1_BASE_256K_AX
,
2009 .controller_address
= 0x400e0c00,
2010 .flash_wait_states
= 6, /* workaround silicon bug */
2012 .size_bytes
= 128 * 1024,
2014 .sector_size
= 16384,
2028 /***********************************************************************
2029 **********************************************************************
2030 **********************************************************************
2031 **********************************************************************
2032 **********************************************************************
2033 **********************************************************************/
2034 /* *ATMEL* style code - from the SAM3 driver code */
2037 * Get the current status of the EEFC and
2038 * the value of some status bits (LOCKE, PROGE).
2039 * @param pPrivate - info about the bank
2040 * @param v - result goes here
2042 static int EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
2045 r
= target_read_u32(pPrivate
->pChip
->target
,
2046 pPrivate
->controller_address
+ offset_EFC_FSR
,
2048 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2050 ((unsigned int)((*v
>> 2) & 1)),
2051 ((unsigned int)((*v
>> 1) & 1)),
2052 ((unsigned int)((*v
>> 0) & 1)));
2058 * Get the result of the last executed command.
2059 * @param pPrivate - info about the bank
2060 * @param v - result goes here
2062 static int EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
2066 r
= target_read_u32(pPrivate
->pChip
->target
,
2067 pPrivate
->controller_address
+ offset_EFC_FRR
,
2071 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
2075 static int EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
2076 unsigned command
, unsigned argument
)
2085 /* Check command & argument */
2088 case AT91C_EFC_FCMD_WP
:
2089 case AT91C_EFC_FCMD_WPL
:
2090 case AT91C_EFC_FCMD_EWP
:
2091 case AT91C_EFC_FCMD_EWPL
:
2092 /* case AT91C_EFC_FCMD_EPL: */
2093 /* case AT91C_EFC_FCMD_EPA: */
2094 case AT91C_EFC_FCMD_SLB
:
2095 case AT91C_EFC_FCMD_CLB
:
2096 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
2098 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
2101 case AT91C_EFC_FCMD_SFB
:
2102 case AT91C_EFC_FCMD_CFB
:
2103 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2104 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2105 pPrivate
->pChip
->details
.n_gpnvms
);
2109 case AT91C_EFC_FCMD_GETD
:
2110 case AT91C_EFC_FCMD_EA
:
2111 case AT91C_EFC_FCMD_GLB
:
2112 case AT91C_EFC_FCMD_GFB
:
2113 case AT91C_EFC_FCMD_STUI
:
2114 case AT91C_EFC_FCMD_SPUI
:
2116 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
2119 LOG_ERROR("Unknown command %d", command
);
2123 if (command
== AT91C_EFC_FCMD_SPUI
) {
2124 /* this is a very special situation. */
2125 /* Situation (1) - error/retry - see below */
2126 /* And we are being called recursively */
2127 /* Situation (2) - normal, finished reading unique id */
2129 /* it should be "ready" */
2130 EFC_GetStatus(pPrivate
, &v
);
2132 /* then it is ready */
2136 /* we have done this before */
2137 /* the controller is not responding. */
2138 LOG_ERROR("flash controller(%d) is not ready! Error",
2139 pPrivate
->bank_number
);
2143 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2144 pPrivate
->bank_number
);
2145 /* we do that by issuing the *STOP* command */
2146 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
2147 /* above is recursive, and further recursion is blocked by */
2148 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2154 v
= (0x5A << 24) | (argument
<< 8) | command
;
2155 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
2156 r
= target_write_u32(pPrivate
->pBank
->target
,
2157 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
2159 LOG_DEBUG("Error Write failed");
2164 * Performs the given command and wait until its completion (or an error).
2165 * @param pPrivate - info about the bank
2166 * @param command - Command to perform.
2167 * @param argument - Optional command argument.
2168 * @param status - put command status bits here
2170 static int EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
2178 int64_t ms_now
, ms_end
;
2184 r
= EFC_StartCommand(pPrivate
, command
, argument
);
2188 ms_end
= 500 + timeval_ms();
2191 r
= EFC_GetStatus(pPrivate
, &v
);
2194 ms_now
= timeval_ms();
2195 if (ms_now
> ms_end
) {
2197 LOG_ERROR("Command timeout");
2200 } while ((v
& 1) == 0);
2204 *status
= (v
& 0x6);
2210 * Read the unique ID.
2211 * @param pPrivate - info about the bank
2212 * The unique ID is stored in the 'pPrivate' structure.
2214 static int FLASHD_ReadUniqueID(struct sam3_bank_private
*pPrivate
)
2220 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
2221 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
2222 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
2223 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
2226 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
2230 for (x
= 0; x
< 4; x
++) {
2231 r
= target_read_u32(pPrivate
->pChip
->target
,
2232 pPrivate
->pBank
->base
+ (x
* 4),
2236 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
2239 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
2240 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2242 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
2243 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
2244 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
2245 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
2251 * Erases the entire flash.
2252 * @param pPrivate - the info about the bank.
2254 static int FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
2257 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
2261 * Gets current GPNVM state.
2262 * @param pPrivate - info about the bank.
2263 * @param gpnvm - GPNVM bit index.
2264 * @param puthere - result stored here.
2266 /* ------------------------------------------------------------------------------ */
2267 static int FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
2273 if (pPrivate
->bank_number
!= 0) {
2274 LOG_ERROR("GPNVM only works with Bank0");
2278 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2279 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2280 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2284 /* Get GPNVMs status */
2285 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
2286 if (r
!= ERROR_OK
) {
2287 LOG_ERROR("Failed");
2291 r
= EFC_GetResult(pPrivate
, &v
);
2294 /* Check if GPNVM is set */
2295 /* get the bit and make it a 0/1 */
2296 *puthere
= (v
>> gpnvm
) & 1;
2303 * Clears the selected GPNVM bit.
2304 * @param pPrivate info about the bank
2305 * @param gpnvm GPNVM index.
2306 * @returns 0 if successful; otherwise returns an error code.
2308 static int FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2314 if (pPrivate
->bank_number
!= 0) {
2315 LOG_ERROR("GPNVM only works with Bank0");
2319 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2320 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2321 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2325 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2326 if (r
!= ERROR_OK
) {
2327 LOG_DEBUG("Failed: %d", r
);
2330 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
2331 LOG_DEBUG("End: %d", r
);
2336 * Sets the selected GPNVM bit.
2337 * @param pPrivate info about the bank
2338 * @param gpnvm GPNVM index.
2340 static int FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
2345 if (pPrivate
->bank_number
!= 0) {
2346 LOG_ERROR("GPNVM only works with Bank0");
2350 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
2351 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2352 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
2356 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
2364 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
2370 * Returns a bit field (at most 64) of locked regions within a page.
2371 * @param pPrivate info about the bank
2372 * @param v where to store locked bits
2374 static int FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
2378 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
2380 r
= EFC_GetResult(pPrivate
, v
);
2381 LOG_DEBUG("End: %d", r
);
2386 * Unlocks all the regions in the given address range.
2387 * @param pPrivate info about the bank
2388 * @param start_sector first sector to unlock
2389 * @param end_sector last (inclusive) to unlock
2392 static int FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
2393 unsigned start_sector
,
2394 unsigned end_sector
)
2399 uint32_t pages_per_sector
;
2401 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2403 /* Unlock all pages */
2404 while (start_sector
<= end_sector
) {
2405 pg
= start_sector
* pages_per_sector
;
2407 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
2418 * @param pPrivate - info about the bank
2419 * @param start_sector - first sector to lock
2420 * @param end_sector - last sector (inclusive) to lock
2422 static int FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
2423 unsigned start_sector
,
2424 unsigned end_sector
)
2428 uint32_t pages_per_sector
;
2431 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
2433 /* Lock all pages */
2434 while (start_sector
<= end_sector
) {
2435 pg
= start_sector
* pages_per_sector
;
2437 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
2445 /****** END SAM3 CODE ********/
2447 /* begin helpful debug code */
2448 /* print the fieldname, the field value, in dec & hex, and return field value */
2449 static uint32_t sam3_reg_fieldname(struct sam3_chip
*pChip
,
2450 const char *regname
,
2459 /* extract the field */
2461 v
= v
& ((1 << width
)-1);
2470 /* show the basics */
2471 LOG_USER_N("\t%*s: %*" PRIu32
" [0x%0*" PRIx32
"] ",
2472 REG_NAME_WIDTH
, regname
,
2478 static const char _unknown
[] = "unknown";
2479 static const char *const eproc_names
[] = {
2483 "Cortex-M3", /* 3 */
2485 "arm926ejs", /* 5 */
2498 #define nvpsize2 nvpsize /* these two tables are identical */
2499 static const char *const nvpsize
[] = {
2502 "16K bytes", /* 2 */
2503 "32K bytes", /* 3 */
2505 "64K bytes", /* 5 */
2507 "128K bytes", /* 7 */
2509 "256K bytes", /* 9 */
2510 "512K bytes", /* 10 */
2512 "1024K bytes", /* 12 */
2514 "2048K bytes", /* 14 */
2518 static const char *const sramsize
[] = {
2519 "48K Bytes", /* 0 */
2523 "112K Bytes", /* 4 */
2525 "80K Bytes", /* 6 */
2526 "160K Bytes", /* 7 */
2528 "16K Bytes", /* 9 */
2529 "32K Bytes", /* 10 */
2530 "64K Bytes", /* 11 */
2531 "128K Bytes", /* 12 */
2532 "256K Bytes", /* 13 */
2533 "96K Bytes", /* 14 */
2534 "512K Bytes", /* 15 */
2538 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2539 { 0x19, "AT91SAM9xx Series" },
2540 { 0x29, "AT91SAM9XExx Series" },
2541 { 0x34, "AT91x34 Series" },
2542 { 0x37, "CAP7 Series" },
2543 { 0x39, "CAP9 Series" },
2544 { 0x3B, "CAP11 Series" },
2545 { 0x40, "AT91x40 Series" },
2546 { 0x42, "AT91x42 Series" },
2547 { 0x55, "AT91x55 Series" },
2548 { 0x60, "AT91SAM7Axx Series" },
2549 { 0x61, "AT91SAM7AQxx Series" },
2550 { 0x63, "AT91x63 Series" },
2551 { 0x70, "AT91SAM7Sxx Series" },
2552 { 0x71, "AT91SAM7XCxx Series" },
2553 { 0x72, "AT91SAM7SExx Series" },
2554 { 0x73, "AT91SAM7Lxx Series" },
2555 { 0x75, "AT91SAM7Xxx Series" },
2556 { 0x76, "AT91SAM7SLxx Series" },
2557 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2558 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2559 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2560 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2561 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2562 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2563 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2564 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2565 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2566 { 0x92, "AT91x92 Series" },
2567 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2568 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2569 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2570 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2571 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2572 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2573 { 0xA5, "ATSAM5A" },
2574 { 0xF0, "AT75Cxx Series" },
2578 static const char *const nvptype
[] = {
2580 "romless or onchip flash", /* 1 */
2581 "embedded flash memory",/* 2 */
2582 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2583 "sram emulating flash", /* 4 */
2589 static const char *_yes_or_no(uint32_t v
)
2597 static const char *const _rc_freq
[] = {
2598 "4 MHz", "8 MHz", "12 MHz", "reserved"
2601 static void sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
2606 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
2607 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2608 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
2609 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2610 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
2611 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2612 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
2613 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2615 pChip
->cfg
.rc_freq
= 0;
2619 pChip
->cfg
.rc_freq
= 0;
2622 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2625 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2628 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2633 v
= sam3_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
2634 LOG_USER("(startup clks, time= %f uSecs)",
2635 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
2636 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
2637 LOG_USER("(mainosc source: %s)",
2638 v
? "external xtal" : "internal RC");
2640 v
= sam3_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
2641 LOG_USER("(clock failure enabled: %s)",
2645 static void sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
2651 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
2654 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
2655 LOG_USER("%s", eproc_names
[v
]);
2657 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
2658 LOG_USER("%s", nvpsize
[v
]);
2660 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
2661 LOG_USER("%s", nvpsize2
[v
]);
2663 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
2664 LOG_USER("%s", sramsize
[v
]);
2666 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
2668 for (x
= 0; archnames
[x
].name
; x
++) {
2669 if (v
== archnames
[x
].value
) {
2670 cp
= archnames
[x
].name
;
2677 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2678 LOG_USER("%s", nvptype
[v
]);
2680 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2681 LOG_USER("(exists: %s)", _yes_or_no(v
));
2684 static void sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
2688 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2689 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2691 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2693 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2694 pChip
->cfg
.mainosc_freq
= v
;
2696 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
2698 (uint32_t)(pChip
->cfg
.slow_freq
/ 1000),
2699 (uint32_t)(pChip
->cfg
.slow_freq
% 1000));
2702 static void sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2704 uint32_t mula
, diva
;
2706 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2708 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2710 pChip
->cfg
.plla_freq
= 0;
2712 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2714 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2715 else if (diva
>= 1) {
2716 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2717 LOG_USER("\tPLLA Freq: %3.03f MHz",
2718 _tomhz(pChip
->cfg
.plla_freq
));
2722 static void sam3_explain_mckr(struct sam3_chip
*pChip
)
2724 uint32_t css
, pres
, fin
= 0;
2726 const char *cp
= NULL
;
2728 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2731 fin
= pChip
->cfg
.slow_freq
;
2735 fin
= pChip
->cfg
.mainosc_freq
;
2739 fin
= pChip
->cfg
.plla_freq
;
2743 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2744 fin
= 480 * 1000 * 1000;
2748 cp
= "upll (*ERROR* UPLL is disabled)";
2756 LOG_USER("%s (%3.03f Mhz)",
2759 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2760 switch (pres
& 0x07) {
2763 cp
= "selected clock";
2797 LOG_USER("(%s)", cp
);
2799 /* sam3 has a *SINGLE* clock - */
2800 /* other at91 series parts have divisors for these. */
2801 pChip
->cfg
.cpu_freq
= fin
;
2802 pChip
->cfg
.mclk_freq
= fin
;
2803 pChip
->cfg
.fclk_freq
= fin
;
2804 LOG_USER("\t\tResult CPU Freq: %3.03f",
2809 static struct sam3_chip
*target2sam3(struct target
*pTarget
)
2811 struct sam3_chip
*pChip
;
2813 if (pTarget
== NULL
)
2816 pChip
= all_sam3_chips
;
2818 if (pChip
->target
== pTarget
)
2819 break; /* return below */
2821 pChip
= pChip
->next
;
2827 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2829 /* this function exists to help */
2830 /* keep funky offsetof() errors */
2831 /* and casting from causing bugs */
2833 /* By using prototypes - we can detect what would */
2834 /* be casting errors. */
2836 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
2840 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2842 NAME), # NAME, FUNC }
2843 static const struct sam3_reg_list sam3_all_regs
[] = {
2844 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2845 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2846 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2847 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2848 SAM3_ENTRY(PMC_FSMR
, NULL
),
2849 SAM3_ENTRY(PMC_FSPR
, NULL
),
2850 SAM3_ENTRY(PMC_IMR
, NULL
),
2851 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2852 SAM3_ENTRY(PMC_PCK0
, NULL
),
2853 SAM3_ENTRY(PMC_PCK1
, NULL
),
2854 SAM3_ENTRY(PMC_PCK2
, NULL
),
2855 SAM3_ENTRY(PMC_PCSR
, NULL
),
2856 SAM3_ENTRY(PMC_SCSR
, NULL
),
2857 SAM3_ENTRY(PMC_SR
, NULL
),
2858 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2859 SAM3_ENTRY(CHIPID_CIDR2
, sam3_explain_chipid_cidr
),
2860 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2861 SAM3_ENTRY(CHIPID_EXID2
, NULL
),
2862 /* TERMINATE THE LIST */
2867 static struct sam3_bank_private
*get_sam3_bank_private(struct flash_bank
*bank
)
2869 return bank
->driver_priv
;
2873 * Given a pointer to where it goes in the structure,
2874 * determine the register name, address from the all registers table.
2876 static const struct sam3_reg_list
*sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2878 const struct sam3_reg_list
*pReg
;
2880 pReg
= &(sam3_all_regs
[0]);
2881 while (pReg
->name
) {
2882 uint32_t *pPossible
;
2884 /* calculate where this one go.. */
2885 /* it is "possibly" this register. */
2887 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2889 /* well? Is it this register */
2890 if (pPossible
== goes_here
) {
2898 /* This is *TOTAL*PANIC* - we are totally screwed. */
2899 LOG_ERROR("INVALID SAM3 REGISTER");
2903 static int sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2905 const struct sam3_reg_list
*pReg
;
2908 pReg
= sam3_GetReg(pChip
, goes_here
);
2912 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2913 if (r
!= ERROR_OK
) {
2914 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2915 pReg
->name
, (unsigned)(pReg
->address
), r
);
2920 static int sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2923 const struct sam3_reg_list
*pReg
;
2925 pReg
= &(sam3_all_regs
[0]);
2926 while (pReg
->name
) {
2927 r
= sam3_ReadThisReg(pChip
,
2928 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2929 if (r
!= ERROR_OK
) {
2930 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2931 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2937 /* Chip identification register
2939 * Unfortunately, the chip identification register is not at
2940 * a constant address across all of the SAM3 series'. As a
2941 * consequence, a simple heuristic is used to find where it's
2944 * If the contents at the first address is zero, then we know
2945 * that the second address is where the chip id register is.
2946 * We can deduce this because for those SAM's that have the
2947 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2948 * located in the memory map of the Power Management Controller
2949 * (PMC). Furthermore, the address is not used by the PMC.
2950 * So when read, the memory controller returns zero.*/
2951 if (pChip
->cfg
.CHIPID_CIDR
== 0) {
2952 /*Put the correct CIDR and EXID values in the pChip structure */
2953 pChip
->cfg
.CHIPID_CIDR
= pChip
->cfg
.CHIPID_CIDR2
;
2954 pChip
->cfg
.CHIPID_EXID
= pChip
->cfg
.CHIPID_EXID2
;
2959 static int sam3_GetInfo(struct sam3_chip
*pChip
)
2961 const struct sam3_reg_list
*pReg
;
2964 pReg
= &(sam3_all_regs
[0]);
2965 while (pReg
->name
) {
2966 /* display all regs */
2967 LOG_DEBUG("Start: %s", pReg
->name
);
2968 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2969 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
2974 if (pReg
->explain_func
)
2975 (*(pReg
->explain_func
))(pChip
);
2976 LOG_DEBUG("End: %s", pReg
->name
);
2979 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2980 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2981 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2982 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2983 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2985 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
,
2986 pChip
->cfg
.unique_id
[0],
2987 pChip
->cfg
.unique_id
[1],
2988 pChip
->cfg
.unique_id
[2],
2989 pChip
->cfg
.unique_id
[3]);
2994 static int sam3_erase_check(struct flash_bank
*bank
)
2999 if (bank
->target
->state
!= TARGET_HALTED
) {
3000 LOG_ERROR("Target not halted");
3001 return ERROR_TARGET_NOT_HALTED
;
3003 if (0 == bank
->num_sectors
) {
3004 LOG_ERROR("Target: not supported/not probed");
3008 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
3009 for (x
= 0; x
< bank
->num_sectors
; x
++)
3010 bank
->sectors
[x
].is_erased
= 1;
3016 static int sam3_protect_check(struct flash_bank
*bank
)
3021 struct sam3_bank_private
*pPrivate
;
3024 if (bank
->target
->state
!= TARGET_HALTED
) {
3025 LOG_ERROR("Target not halted");
3026 return ERROR_TARGET_NOT_HALTED
;
3029 pPrivate
= get_sam3_bank_private(bank
);
3031 LOG_ERROR("no private for this bank?");
3034 if (!(pPrivate
->probed
))
3035 return ERROR_FLASH_BANK_NOT_PROBED
;
3037 r
= FLASHD_GetLockBits(pPrivate
, &v
);
3038 if (r
!= ERROR_OK
) {
3039 LOG_DEBUG("Failed: %d", r
);
3043 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
3044 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
3049 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
3051 struct sam3_chip
*pChip
;
3053 pChip
= all_sam3_chips
;
3055 /* is this an existing chip? */
3057 if (pChip
->target
== bank
->target
)
3059 pChip
= pChip
->next
;
3063 /* this is a *NEW* chip */
3064 pChip
= calloc(1, sizeof(struct sam3_chip
));
3066 LOG_ERROR("NO RAM!");
3069 pChip
->target
= bank
->target
;
3070 /* insert at head */
3071 pChip
->next
= all_sam3_chips
;
3072 all_sam3_chips
= pChip
;
3073 pChip
->target
= bank
->target
;
3074 /* assumption is this runs at 32khz */
3075 pChip
->cfg
.slow_freq
= 32768;
3079 switch (bank
->base
) {
3081 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3082 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3083 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3084 ((unsigned int)(bank
->base
)),
3085 ((unsigned int)(FLASH_BANK0_BASE_U
)),
3086 ((unsigned int)(FLASH_BANK1_BASE_U
)),
3087 ((unsigned int)(FLASH_BANK_BASE_S
)),
3088 ((unsigned int)(FLASH_BANK_BASE_N
)),
3089 ((unsigned int)(FLASH_BANK0_BASE_AX
)),
3090 ((unsigned int)(FLASH_BANK1_BASE_256K_AX
)),
3091 ((unsigned int)(FLASH_BANK1_BASE_512K_AX
)));
3095 /* at91sam3s and at91sam3n series only has bank 0*/
3096 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3097 case FLASH_BANK_BASE_S
:
3098 case FLASH_BANK0_BASE_U
:
3099 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
3100 bank
->bank_number
= 0;
3101 pChip
->details
.bank
[0].pChip
= pChip
;
3102 pChip
->details
.bank
[0].pBank
= bank
;
3105 /* Bank 1 of at91sam3u or at91sam3ax series */
3106 case FLASH_BANK1_BASE_U
:
3107 case FLASH_BANK1_BASE_256K_AX
:
3108 case FLASH_BANK1_BASE_512K_AX
:
3109 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
3110 bank
->bank_number
= 1;
3111 pChip
->details
.bank
[1].pChip
= pChip
;
3112 pChip
->details
.bank
[1].pBank
= bank
;
3116 /* we initialize after probing. */
3120 static int sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
3122 const struct sam3_chip_details
*pDetails
;
3123 struct sam3_chip
*pChip
;
3124 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
3128 pDetails
= all_sam3_details
;
3129 while (pDetails
->name
) {
3130 /* Compare cidr without version bits */
3131 if (((pDetails
->chipid_cidr
^ pPrivate
->pChip
->cfg
.CHIPID_CIDR
) & 0xFFFFFFE0) == 0)
3136 if (pDetails
->name
== NULL
) {
3137 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3138 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
3139 /* Help the victim, print details about the chip */
3140 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
3141 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
3142 sam3_explain_chipid_cidr(pPrivate
->pChip
);
3146 /* DANGER: THERE ARE DRAGONS HERE */
3148 /* get our pChip - it is going */
3149 /* to be over-written shortly */
3150 pChip
= pPrivate
->pChip
;
3152 /* Note that, in reality: */
3154 /* pPrivate = &(pChip->details.bank[0]) */
3155 /* or pPrivate = &(pChip->details.bank[1]) */
3158 /* save the "bank" pointers */
3159 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++)
3160 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
3162 /* Overwrite the "details" structure. */
3163 memcpy(&(pPrivate
->pChip
->details
),
3165 sizeof(pPrivate
->pChip
->details
));
3167 /* now fix the ghosted pointers */
3168 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3169 pChip
->details
.bank
[x
].pChip
= pChip
;
3170 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
3173 /* update the *BANK*SIZE* */
3179 static int _sam3_probe(struct flash_bank
*bank
, int noise
)
3183 struct sam3_bank_private
*pPrivate
;
3186 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
3187 if (bank
->target
->state
!= TARGET_HALTED
) {
3188 LOG_ERROR("Target not halted");
3189 return ERROR_TARGET_NOT_HALTED
;
3192 pPrivate
= get_sam3_bank_private(bank
);
3194 LOG_ERROR("Invalid/unknown bank number");
3198 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
3203 if (pPrivate
->pChip
->probed
)
3204 r
= sam3_GetInfo(pPrivate
->pChip
);
3206 r
= sam3_GetDetails(pPrivate
);
3210 /* update the flash bank size */
3211 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3212 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
3213 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
3218 if (bank
->sectors
== NULL
) {
3219 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
3220 if (bank
->sectors
== NULL
) {
3221 LOG_ERROR("No memory!");
3224 bank
->num_sectors
= pPrivate
->nsectors
;
3226 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
3227 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
3228 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
3229 /* mark as unknown */
3230 bank
->sectors
[x
].is_erased
= -1;
3231 bank
->sectors
[x
].is_protected
= -1;
3235 pPrivate
->probed
= 1;
3237 r
= sam3_protect_check(bank
);
3241 LOG_DEBUG("Bank = %d, nbanks = %d",
3242 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
3243 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
3244 /* read unique id, */
3245 /* it appears to be associated with the *last* flash bank. */
3246 FLASHD_ReadUniqueID(pPrivate
);
3252 static int sam3_probe(struct flash_bank
*bank
)
3254 return _sam3_probe(bank
, 1);
3257 static int sam3_auto_probe(struct flash_bank
*bank
)
3259 return _sam3_probe(bank
, 0);
3262 static int sam3_erase(struct flash_bank
*bank
, int first
, int last
)
3264 struct sam3_bank_private
*pPrivate
;
3268 if (bank
->target
->state
!= TARGET_HALTED
) {
3269 LOG_ERROR("Target not halted");
3270 return ERROR_TARGET_NOT_HALTED
;
3273 r
= sam3_auto_probe(bank
);
3274 if (r
!= ERROR_OK
) {
3275 LOG_DEBUG("Here,r=%d", r
);
3279 pPrivate
= get_sam3_bank_private(bank
);
3280 if (!(pPrivate
->probed
))
3281 return ERROR_FLASH_BANK_NOT_PROBED
;
3283 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
3286 return FLASHD_EraseEntireBank(pPrivate
);
3288 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3292 static int sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
3294 struct sam3_bank_private
*pPrivate
;
3298 if (bank
->target
->state
!= TARGET_HALTED
) {
3299 LOG_ERROR("Target not halted");
3300 return ERROR_TARGET_NOT_HALTED
;
3303 pPrivate
= get_sam3_bank_private(bank
);
3304 if (!(pPrivate
->probed
))
3305 return ERROR_FLASH_BANK_NOT_PROBED
;
3308 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
3310 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
3311 LOG_DEBUG("End: r=%d", r
);
3317 static int sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
3322 adr
= pagenum
* pPrivate
->page_size
;
3323 adr
+= pPrivate
->base_address
;
3325 r
= target_read_memory(pPrivate
->pChip
->target
,
3327 4, /* THIS*MUST*BE* in 32bit values */
3328 pPrivate
->page_size
/ 4,
3331 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3332 (unsigned int)(adr
));
3336 static int sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, const uint8_t *buf
)
3340 uint32_t fmr
; /* EEFC Flash Mode Register */
3343 adr
= pagenum
* pPrivate
->page_size
;
3344 adr
+= pPrivate
->base_address
;
3346 /* Get flash mode register value */
3347 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
3349 LOG_DEBUG("Error Read failed: read flash mode register");
3351 /* Clear flash wait state field */
3354 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3355 fmr
|= (pPrivate
->flash_wait_states
<< 8);
3357 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
3358 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
3360 LOG_DEBUG("Error Write failed: set flash mode register");
3362 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
3363 r
= target_write_memory(pPrivate
->pChip
->target
,
3365 4, /* THIS*MUST*BE* in 32bit values */
3366 pPrivate
->page_size
/ 4,
3368 if (r
!= ERROR_OK
) {
3369 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3370 (unsigned int)(adr
));
3374 r
= EFC_PerformCommand(pPrivate
,
3375 /* send Erase & Write Page */
3381 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3382 (unsigned int)(adr
));
3383 if (status
& (1 << 2)) {
3384 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
3387 if (status
& (1 << 1)) {
3388 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
3394 static int sam3_write(struct flash_bank
*bank
,
3395 const uint8_t *buffer
,
3403 unsigned page_offset
;
3404 struct sam3_bank_private
*pPrivate
;
3405 uint8_t *pagebuffer
;
3407 /* incase we bail further below, set this to null */
3410 /* ignore dumb requests */
3416 if (bank
->target
->state
!= TARGET_HALTED
) {
3417 LOG_ERROR("Target not halted");
3418 r
= ERROR_TARGET_NOT_HALTED
;
3422 pPrivate
= get_sam3_bank_private(bank
);
3423 if (!(pPrivate
->probed
)) {
3424 r
= ERROR_FLASH_BANK_NOT_PROBED
;
3428 if ((offset
+ count
) > pPrivate
->size_bytes
) {
3429 LOG_ERROR("Flash write error - past end of bank");
3430 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3431 (unsigned int)(offset
),
3432 (unsigned int)(count
),
3433 (unsigned int)(pPrivate
->size_bytes
));
3438 pagebuffer
= malloc(pPrivate
->page_size
);
3440 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
3445 /* what page do we start & end in? */
3446 page_cur
= offset
/ pPrivate
->page_size
;
3447 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
3449 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
3450 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
3452 /* Special case: all one page */
3455 /* (1) non-aligned start */
3456 /* (2) body pages */
3457 /* (3) non-aligned end. */
3459 /* Handle special case - all one page. */
3460 if (page_cur
== page_end
) {
3461 LOG_DEBUG("Special case, all in one page");
3462 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3466 page_offset
= (offset
& (pPrivate
->page_size
-1));
3467 memcpy(pagebuffer
+ page_offset
,
3471 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3478 /* non-aligned start */
3479 page_offset
= offset
& (pPrivate
->page_size
- 1);
3481 LOG_DEBUG("Not-Aligned start");
3482 /* read the partial */
3483 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3487 /* over-write with new data */
3488 n
= (pPrivate
->page_size
- page_offset
);
3489 memcpy(pagebuffer
+ page_offset
,
3493 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3503 /* By checking that offset is correct here, we also
3504 fix a clang warning */
3505 assert(offset
% pPrivate
->page_size
== 0);
3507 /* intermediate large pages */
3508 /* also - the final *terminal* */
3509 /* if that terminal page is a full page */
3510 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3511 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3513 while ((page_cur
< page_end
) &&
3514 (count
>= pPrivate
->page_size
)) {
3515 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
3518 count
-= pPrivate
->page_size
;
3519 buffer
+= pPrivate
->page_size
;
3523 /* terminal partial page? */
3525 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3526 /* we have a partial page */
3527 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3530 /* data goes at start */
3531 memcpy(pagebuffer
, buffer
, count
);
3532 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3544 COMMAND_HANDLER(sam3_handle_info_command
)
3546 struct sam3_chip
*pChip
;
3547 pChip
= get_current_sam3(CMD_CTX
);
3554 /* bank0 must exist before we can do anything */
3555 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3558 command_print(CMD_CTX
,
3559 "Please define bank %d via command: flash bank %s ... ",
3561 at91sam3_flash
.name
);
3565 /* if bank 0 is not probed, then probe it */
3566 if (!(pChip
->details
.bank
[0].probed
)) {
3567 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3571 /* above guarantees the "chip details" structure is valid */
3572 /* and thus, bank private areas are valid */
3573 /* and we have a SAM3 chip, what a concept! */
3575 /* auto-probe other banks, 0 done above */
3576 for (x
= 1; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3577 /* skip banks not present */
3578 if (!(pChip
->details
.bank
[x
].present
))
3581 if (pChip
->details
.bank
[x
].pBank
== NULL
)
3584 if (pChip
->details
.bank
[x
].probed
)
3587 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3592 r
= sam3_GetInfo(pChip
);
3593 if (r
!= ERROR_OK
) {
3594 LOG_DEBUG("Sam3Info, Failed %d", r
);
3601 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3605 struct sam3_chip
*pChip
;
3607 pChip
= get_current_sam3(CMD_CTX
);
3611 if (pChip
->target
->state
!= TARGET_HALTED
) {
3612 LOG_ERROR("sam3 - target not halted");
3613 return ERROR_TARGET_NOT_HALTED
;
3616 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3617 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3618 at91sam3_flash
.name
);
3621 if (!pChip
->details
.bank
[0].probed
) {
3622 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3629 return ERROR_COMMAND_SYNTAX_ERROR
;
3638 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
3642 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3648 if (0 == strcmp("show", CMD_ARGV
[0])) {
3652 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
3653 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3656 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3660 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3661 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3662 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3665 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3666 return ERROR_COMMAND_SYNTAX_ERROR
;
3671 command_print(CMD_CTX
, "Missing GPNVM number");
3672 return ERROR_COMMAND_SYNTAX_ERROR
;
3675 if (0 == strcmp("set", CMD_ARGV
[0]))
3676 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3677 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3678 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
3679 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3681 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3682 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3687 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3689 struct sam3_chip
*pChip
;
3691 pChip
= get_current_sam3(CMD_CTX
);
3703 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3705 /* absurd slow clock of 200Khz? */
3706 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3707 return ERROR_COMMAND_SYNTAX_ERROR
;
3709 pChip
->cfg
.slow_freq
= v
;
3714 command_print(CMD_CTX
, "Too many parameters");
3715 return ERROR_COMMAND_SYNTAX_ERROR
;
3718 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3719 (int)(pChip
->cfg
.slow_freq
/ 1000),
3720 (int)(pChip
->cfg
.slow_freq
% 1000));
3724 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3727 .handler
= sam3_handle_gpnvm_command
,
3728 .mode
= COMMAND_EXEC
,
3729 .usage
= "[('clr'|'set'|'show') bitnum]",
3730 .help
= "Without arguments, shows all bits in the gpnvm "
3731 "register. Otherwise, clears, sets, or shows one "
3732 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3736 .handler
= sam3_handle_info_command
,
3737 .mode
= COMMAND_EXEC
,
3738 .help
= "Print information about the current at91sam3 chip"
3739 "and its flash configuration.",
3743 .handler
= sam3_handle_slowclk_command
,
3744 .mode
= COMMAND_EXEC
,
3745 .usage
= "[clock_hz]",
3746 .help
= "Display or set the slowclock frequency "
3747 "(default 32768 Hz).",
3749 COMMAND_REGISTRATION_DONE
3751 static const struct command_registration at91sam3_command_handlers
[] = {
3754 .mode
= COMMAND_ANY
,
3755 .help
= "at91sam3 flash command group",
3757 .chain
= at91sam3_exec_command_handlers
,
3759 COMMAND_REGISTRATION_DONE
3762 struct flash_driver at91sam3_flash
= {
3764 .commands
= at91sam3_command_handlers
,
3765 .flash_bank_command
= sam3_flash_bank_command
,
3766 .erase
= sam3_erase
,
3767 .protect
= sam3_protect
,
3768 .write
= sam3_write
,
3769 .read
= default_flash_read
,
3770 .probe
= sam3_probe
,
3771 .auto_probe
= sam3_auto_probe
,
3772 .erase_check
= sam3_erase_check
,
3773 .protect_check
= sam3_protect_check
,
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