target/riscv: Free registers to avoid memory leak 85/4885/3
authorMarc Schink <openocd-dev@marcschink.de>
Mon, 1 Apr 2019 11:47:17 +0000 (13:47 +0200)
committerTomas Vanek <vanekt@fbl.cz>
Wed, 10 Apr 2019 15:37:21 +0000 (16:37 +0100)
commitd5936dc688bedf54848a29b7c171ef47deb2bf91
treefba2727f9d1c98d7d757fdd59b1ee32e6b489ef1
parent6aae614cc2072e0d45bc32213595286ccbd32248
target/riscv: Free registers to avoid memory leak

Tested with SiFive HiFive1 development board.

Change-Id: I96a9a528057fcf9fc54d3da46a672d2cd54c3d5f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4885
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
src/target/riscv/riscv.c