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topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc 06/1806/4
authorSergio Chico <sergio.chico@gmail.com>
Sun, 10 Nov 2013 15:03:40 +0000 (16:03 +0100)
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>
Sat, 14 Dec 2013 21:53:16 +0000 (21:53 +0000)
commit93a3a82e49e7d1df855095dd541e9c04ad7823bc
treea26d5939605b3c86bb3407bf683da241eb55757ftree | snapshot
parent2d64cf92aed12fc785afe8bd8bd759ae28a6b2ebcommit | diff
topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc

This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
doc/openocd.texi diff | blob | history
src/target/openrisc/Makefile.am diff | blob | history
src/target/openrisc/or1k.c diff | blob | history
src/target/openrisc/or1k_tap.h diff | blob | history
src/target/openrisc/or1k_tap_xilinx_bscan.c [new file with mode: 0644] blob
tcl/board/or1k_generic.cfg diff | blob | history
tcl/target/or1k.cfg diff | blob | history
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