at91samd: handle reset run/halt in DSU

[openocd.git] / tcl / target / stm32f1x.cfg

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 31c2c5efdf65b850c8d1b6753624d03a52a55adf..bd02e95b06057953cf4ba54f7ef46ba105f82a58 100644 (file)
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,11 +12,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f1x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 4kB (as found on some STM32F100s)
@@ -90,8 +87,23 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
+reset_config srst_nogate
+
 if {![using_hla]} {
     # if srst is not fitted use SYSRESETREQ to
     # perform a soft reset
     cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+       #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xE0042004 0x00000020 0
+}