# CPU TAP ID 0x1ba00477 for early Sandstorm parts
# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
-# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
# ... we'll ignore the JTAG version field, rather than list every
# chip revision that turns up.
if { [info exists CPUTAPID] } {
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
- # default to 8K working area
- set _WORKAREASIZE 0x2000
+ # default to 2K working area
+ set _WORKAREASIZE 0x800
}
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
# 8K working area at base of ram, not backed up
#
$_TARGETNAME configure -event reset-start {
adapter_khz 500
- #
+ #
# When nRST is asserted on most Stellaris devices, it clears some of
# the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
# and OpenOCD depends on those TRMs. So we won't use SRST on those
if {$device_class == 0 || $device_class == 1 ||
$device_class == 3 || $device_class == 5} {
# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
- cortex_m3 reset_config sysresetreq
+ cortex_m reset_config sysresetreq
} else {
# Tempest and Firestorm default to using NVIC VECTRESET
# peripherals will need reseting manually, see proc reset_peripherals
- cortex_m3 reset_config vectreset
+ cortex_m reset_config vectreset
# reset peripherals, based on code in
# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf