lpc1768: turn down the jtag clock

[openocd.git] / tcl / target / lpc1768.cfg

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index fc00d78def6cc91faea2cfecddbba38ea1c822f2..07c5ab8377d5889d7337585d79d9c69f26bba3ee 100644 (file)
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -47,8 +47,33 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
        lpc1700 $_CCLK calc_checksum
 
-# JTAG clock should be CCLK/6 (unless using adaptive clocking)
-# CCLK is 4 MHz after reset, and until board-specific code (like
-# a reset-init handler) speeds it up.
-jtag_rclk [ expr 4000 / 6 ]
-$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6]  }
+# Although rclk "appears to work", it turns out that this yields
+# 4MHz whereas the "correct" rate is CCLK/6, which is not what
+# you get with rclk.
+#
+# Also, crank down the frequency further as we're running of an
+# RC oscillator instead of crystal.
+#
+# Setting up XTAL in the reset-init sequence could be worth 
+# the effort if you need to program the flash which is pretty
+# big on these devices.
+#
+jtag_khz 100
+
+$_TARGETNAME configure -event reset-init {
+       # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+       # "User Flash Mode" where interrupt vectors are _not_ remapped,
+       # and reside in flash instead).
+       #
+       # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+       # Bit Symbol Value Description Reset
+       # value
+       # 0 MAP Memory map control. 0
+       # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+       # 1 User mode. The on-chip Flash memory is mapped to address 0.
+       # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+       #
+       # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+       mww 0x400FC040 0x01
+}