more tcl/{board,target} cleanup

[openocd.git] / tcl / target / ar71xx.cfg

diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 213048ae8f0a9da75c25a766aff2d03c9bd9cb98..20383315cdbc43ca32b4eaee2328515513acdafc 100644 (file)
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -10,7 +10,7 @@ set CHIPNAME ar71xx
 
 jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
 
-set TARGETNAME [format "%s.cpu" $CHIPNAME]
+set TARGETNAME $CHIPNAME.cpu
 target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
 
 $TARGETNAME configure -event reset-halt-post {
@@ -29,11 +29,11 @@ $TARGETNAME configure -event reset-init {
        mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass
        mww 0xb8050008 1                # set clock_switch bit
        sleep 1                         # wait for lock
-       
+
        # Setup DDR config and flash mapping
        mww 0xb8000000 0xefbc8cd0       # DDR cfg cdl val (rst: 0x5bfc8d0)
        mww 0xb8000004 0x8e7156a2       # DDR cfg2 cdl val (rst: 0x80d106a8)
-       
+
        mww 0xb8000010 8                # force precharge all banks
        mww 0xb8000010 1                # force EMRS update cycle
        mww 0xb800000c 0                # clr ext. mode register
@@ -47,7 +47,7 @@ $TARGETNAME configure -event reset-init {
        mww 0xb8000020 0
        mww 0xb8000024 0
        mww 0xb8000028 0
-}      
+}
 
 # setup working area somewhere in RAM
 $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000