Glyn Tonga2: Faster JTAG speed after CPU/RAM init.

[openocd.git] / tcl / board / spear310evb20.cfg

diff --git a/tcl/board/spear310evb20.cfg b/tcl/board/spear310evb20.cfg
index 70783f5b9903689e3a197ffb1dae95a63dc9de2c..c45873ca9923ef724988a5cfe8a1ac3091d39052 100644 (file)
--- a/tcl/board/spear310evb20.cfg
+++ b/tcl/board/spear310evb20.cfg
@@ -8,13 +8,12 @@
 # The standard board has JTAG SRST not connected.
 # This script targets such boards using quirky code to bypass the issue.
 #
-# Check ST Application Note (FIXME: put reference) on how to fix SRST on
+# Check ST Application Note AN3321 on how to fix SRST on
 # the board, then use the script board/spear310evb20_mod.cfg
 
 
 source [find mem_helper.tcl]
 source [find target/spear3xx.cfg]
-source [find chip/st/spear/spear310.tcl]
 source [find chip/st/spear/spear3xx_ddr.tcl]
 source [find chip/st/spear/spear3xx.tcl]
 
@@ -27,7 +26,7 @@ flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
 
 # Serial NOR on SMI CS0. 8Mbyte.
 set _FLASHNAME1 $_CHIPNAME.snor
-flash bank $_FLASHNAME1 spearsmi 0xf8000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
 
 if { [info exists BOARD_HAS_SRST] } {
        # Modified board has SRST on JTAG connector
@@ -42,7 +41,7 @@ if { [info exists BOARD_HAS_SRST] } {
 $_TARGETNAME configure -event reset-init { spear310evb20_init }
 
 proc spear310evb20_init {} {
-       reg pc 0xffff0020       # loop forever
+       reg pc 0xffff0020       ;# loop forever
 
        sp3xx_clock_default
        sp3xx_common_init