rename jtag_nsrst_delay as adapter_nsrst_delay

[openocd.git] / tcl / board / pxa255_sst.cfg

diff --git a/tcl/board/pxa255_sst.cfg b/tcl/board/pxa255_sst.cfg
index 76ae4c93bbe8436d22e240b605b7f56939e299c2..44f34ca1bb86223d651bc1e2b39ddc63d4fbbfda 100644 (file)
--- a/tcl/board/pxa255_sst.cfg
+++ b/tcl/board/pxa255_sst.cfg
@@ -1,7 +1,7 @@
 # A PXA255 test board with SST 39LF400A flash
 #
 # At reset the memory map is as follows. Note that
-# the memory map changes later on as the application 
+# the memory map changes later on as the application
 # starts...
 #
 # RAM at 0x4000000
@@ -10,10 +10,11 @@
 source [find target/pxa255.cfg]
 
 # Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
 
 # flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
-flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
 
 proc pxa255_sst_init {} {
        xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
@@ -92,7 +93,7 @@ $_TARGETNAME configure -event reset-init {pxa255_sst_init}
 
 reset_config trst_and_srst
 
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 #xscale debug_handler 0  0xFFFF0800      # debug handler base address