STLINK: add stlink v1 configuration

[openocd.git] / tcl / board / csb732.cfg

diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 9022fafcb15ec493b44d6bbc157548cd72beaff4..4d6f0e489e6fe0e44c4d95e7ac82f114151ec055 100644 (file)
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -3,7 +3,7 @@ source [find target/imx35.cfg]
 
 # Determined by trial and error
 reset_config trst_and_srst combined
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 $_TARGETNAME configure -event gdb-attach { reset init }
@@ -19,13 +19,13 @@ proc csb732_init { } {
        # We assume the interpreter latency is enough.
 
        # Allow access to all coprocessors
-       mcr 15 0 15 1 0 0x2001
+       arm mcr 15 0 15 1 0 0x2001
 
        # Disable MMU, caches, write buffer
-       mcr 15 0 1 0 0 0x78
+       arm mcr 15 0 1 0 0 0x78
 
        # Grant manager access to all domains
-       mcr 15 0 3 0 0 0xFFFFFFFF
+       arm mcr 15 0 3 0 0 0xFFFFFFFF
 
        # Set ARM clock to 532 MHz, AHB to 133 MHz
        mww 0x53F80004 0x1000