telnet_server: review unused symbols

[openocd.git] / tcl / board / at91sam9g20-ek.cfg

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 00ab7fafaa0bd0b615d483123a9795a6cb59bd53..c3eb952c787e8ad1b148475745985bf6c5f06137 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -5,6 +5,10 @@
 #                                                                                              #
 #################################################################################################
 
+# FIXME use some standard target config, maybe create one from this
+#
+#      source [find target/...cfg]
+
 # Define basic characteristics for the CPU.  The AT91SAM9G20 processor is a subtle variant of
 # the AT91SAM9260 and shares the same tap ID as it.
 
@@ -24,25 +28,26 @@ reset_config trst_and_srst
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-# Use caution changing the delays listed below.  These seem to be affected by the board and type of
-# debugger dongle.  A value of 200 ms seems to work reliably for the configuration listed in the file header above.
+# Use caution changing the delays listed below.  These seem to be
+# affected by the board and type of JTAG adapter.  A value of 200 ms seems
+# to work reliably for the configuration listed in the file header above.
 
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
 jtag_rclk 5
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
 # Both areas are 16 kB long.
 
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
 
 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
 # AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
@@ -72,7 +77,7 @@ proc at91sam9g20_init { } {
        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
 
-       jtag_khz 2                      # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+       adapter_khz 2                   # Slow-speed oscillator enabled at reset, so run jtag speed slow.
        halt                            # Make sure processor is halted, or error will result in following steps.
        mww 0xfffffd08 0xa5000501       # RSTC_MR : enable user reset.
        mww 0xfffffd44 0x00008000       # WDT_MR : disable watchdog.
@@ -107,7 +112,7 @@ proc at91sam9g20_init { } {
 
        # Switch over to adaptive clocking.
 
-       jtag_khz 0
+       adapter_khz 0
 
        # Enable faster DCC downloads.