tcl: fix typo and spelling

[openocd.git] / tcl / board / at91sam9g20-ek.cfg

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index deb4da1540cae3b47d99440d79c755d0920ac5db..9e0413a1963d4f22ca2827c1959dd2acbf1a3fcd 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -9,13 +9,9 @@
 #
 #      source [find target/...cfg]
 
-# Define basic characteristics for the CPU.  The AT91SAM9G20 processor is a subtle variant of
-# the AT91SAM9260 and shares the same tap ID as it.
+source [find target/at91sam9g20.cfg]
 
-set _CHIPNAME at91sam9g20
 set _FLASHTYPE nandflash_cs3
-set _ENDIAN little
-set _CPUTAPID 0x0792603f
 
 # Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
 # the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
@@ -23,31 +19,9 @@ set _CPUTAPID 0x0792603f
 
 reset_config srst_only
 
-# Set up the CPU and generate a new jtag tap for AT91SAM9G20.
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Use caution changing the delays listed below.  These seem to be
-# affected by the board and type of JTAG adapter.  A value of 200 ms seems
-# to work reliably for the configuration listed in the file header above.
-
-adapter_nsrst_delay 200
+adapter srst delay 200
 jtag_ntrst_delay 200
 
-# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
-
-jtag_rclk 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
-# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
-# Both areas are 16 kB long.
-
-#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
-
 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
 # AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
 # some powerful features, we want to have a special function that handles "reset init".  To do this we declare
@@ -80,7 +54,7 @@ proc at91sam9g20_reset_start { } {
        # jtag speed without causing GDB keep alive problem.
 
        arm7_9 fast_memory_access disable
-       adapter_khz 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+       adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
        halt                            ;# Make sure processor is halted, or error will result in following steps.
        wait_halt 10000
        mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
@@ -129,7 +103,7 @@ proc at91sam9g20_reset_init { } {
 
        # Switch over to adaptive clocking.
 
-       adapter_khz 0
+       adapter speed 0
 
        # Enable faster DCC downloads and memory accesses.
 
@@ -195,7 +169,7 @@ proc at91sam9g20_reset_init { } {
        #       TRC = 9 cycles
        #       TWR = 2 cycles
        #       9 column, 13 row, 4 banks
-       #       refresh equal to or less then 7.8 us for commerical/industrial rated devices
+       #       refresh equal to or less then 7.8 us for commercial/industrial rated devices
        #
        #       Thus SDRAM_CR = 0xa6339279
 
@@ -242,4 +216,3 @@ proc at91sam9g20_reset_init { } {
 
        mww 0xffffea04 0x0000039c
 }
-